ssb: add delay after PCI reset to fix SoC reboots
Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
This commit is contained in:
parent
61b559dea4
commit
f56d9e23b7
|
@ -357,6 +357,15 @@ static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
|
||||||
pcicore_write32(pc, SSB_PCICORE_SBTOPCI2,
|
pcicore_write32(pc, SSB_PCICORE_SBTOPCI2,
|
||||||
SSB_PCICORE_SBTOPCI_MEM | SSB_PCI_DMA);
|
SSB_PCICORE_SBTOPCI_MEM | SSB_PCI_DMA);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Accessing PCI config without a proper delay after devices reset (not
|
||||||
|
* GPIO reset) was causing reboots on WRT300N v1.0.
|
||||||
|
* Tested delay 850 us lowered reboot chance to 50-80%, 1000 us fixed it
|
||||||
|
* completely. Flushing all writes was also tested but with no luck.
|
||||||
|
*/
|
||||||
|
if (pc->dev->bus->chip_id == 0x4704)
|
||||||
|
usleep_range(1000, 2000);
|
||||||
|
|
||||||
/* Enable PCI bridge BAR0 prefetch and burst */
|
/* Enable PCI bridge BAR0 prefetch and burst */
|
||||||
val = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
|
val = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
|
||||||
ssb_extpci_write_config(pc, 0, 0, 0, PCI_COMMAND, &val, 2);
|
ssb_extpci_write_config(pc, 0, 0, 0, PCI_COMMAND, &val, 2);
|
||||||
|
|
Loading…
Reference in New Issue