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stmmac: update the driver documentation 

Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Giuseppe Cavallaro 2010-11-12 12:43:34 -08:00 committed by David S. Miller
parent c753796769
commit f5539b5bfa
1 changed files with 37 additions and 11 deletions
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48
Documentation/networking/stmmac.txt
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@ -7,7 +7,7 @@ This is the driver for the MAC 10/100/1000 on-chip Ethernet controllers
(Synopsys IP blocks); it has been fully tested on STLinux platforms. (Synopsys IP blocks); it has been fully tested on STLinux platforms.
Currently this network device driver is for all STM embedded MAC/GMAC Currently this network device driver is for all STM embedded MAC/GMAC
(7xxx SoCs). (7xxx SoCs). Other platforms start using it i.e. ARM SPEAr.
DWC Ether MAC 10/100/1000 Universal version 3.41a and DWC Ether MAC 10/100 DWC Ether MAC 10/100/1000 Universal version 3.41a and DWC Ether MAC 10/100
Universal version 4.0 have been used for developing the first code Universal version 4.0 have been used for developing the first code
@ -95,9 +95,14 @@ Several information came from the platform; please refer to the
driver's Header file in include/linux directory. driver's Header file in include/linux directory.
struct plat_stmmacenet_data { struct plat_stmmacenet_data {
int bus_id; int bus_id;
int pbl; int pbl;
int has_gmac; int clk_csr;
int has_gmac;
int enh_desc;
int tx_coe;
int bugged_jumbo;
int pmt;
void (*fix_mac_speed)(void *priv, unsigned int speed); void (*fix_mac_speed)(void *priv, unsigned int speed);
void (*bus_setup)(unsigned long ioaddr); void (*bus_setup)(unsigned long ioaddr);
#ifdef CONFIG_STM_DRIVERS #ifdef CONFIG_STM_DRIVERS
@ -114,6 +119,12 @@ Where:
registers (on STM platforms); registers (on STM platforms);
- has_gmac: GMAC core is on board (get it at run-time in the next step); - has_gmac: GMAC core is on board (get it at run-time in the next step);
- bus_id: bus identifier. - bus_id: bus identifier.
- tx_coe: core is able to perform the tx csum in HW.
- enh_desc: if sets the MAC will use the enhanced descriptor structure.
- clk_csr: CSR Clock range selection.
- bugged_jumbo: some HWs are not able to perform the csum in HW for
over-sized frames due to limited buffer sizes. Setting this
flag the csum will be done in SW on JUMBO frames.
struct plat_stmmacphy_data { struct plat_stmmacphy_data {
int bus_id; int bus_id;
@ -131,13 +142,28 @@ Where:
- interface: physical MII interface mode; - interface: physical MII interface mode;
- phy_reset: hook to reset HW function. - phy_reset: hook to reset HW function.
SOURCES:
- Kconfig
- Makefile
- stmmac_main.c: main network device driver;
- stmmac_mdio.c: mdio functions;
- stmmac_ethtool.c: ethtool support;
- stmmac_timer.[ch]: timer code used for mitigating the driver dma interrupts
Only tested on ST40 platforms based.
- stmmac.h: private driver structure;
- common.h: common definitions and VFTs;
- descs.h: descriptor structure definitions;
- dwmac1000_core.c: GMAC core functions;
- dwmac1000_dma.c: dma functions for the GMAC chip;
- dwmac1000.h: specific header file for the GMAC;
- dwmac100_core: MAC 100 core and dma code;
- dwmac100_dma.c: dma funtions for the MAC chip;
- dwmac1000.h: specific header file for the MAC;
- dwmac_lib.c: generic DMA functions shared among chips
- enh_desc.c: functions for handling enhanced descriptors
- norm_desc.c: functions for handling normal descriptors
TODO: TODO:
- Continue to make the driver more generic and suitable for other Synopsys - XGMAC controller is not supported.
Ethernet controllers used on other architectures (i.e. ARM).
- 10G controllers are not supported.
- MAC uses Normal descriptors and GMAC uses enhanced ones.
This is a limit that should be reviewed. MAC could want to
use the enhanced structure.
- Checksumming: Rx/Tx csum is done in HW in case of GMAC only.
- Review the timer optimisation code to use an embedded device that seems to be - Review the timer optimisation code to use an embedded device that seems to be
available in new chip generations. available in new chip generations.