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ARM: proc: add definition of cpu_reset for ARMv6 and ARMv7 cores 

This patch adds simple definitions of cpu_reset for ARMv6 and ARMv7
cores, which disable the MMU via the SCTLR.

Signed-off-by: Will Deacon <will.deacon@arm.com>
This commit is contained in:
Will Deacon 2011-06-06 12:27:34 +01:00
parent 14abd038a7
commit f4daf06fc2
2 changed files with 12 additions and 0 deletions
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5
arch/arm/mm/proc-v6.S
View File

@ -56,6 +56,11 @@ ENTRY(cpu_v6_proc_fin)
*/ */
.align 5 .align 5
ENTRY(cpu_v6_reset) ENTRY(cpu_v6_reset)
mrc p15, 0, r1, c1, c0, 0 @ ctrl register
bic r1, r1, #0x1 @ ...............m
mcr p15, 0, r1, c1, c0, 0 @ disable MMU
mov r1, #0
mcr p15, 0, r1, c7, c5, 4 @ ISB
mov pc, r0 mov pc, r0
/* /*

7
arch/arm/mm/proc-v7.S
View File

@ -58,9 +58,16 @@ ENDPROC(cpu_v7_proc_fin)
* to what would be the reset vector. * to what would be the reset vector.
* *
* - loc - location to jump to for soft reset * - loc - location to jump to for soft reset
*
* This code must be executed using a flat identity mapping with
* caches disabled.
*/ */
.align 5 .align 5
ENTRY(cpu_v7_reset) ENTRY(cpu_v7_reset)
mrc p15, 0, r1, c1, c0, 0 @ ctrl register
bic r1, r1, #0x1 @ ...............m
mcr p15, 0, r1, c1, c0, 0 @ disable MMU
isb
mov pc, r0 mov pc, r0
ENDPROC(cpu_v7_reset) ENDPROC(cpu_v7_reset)