net: ethernet: arc: Keep emac compatibility for more Rockchip SoCs
On the RK3066/RK3188, there was fixed GRF offset configuration to set emac and fixed DIV2 mac TX/RX clock. So, we need to easily set and fit to other SoCs (RK3036) which maybe have different GRF offset, and need adjust mac TX/RX clock. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -25,17 +25,13 @@
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#include "emac.h"
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#define DRV_NAME "rockchip_emac"
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#define DRV_VERSION "1.0"
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#define GRF_MODE_MII (1UL << 0)
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#define GRF_MODE_RMII (0UL << 0)
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#define GRF_SPEED_10M (0UL << 1)
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#define GRF_SPEED_100M (1UL << 1)
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#define GRF_SPEED_ENABLE_BIT (1UL << 17)
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#define GRF_MODE_ENABLE_BIT (1UL << 16)
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#define DRV_VERSION "1.1"
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struct emac_rockchip_soc_data {
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int grf_offset;
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unsigned int grf_offset;
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unsigned int grf_mode_offset;
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unsigned int grf_speed_offset;
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bool need_div_macclk;
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};
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struct rockchip_priv_data {
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@ -44,23 +40,22 @@ struct rockchip_priv_data {
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const struct emac_rockchip_soc_data *soc_data;
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struct regulator *regulator;
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struct clk *refclk;
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struct clk *macclk;
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};
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static void emac_rockchip_set_mac_speed(void *priv, unsigned int speed)
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{
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struct rockchip_priv_data *emac = priv;
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u32 speed_offset = emac->soc_data->grf_speed_offset;
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u32 data;
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int err = 0;
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/* write-enable bits */
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data = GRF_SPEED_ENABLE_BIT;
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switch(speed) {
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case 10:
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data |= GRF_SPEED_10M;
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data = (1 << (speed_offset + 16)) | (0 << speed_offset);
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break;
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case 100:
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data |= GRF_SPEED_100M;
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data = (1 << (speed_offset + 16)) | (1 << speed_offset);
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break;
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default:
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pr_err("speed %u not supported\n", speed);
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@ -72,14 +67,19 @@ static void emac_rockchip_set_mac_speed(void *priv, unsigned int speed)
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pr_err("unable to apply speed %u to grf (%d)\n", speed, err);
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}
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static const struct emac_rockchip_soc_data emac_rockchip_dt_data[] = {
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{ .grf_offset = 0x154 }, /* rk3066 */
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{ .grf_offset = 0x0a4 }, /* rk3188 */
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static const struct emac_rockchip_soc_data emac_rk3066_emac_data = {
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.grf_offset = 0x154, .grf_mode_offset = 0,
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.grf_speed_offset = 1, .need_div_macclk = 0,
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};
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static const struct emac_rockchip_soc_data emac_rk3188_emac_data = {
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.grf_offset = 0x0a4, .grf_mode_offset = 0,
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.grf_speed_offset = 1, .need_div_macclk = 0,
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};
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static const struct of_device_id emac_rockchip_dt_ids[] = {
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{ .compatible = "rockchip,rk3066-emac", .data = &emac_rockchip_dt_data[0] },
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{ .compatible = "rockchip,rk3188-emac", .data = &emac_rockchip_dt_data[1] },
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{ .compatible = "rockchip,rk3066-emac", .data = &emac_rk3066_emac_data },
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{ .compatible = "rockchip,rk3188-emac", .data = &emac_rk3188_emac_data },
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{ /* Sentinel */ }
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};
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@ -164,11 +164,12 @@ static int emac_rockchip_probe(struct platform_device *pdev)
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}
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}
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/* write-enable bits */
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data = GRF_MODE_ENABLE_BIT | GRF_SPEED_ENABLE_BIT;
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data |= GRF_SPEED_100M;
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data |= GRF_MODE_RMII;
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/* Set speed 100M */
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data = (1 << (priv->soc_data->grf_speed_offset + 16)) |
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(1 << priv->soc_data->grf_speed_offset);
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/* Set RMII mode */
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data |= (1 << (priv->soc_data->grf_mode_offset + 16)) |
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(0 << priv->soc_data->grf_mode_offset);
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err = regmap_write(priv->grf, priv->soc_data->grf_offset, data);
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if (err) {
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@ -181,6 +182,26 @@ static int emac_rockchip_probe(struct platform_device *pdev)
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if (err)
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dev_err(dev, "failed to change reference clock rate (%d)\n", err);
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if (priv->soc_data->need_div_macclk) {
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priv->macclk = devm_clk_get(dev, "macclk");
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if (IS_ERR(priv->macclk)) {
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dev_err(dev, "failed to retrieve mac clock (%ld)\n", PTR_ERR(priv->macclk));
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err = PTR_ERR(priv->macclk);
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goto out_regulator_disable;
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}
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err = clk_prepare_enable(priv->macclk);
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if (err) {
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dev_err(dev, "failed to enable mac clock (%d)\n", err);
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goto out_regulator_disable;
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}
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/* RMII TX/RX needs always a rate of 25MHz */
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err = clk_set_rate(priv->macclk, 25000000);
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if (err)
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dev_err(dev, "failed to change mac clock rate (%d)\n", err);
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}
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err = arc_emac_probe(ndev, interface);
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if (err) {
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dev_err(dev, "failed to probe arc emac (%d)\n", err);
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