drm: rockchip: vop: add rk3066 vop definitions
This patch adds the rk3066 VOP definitions. The VOP or LCD Controller serves as interface between framebuffer memory and a display device (LCD panel or TV set). This SOC has two symmetrical LCDC's for a dual panel application. A LCDC has 5 display layers. Only 3 are used here. - Video layer 0 (Win0) - Video layer 1 (Win1) - OSD layer (Win2) Win0 and Win1 are exchangeable. Maximum resolution is 1920x1080. The LCDC0 output is connected to: - LCDC0 IO (without IOMUX) - HDMI TX video input The LCDC1 output is connected to: - LCDC1 IO (with IOMUX) - HDMI TX video input The HDMI TX input can switch between LCDC0 and LCDC1. Signed-off-by: Mark Yao <mark.yao@rock-chips.com> Signed-off-by: Johan Jonker <jbx6244@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://patchwork.freedesktop.org/patch/msgid/20181229133318.18128-4-jbx6244@gmail.com
This commit is contained in:
Mark Yao
Heiko Stuebner
parent
b981a6863e
commit
f4a6de855e
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@ -10,6 +10,7 @@ Required properties:
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"rockchip,rk3126-vop";
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"rockchip,px30-vop-lit";
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"rockchip,px30-vop-big";
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"rockchip,rk3066-vop";
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"rockchip,rk3188-vop";
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"rockchip,rk3288-vop";
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"rockchip,rk3368-vop";
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@ -299,6 +299,114 @@ static const struct vop_data px30_vop_lit = {
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.win_size = ARRAY_SIZE(px30_vop_lit_win_data),
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};
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static const struct vop_scl_regs rk3066_win_scl = {
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.scale_yrgb_x = VOP_REG(RK3066_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
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.scale_yrgb_y = VOP_REG(RK3066_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
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.scale_cbcr_x = VOP_REG(RK3066_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
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.scale_cbcr_y = VOP_REG(RK3066_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
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};
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static const struct vop_win_phy rk3066_win0_data = {
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.scl = &rk3066_win_scl,
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.data_formats = formats_win_full,
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.nformats = ARRAY_SIZE(formats_win_full),
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.enable = VOP_REG(RK3066_SYS_CTRL1, 0x1, 0),
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.format = VOP_REG(RK3066_SYS_CTRL0, 0x7, 4),
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.rb_swap = VOP_REG(RK3066_SYS_CTRL0, 0x1, 19),
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.act_info = VOP_REG(RK3066_WIN0_ACT_INFO, 0x1fff1fff, 0),
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.dsp_info = VOP_REG(RK3066_WIN0_DSP_INFO, 0x0fff0fff, 0),
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.dsp_st = VOP_REG(RK3066_WIN0_DSP_ST, 0x1fff1fff, 0),
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.yrgb_mst = VOP_REG(RK3066_WIN0_YRGB_MST0, 0xffffffff, 0),
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.uv_mst = VOP_REG(RK3066_WIN0_CBR_MST0, 0xffffffff, 0),
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.yrgb_vir = VOP_REG(RK3066_WIN0_VIR, 0xffff, 0),
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.uv_vir = VOP_REG(RK3066_WIN0_VIR, 0x1fff, 16),
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};
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static const struct vop_win_phy rk3066_win1_data = {
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.scl = &rk3066_win_scl,
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.data_formats = formats_win_full,
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.nformats = ARRAY_SIZE(formats_win_full),
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.enable = VOP_REG(RK3066_SYS_CTRL1, 0x1, 1),
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.format = VOP_REG(RK3066_SYS_CTRL0, 0x7, 7),
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.rb_swap = VOP_REG(RK3066_SYS_CTRL0, 0x1, 23),
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.act_info = VOP_REG(RK3066_WIN1_ACT_INFO, 0x1fff1fff, 0),
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.dsp_info = VOP_REG(RK3066_WIN1_DSP_INFO, 0x0fff0fff, 0),
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.dsp_st = VOP_REG(RK3066_WIN1_DSP_ST, 0x1fff1fff, 0),
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.yrgb_mst = VOP_REG(RK3066_WIN1_YRGB_MST, 0xffffffff, 0),
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.uv_mst = VOP_REG(RK3066_WIN1_CBR_MST, 0xffffffff, 0),
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.yrgb_vir = VOP_REG(RK3066_WIN1_VIR, 0xffff, 0),
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.uv_vir = VOP_REG(RK3066_WIN1_VIR, 0x1fff, 16),
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};
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static const struct vop_win_phy rk3066_win2_data = {
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.data_formats = formats_win_lite,
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.nformats = ARRAY_SIZE(formats_win_lite),
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.enable = VOP_REG(RK3066_SYS_CTRL1, 0x1, 2),
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.format = VOP_REG(RK3066_SYS_CTRL0, 0x7, 10),
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.rb_swap = VOP_REG(RK3066_SYS_CTRL0, 0x1, 27),
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.dsp_info = VOP_REG(RK3066_WIN2_DSP_INFO, 0x0fff0fff, 0),
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.dsp_st = VOP_REG(RK3066_WIN2_DSP_ST, 0x1fff1fff, 0),
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.yrgb_mst = VOP_REG(RK3066_WIN2_MST, 0xffffffff, 0),
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.yrgb_vir = VOP_REG(RK3066_WIN2_VIR, 0xffff, 0),
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};
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static const struct vop_modeset rk3066_modeset = {
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.htotal_pw = VOP_REG(RK3066_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
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.hact_st_end = VOP_REG(RK3066_DSP_HACT_ST_END, 0x1fff1fff, 0),
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.vtotal_pw = VOP_REG(RK3066_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
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.vact_st_end = VOP_REG(RK3066_DSP_VACT_ST_END, 0x1fff1fff, 0),
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};
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static const struct vop_output rk3066_output = {
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.pin_pol = VOP_REG(RK3066_DSP_CTRL0, 0x7, 4),
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};
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static const struct vop_common rk3066_common = {
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.standby = VOP_REG(RK3066_SYS_CTRL0, 0x1, 1),
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.out_mode = VOP_REG(RK3066_DSP_CTRL0, 0xf, 0),
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.cfg_done = VOP_REG(RK3066_REG_CFG_DONE, 0x1, 0),
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.dsp_blank = VOP_REG(RK3066_DSP_CTRL1, 0x1, 24),
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};
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static const struct vop_win_data rk3066_vop_win_data[] = {
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{ .base = 0x00, .phy = &rk3066_win0_data,
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.type = DRM_PLANE_TYPE_PRIMARY },
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{ .base = 0x00, .phy = &rk3066_win1_data,
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.type = DRM_PLANE_TYPE_OVERLAY },
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{ .base = 0x00, .phy = &rk3066_win2_data,
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.type = DRM_PLANE_TYPE_CURSOR },
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};
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static const int rk3066_vop_intrs[] = {
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/*
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* hs_start interrupt fires at frame-start, so serves
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* the same purpose as dsp_hold in the driver.
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*/
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DSP_HOLD_VALID_INTR,
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FS_INTR,
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LINE_FLAG_INTR,
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BUS_ERROR_INTR,
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};
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static const struct vop_intr rk3066_intr = {
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.intrs = rk3066_vop_intrs,
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.nintrs = ARRAY_SIZE(rk3066_vop_intrs),
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.line_flag_num[0] = VOP_REG(RK3066_INT_STATUS, 0xfff, 12),
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.status = VOP_REG(RK3066_INT_STATUS, 0xf, 0),
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.enable = VOP_REG(RK3066_INT_STATUS, 0xf, 4),
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.clear = VOP_REG(RK3066_INT_STATUS, 0xf, 8),
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};
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static const struct vop_data rk3066_vop = {
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.version = VOP_VERSION(2, 1),
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.intr = &rk3066_intr,
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.common = &rk3066_common,
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.modeset = &rk3066_modeset,
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.output = &rk3066_output,
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.win = rk3066_vop_win_data,
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.win_size = ARRAY_SIZE(rk3066_vop_win_data),
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};
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static const struct vop_scl_regs rk3188_win_scl = {
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.scale_yrgb_x = VOP_REG(RK3188_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
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.scale_yrgb_y = VOP_REG(RK3188_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
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@ -817,6 +925,8 @@ static const struct of_device_id vop_driver_dt_match[] = {
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.data = &px30_vop_big },
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{ .compatible = "rockchip,px30-vop-lit",
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.data = &px30_vop_lit },
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{ .compatible = "rockchip,rk3066-vop",
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.data = &rk3066_vop },
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{ .compatible = "rockchip,rk3188-vop",
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.data = &rk3188_vop },
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{ .compatible = "rockchip,rk3288-vop",
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@ -983,4 +983,57 @@
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#define RK3188_REG_CFG_DONE 0x90
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/* rk3188 register definition end */
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/* rk3066 register definition */
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#define RK3066_SYS_CTRL0 0x00
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#define RK3066_SYS_CTRL1 0x04
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#define RK3066_DSP_CTRL0 0x08
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#define RK3066_DSP_CTRL1 0x0c
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#define RK3066_INT_STATUS 0x10
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#define RK3066_MCU_CTRL 0x14
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#define RK3066_BLEND_CTRL 0x18
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#define RK3066_WIN0_COLOR_KEY_CTRL 0x1c
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#define RK3066_WIN1_COLOR_KEY_CTRL 0x20
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#define RK3066_WIN2_COLOR_KEY_CTRL 0x24
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#define RK3066_WIN0_YRGB_MST0 0x28
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#define RK3066_WIN0_CBR_MST0 0x2c
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#define RK3066_WIN0_YRGB_MST1 0x30
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#define RK3066_WIN0_CBR_MST1 0x34
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#define RK3066_WIN0_VIR 0x38
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#define RK3066_WIN0_ACT_INFO 0x3c
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#define RK3066_WIN0_DSP_INFO 0x40
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#define RK3066_WIN0_DSP_ST 0x44
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#define RK3066_WIN0_SCL_FACTOR_YRGB 0x48
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#define RK3066_WIN0_SCL_FACTOR_CBR 0x4c
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#define RK3066_WIN0_SCL_OFFSET 0x50
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#define RK3066_WIN1_YRGB_MST 0x54
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#define RK3066_WIN1_CBR_MST 0x58
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#define RK3066_WIN1_VIR 0x5c
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#define RK3066_WIN1_ACT_INFO 0x60
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#define RK3066_WIN1_DSP_INFO 0x64
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#define RK3066_WIN1_DSP_ST 0x68
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#define RK3066_WIN1_SCL_FACTOR_YRGB 0x6c
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#define RK3066_WIN1_SCL_FACTOR_CBR 0x70
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#define RK3066_WIN1_SCL_OFFSET 0x74
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#define RK3066_WIN2_MST 0x78
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#define RK3066_WIN2_VIR 0x7c
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#define RK3066_WIN2_DSP_INFO 0x80
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#define RK3066_WIN2_DSP_ST 0x84
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#define RK3066_HWC_MST 0x88
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#define RK3066_HWC_DSP_ST 0x8c
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#define RK3066_HWC_COLOR_LUT0 0x90
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#define RK3066_HWC_COLOR_LUT1 0x94
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#define RK3066_HWC_COLOR_LUT2 0x98
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#define RK3066_DSP_HTOTAL_HS_END 0x9c
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#define RK3066_DSP_HACT_ST_END 0xa0
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#define RK3066_DSP_VTOTAL_VS_END 0xa4
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#define RK3066_DSP_VACT_ST_END 0xa8
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#define RK3066_DSP_VS_ST_END_F1 0xac
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#define RK3066_DSP_VACT_ST_END_F1 0xb0
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#define RK3066_REG_CFG_DONE 0xc0
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#define RK3066_MCU_BYPASS_WPORT 0x100
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#define RK3066_MCU_BYPASS_RPORT 0x200
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#define RK3066_WIN2_LUT_ADDR 0x400
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#define RK3066_DSP_LUT_ADDR 0x800
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/* rk3066 register definition end */
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#endif /* _ROCKCHIP_VOP_REG_H */
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