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drm/i915: Bikeshed rpm functions name a bit. 

- fini goes with init, so call it intel_power_domains_fini. While
  at it shovel some of the fini code that leaked out of it back in.

- give power_enabled functions the verb _is_ to make the meaning clearer.
  Also use a __ prefix instead of _unlocked to really discourage users.

- rename runtime_pm_init/fini to enable/disable since that's what they do.

Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Daniel Vetter 2014-09-30 10:56:39 +02:00
parent 9c065a7d5b
commit f458ebbc33
13 changed files with 51 additions and 50 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/drm/i915/i915_debugfs.c
View File

@ -716,7 +716,7 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
} }
for_each_pipe(dev_priv, pipe) { for_each_pipe(dev_priv, pipe) {
if (!intel_display_power_enabled(dev_priv, if (!intel_display_power_is_enabled(dev_priv,
POWER_DOMAIN_PIPE(pipe))) { POWER_DOMAIN_PIPE(pipe))) {
seq_printf(m, "Pipe %c power disabled\n", seq_printf(m, "Pipe %c power disabled\n",
pipe_name(pipe)); pipe_name(pipe));

12
drivers/gpu/drm/i915/i915_dma.c
View File

@ -1798,12 +1798,12 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
if (IS_GEN5(dev)) if (IS_GEN5(dev))
intel_gpu_ips_init(dev_priv); intel_gpu_ips_init(dev_priv);
intel_init_runtime_pm(dev_priv); intel_runtime_pm_enable(dev_priv);
return 0; return 0;
out_power_well: out_power_well:
intel_power_domains_remove(dev_priv); intel_power_domains_fini(dev_priv);
drm_vblank_cleanup(dev); drm_vblank_cleanup(dev);
out_gem_unload: out_gem_unload:
WARN_ON(unregister_oom_notifier(&dev_priv->mm.oom_notifier)); WARN_ON(unregister_oom_notifier(&dev_priv->mm.oom_notifier));
@ -1846,15 +1846,11 @@ int i915_driver_unload(struct drm_device *dev)
return ret; return ret;
} }
intel_fini_runtime_pm(dev_priv); intel_runtime_pm_disable(dev_priv);
intel_gpu_ips_teardown(); intel_gpu_ips_teardown();
/* The i915.ko module is still not prepared to be loaded when intel_power_domains_fini(dev_priv);
* the power well is not enabled, so just enable it in case
* we're going to unload/reload. */
intel_display_set_init_power(dev_priv, true);
intel_power_domains_remove(dev_priv);
i915_teardown_sysfs(dev); i915_teardown_sysfs(dev);

2
drivers/gpu/drm/i915/i915_drv.h
View File

@ -1411,7 +1411,7 @@ struct ilk_wm_values {
* *
* Our driver uses the autosuspend delay feature, which means we'll only really * Our driver uses the autosuspend delay feature, which means we'll only really
* suspend if we stay with zero refcount for a certain amount of time. The * suspend if we stay with zero refcount for a certain amount of time. The
* default value is currently very conservative (see intel_init_runtime_pm), but * default value is currently very conservative (see intel_runtime_pm_enable), but
* it can be changed with the standard runtime PM files from sysfs. * it can be changed with the standard runtime PM files from sysfs.
* *
* The irqs_disabled variable becomes true exactly after we disable the IRQs and * The irqs_disabled variable becomes true exactly after we disable the IRQs and

6
drivers/gpu/drm/i915/i915_irq.c
View File

@ -3473,8 +3473,8 @@ static void gen8_irq_reset(struct drm_device *dev)
gen8_gt_irq_reset(dev_priv); gen8_gt_irq_reset(dev_priv);
for_each_pipe(dev_priv, pipe) for_each_pipe(dev_priv, pipe)
if (intel_display_power_enabled(dev_priv, if (intel_display_power_is_enabled(dev_priv,
POWER_DOMAIN_PIPE(pipe))) POWER_DOMAIN_PIPE(pipe)))
GEN8_IRQ_RESET_NDX(DE_PIPE, pipe); GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
GEN5_IRQ_RESET(GEN8_DE_PORT_); GEN5_IRQ_RESET(GEN8_DE_PORT_);
@ -3826,7 +3826,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked; dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
for_each_pipe(dev_priv, pipe) for_each_pipe(dev_priv, pipe)
if (intel_display_power_enabled(dev_priv, if (intel_display_power_is_enabled(dev_priv,
POWER_DOMAIN_PIPE(pipe))) POWER_DOMAIN_PIPE(pipe)))
GEN8_IRQ_INIT_NDX(DE_PIPE, pipe, GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
dev_priv->de_irq_mask[pipe], dev_priv->de_irq_mask[pipe],

2
drivers/gpu/drm/i915/intel_crt.c
View File

@ -72,7 +72,7 @@ static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
u32 tmp; u32 tmp;
power_domain = intel_display_port_power_domain(encoder); power_domain = intel_display_port_power_domain(encoder);
if (!intel_display_power_enabled(dev_priv, power_domain)) if (!intel_display_power_is_enabled(dev_priv, power_domain))
return false; return false;
tmp = I915_READ(crt->adpa_reg); tmp = I915_READ(crt->adpa_reg);

8
drivers/gpu/drm/i915/intel_ddi.c
View File

@ -998,7 +998,7 @@ bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
uint32_t tmp; uint32_t tmp;
power_domain = intel_display_port_power_domain(intel_encoder); power_domain = intel_display_port_power_domain(intel_encoder);
if (!intel_display_power_enabled(dev_priv, power_domain)) if (!intel_display_power_is_enabled(dev_priv, power_domain))
return false; return false;
if (!intel_encoder->get_hw_state(intel_encoder, &pipe)) if (!intel_encoder->get_hw_state(intel_encoder, &pipe))
@ -1044,7 +1044,7 @@ bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
int i; int i;
power_domain = intel_display_port_power_domain(encoder); power_domain = intel_display_port_power_domain(encoder);
if (!intel_display_power_enabled(dev_priv, power_domain)) if (!intel_display_power_is_enabled(dev_priv, power_domain))
return false; return false;
tmp = I915_READ(DDI_BUF_CTL(port)); tmp = I915_READ(DDI_BUF_CTL(port));
@ -1332,7 +1332,7 @@ static bool hsw_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
{ {
uint32_t val; uint32_t val;
if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_PLLS)) if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
return false; return false;
val = I915_READ(WRPLL_CTL(pll->id)); val = I915_READ(WRPLL_CTL(pll->id));
@ -1522,7 +1522,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
break; break;
} }
if (intel_display_power_enabled(dev_priv, POWER_DOMAIN_AUDIO)) { if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
if (temp & (AUDIO_OUTPUT_ENABLE_A << (intel_crtc->pipe * 4))) if (temp & (AUDIO_OUTPUT_ENABLE_A << (intel_crtc->pipe * 4)))
pipe_config->has_audio = true; pipe_config->has_audio = true;

26
drivers/gpu/drm/i915/intel_display.c
View File

@ -1210,7 +1210,7 @@ void assert_pipe(struct drm_i915_private *dev_priv,
(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
state = true; state = true;
if (!intel_display_power_enabled(dev_priv, if (!intel_display_power_is_enabled(dev_priv,
POWER_DOMAIN_TRANSCODER(cpu_transcoder))) { POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
cur_state = false; cur_state = false;
} else { } else {
@ -6493,8 +6493,8 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_private *dev_priv = dev->dev_private;
uint32_t tmp; uint32_t tmp;
if (!intel_display_power_enabled(dev_priv, if (!intel_display_power_is_enabled(dev_priv,
POWER_DOMAIN_PIPE(crtc->pipe))) POWER_DOMAIN_PIPE(crtc->pipe)))
return false; return false;
pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
@ -7503,8 +7503,8 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_private *dev_priv = dev->dev_private;
uint32_t tmp; uint32_t tmp;
if (!intel_display_power_enabled(dev_priv, if (!intel_display_power_is_enabled(dev_priv,
POWER_DOMAIN_PIPE(crtc->pipe))) POWER_DOMAIN_PIPE(crtc->pipe)))
return false; return false;
pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
@ -7902,7 +7902,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
enum intel_display_power_domain pfit_domain; enum intel_display_power_domain pfit_domain;
uint32_t tmp; uint32_t tmp;
if (!intel_display_power_enabled(dev_priv, if (!intel_display_power_is_enabled(dev_priv,
POWER_DOMAIN_PIPE(crtc->pipe))) POWER_DOMAIN_PIPE(crtc->pipe)))
return false; return false;
@ -7931,7 +7931,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
pipe_config->cpu_transcoder = TRANSCODER_EDP; pipe_config->cpu_transcoder = TRANSCODER_EDP;
} }
if (!intel_display_power_enabled(dev_priv, if (!intel_display_power_is_enabled(dev_priv,
POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
return false; return false;
@ -7944,7 +7944,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
intel_get_pipe_timings(crtc, pipe_config); intel_get_pipe_timings(crtc, pipe_config);
pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
if (intel_display_power_enabled(dev_priv, pfit_domain)) if (intel_display_power_is_enabled(dev_priv, pfit_domain))
ironlake_get_pfit_config(crtc, pipe_config); ironlake_get_pfit_config(crtc, pipe_config);
if (IS_HASWELL(dev)) if (IS_HASWELL(dev))
@ -11534,7 +11534,7 @@ static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
{ {
uint32_t val; uint32_t val;
if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_PLLS)) if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
return false; return false;
val = I915_READ(PCH_DPLL(pll->id)); val = I915_READ(PCH_DPLL(pll->id));
@ -13165,7 +13165,7 @@ void i915_redisable_vga(struct drm_device *dev)
* level, just check if the power well is enabled instead of trying to * level, just check if the power well is enabled instead of trying to
* follow the "don't touch the power well if we don't need it" policy * follow the "don't touch the power well if we don't need it" policy
* the rest of the driver uses. */ * the rest of the driver uses. */
if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA)) if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
return; return;
i915_redisable_vga_power_on(dev); i915_redisable_vga_power_on(dev);
@ -13543,8 +13543,8 @@ intel_display_capture_error_state(struct drm_device *dev)
for_each_pipe(dev_priv, i) { for_each_pipe(dev_priv, i) {
error->pipe[i].power_domain_on = error->pipe[i].power_domain_on =
intel_display_power_enabled_unlocked(dev_priv, __intel_display_power_is_enabled(dev_priv,
POWER_DOMAIN_PIPE(i)); POWER_DOMAIN_PIPE(i));
if (!error->pipe[i].power_domain_on) if (!error->pipe[i].power_domain_on)
continue; continue;
@ -13579,7 +13579,7 @@ intel_display_capture_error_state(struct drm_device *dev)
enum transcoder cpu_transcoder = transcoders[i]; enum transcoder cpu_transcoder = transcoders[i];
error->transcoder[i].power_domain_on = error->transcoder[i].power_domain_on =
intel_display_power_enabled_unlocked(dev_priv, __intel_display_power_is_enabled(dev_priv,
POWER_DOMAIN_TRANSCODER(cpu_transcoder)); POWER_DOMAIN_TRANSCODER(cpu_transcoder));
if (!error->transcoder[i].power_domain_on) if (!error->transcoder[i].power_domain_on)
continue; continue;

2
drivers/gpu/drm/i915/intel_dp.c
View File

@ -1853,7 +1853,7 @@ static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
u32 tmp; u32 tmp;
power_domain = intel_display_port_power_domain(encoder); power_domain = intel_display_port_power_domain(encoder);
if (!intel_display_power_enabled(dev_priv, power_domain)) if (!intel_display_power_is_enabled(dev_priv, power_domain))
return false; return false;
tmp = I915_READ(intel_dp->output_reg); tmp = I915_READ(intel_dp->output_reg);

14
drivers/gpu/drm/i915/intel_drv.h
View File

@ -1083,15 +1083,15 @@ extern struct drm_display_mode *intel_find_panel_downclock(
/* intel_runtime_pm.c */ /* intel_runtime_pm.c */
int intel_power_domains_init(struct drm_i915_private *); int intel_power_domains_init(struct drm_i915_private *);
void intel_power_domains_remove(struct drm_i915_private *); void intel_power_domains_fini(struct drm_i915_private *);
void intel_power_domains_init_hw(struct drm_i915_private *dev_priv); void intel_power_domains_init_hw(struct drm_i915_private *dev_priv);
void intel_init_runtime_pm(struct drm_i915_private *dev_priv); void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
void intel_fini_runtime_pm(struct drm_i915_private *dev_priv); void intel_runtime_pm_disable(struct drm_i915_private *dev_priv);
bool intel_display_power_enabled(struct drm_i915_private *dev_priv, bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
enum intel_display_power_domain domain); enum intel_display_power_domain domain);
bool intel_display_power_enabled_unlocked(struct drm_i915_private *dev_priv, bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
enum intel_display_power_domain domain); enum intel_display_power_domain domain);
void intel_display_power_get(struct drm_i915_private *dev_priv, void intel_display_power_get(struct drm_i915_private *dev_priv,
enum intel_display_power_domain domain); enum intel_display_power_domain domain);
void intel_display_power_put(struct drm_i915_private *dev_priv, void intel_display_power_put(struct drm_i915_private *dev_priv,

2
drivers/gpu/drm/i915/intel_dsi.c
View File

@ -344,7 +344,7 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
DRM_DEBUG_KMS("\n"); DRM_DEBUG_KMS("\n");
power_domain = intel_display_port_power_domain(encoder); power_domain = intel_display_port_power_domain(encoder);
if (!intel_display_power_enabled(dev_priv, power_domain)) if (!intel_display_power_is_enabled(dev_priv, power_domain))
return false; return false;
/* XXX: this only works for one DSI output */ /* XXX: this only works for one DSI output */

2
drivers/gpu/drm/i915/intel_hdmi.c
View File

@ -690,7 +690,7 @@ static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
u32 tmp; u32 tmp;
power_domain = intel_display_port_power_domain(encoder); power_domain = intel_display_port_power_domain(encoder);
if (!intel_display_power_enabled(dev_priv, power_domain)) if (!intel_display_power_is_enabled(dev_priv, power_domain))
return false; return false;
tmp = I915_READ(intel_hdmi->hdmi_reg); tmp = I915_READ(intel_hdmi->hdmi_reg);

2
drivers/gpu/drm/i915/intel_lvds.c
View File

@ -76,7 +76,7 @@ static bool intel_lvds_get_hw_state(struct intel_encoder *encoder,
u32 tmp; u32 tmp;
power_domain = intel_display_port_power_domain(encoder); power_domain = intel_display_port_power_domain(encoder);
if (!intel_display_power_enabled(dev_priv, power_domain)) if (!intel_display_power_is_enabled(dev_priv, power_domain))
return false; return false;
tmp = I915_READ(lvds_encoder->reg); tmp = I915_READ(lvds_encoder->reg);

21
drivers/gpu/drm/i915/intel_runtime_pm.c
View File

@ -60,8 +60,8 @@ static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
(HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED); (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
} }
bool intel_display_power_enabled_unlocked(struct drm_i915_private *dev_priv, bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
enum intel_display_power_domain domain) enum intel_display_power_domain domain)
{ {
struct i915_power_domains *power_domains; struct i915_power_domains *power_domains;
struct i915_power_well *power_well; struct i915_power_well *power_well;
@ -88,8 +88,8 @@ bool intel_display_power_enabled_unlocked(struct drm_i915_private *dev_priv,
return is_enabled; return is_enabled;
} }
bool intel_display_power_enabled(struct drm_i915_private *dev_priv, bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
enum intel_display_power_domain domain) enum intel_display_power_domain domain)
{ {
struct i915_power_domains *power_domains; struct i915_power_domains *power_domains;
bool ret; bool ret;
@ -97,7 +97,7 @@ bool intel_display_power_enabled(struct drm_i915_private *dev_priv,
power_domains = &dev_priv->power_domains; power_domains = &dev_priv->power_domains;
mutex_lock(&power_domains->lock); mutex_lock(&power_domains->lock);
ret = intel_display_power_enabled_unlocked(dev_priv, domain); ret = __intel_display_power_is_enabled(dev_priv, domain);
mutex_unlock(&power_domains->lock); mutex_unlock(&power_domains->lock);
return ret; return ret;
@ -981,8 +981,13 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
return 0; return 0;
} }
void intel_power_domains_remove(struct drm_i915_private *dev_priv) void intel_power_domains_fini(struct drm_i915_private *dev_priv)
{ {
/* The i915.ko module is still not prepared to be loaded when
* the power well is not enabled, so just enable it in case
* we're going to unload/reload. */
intel_display_set_init_power(dev_priv, true);
hsw_pwr = NULL; hsw_pwr = NULL;
} }
@ -1097,7 +1102,7 @@ void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
pm_runtime_put_autosuspend(device); pm_runtime_put_autosuspend(device);
} }
void intel_init_runtime_pm(struct drm_i915_private *dev_priv) void intel_runtime_pm_enable(struct drm_i915_private *dev_priv)
{ {
struct drm_device *dev = dev_priv->dev; struct drm_device *dev = dev_priv->dev;
struct device *device = &dev->pdev->dev; struct device *device = &dev->pdev->dev;
@ -1123,7 +1128,7 @@ void intel_init_runtime_pm(struct drm_i915_private *dev_priv)
pm_runtime_put_autosuspend(device); pm_runtime_put_autosuspend(device);
} }
void intel_fini_runtime_pm(struct drm_i915_private *dev_priv) void intel_runtime_pm_disable(struct drm_i915_private *dev_priv)
{ {
struct drm_device *dev = dev_priv->dev; struct drm_device *dev = dev_priv->dev;
struct device *device = &dev->pdev->dev; struct device *device = &dev->pdev->dev;