Merge branch 'pm-cpufreq'
* pm-cpufreq: cpufreq: Don't use smp_processor_id() in preemptible context cpufreq: governor: Fix typos in comments cpufreq: governors: Remove duplicate check of target freq in supported range cpufreq: Fix timer/workqueue corruption due to double queueing cpufreq: imx6q: Fix clock enable balance cpufreq: tegra: fix the wrong clock name
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f41b83126c
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@ -67,8 +67,6 @@ static void cs_check_cpu(int cpu, unsigned int load)
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return;
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dbs_info->requested_freq += get_freq_target(cs_tuners, policy);
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if (dbs_info->requested_freq > policy->max)
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dbs_info->requested_freq = policy->max;
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__cpufreq_driver_target(policy, dbs_info->requested_freq,
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CPUFREQ_RELATION_H);
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@ -89,8 +87,6 @@ static void cs_check_cpu(int cpu, unsigned int load)
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return;
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dbs_info->requested_freq -= get_freq_target(cs_tuners, policy);
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if (dbs_info->requested_freq < policy->min)
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dbs_info->requested_freq = policy->min;
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__cpufreq_driver_target(policy, dbs_info->requested_freq,
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CPUFREQ_RELATION_L);
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@ -119,8 +119,18 @@ void gov_queue_work(struct dbs_data *dbs_data, struct cpufreq_policy *policy,
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{
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int i;
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if (!policy->governor_enabled)
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return;
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if (!all_cpus) {
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__gov_queue_work(smp_processor_id(), dbs_data, delay);
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/*
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* Use raw_smp_processor_id() to avoid preemptible warnings.
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* We know that this is only called with all_cpus == false from
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* works that have been queued with *_work_on() functions and
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* those works are canceled during CPU_DOWN_PREPARE so they
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* can't possibly run on any other CPU.
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*/
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__gov_queue_work(raw_smp_processor_id(), dbs_data, delay);
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} else {
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for_each_cpu(i, policy->cpus)
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__gov_queue_work(i, dbs_data, delay);
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@ -230,7 +240,7 @@ int cpufreq_governor_dbs(struct cpufreq_policy *policy,
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policy->governor_data = dbs_data;
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/* policy latency is in nS. Convert it to uS first */
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/* policy latency is in ns. Convert it to us first */
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latency = policy->cpuinfo.transition_latency / 1000;
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if (latency == 0)
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latency = 1;
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@ -25,11 +25,11 @@
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/*
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* The polling frequency depends on the capability of the processor. Default
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* polling frequency is 1000 times the transition latency of the processor. The
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* governor will work on any processor with transition latency <= 10mS, using
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* governor will work on any processor with transition latency <= 10ms, using
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* appropriate sampling rate.
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*
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* For CPUs with transition latency > 10mS (mostly drivers with CPUFREQ_ETERNAL)
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* this governor will not work. All times here are in uS.
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* For CPUs with transition latency > 10ms (mostly drivers with CPUFREQ_ETERNAL)
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* this governor will not work. All times here are in us (micro seconds).
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*/
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#define MIN_SAMPLING_RATE_RATIO (2)
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#define LATENCY_MULTIPLIER (1000)
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@ -162,7 +162,7 @@ struct cs_cpu_dbs_info_s {
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unsigned int enable:1;
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};
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/* Per policy Governers sysfs tunables */
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/* Per policy Governors sysfs tunables */
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struct od_dbs_tuners {
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unsigned int ignore_nice_load;
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unsigned int sampling_rate;
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@ -181,7 +181,7 @@ struct cs_dbs_tuners {
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unsigned int freq_step;
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};
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/* Common Governer data across policies */
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/* Common Governor data across policies */
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struct dbs_data;
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struct common_dbs_data {
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/* Common across governors */
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@ -205,7 +205,7 @@ struct common_dbs_data {
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void *gov_ops;
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};
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/* Governer Per policy data */
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/* Governor Per policy data */
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struct dbs_data {
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struct common_dbs_data *cdata;
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unsigned int min_sampling_rate;
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@ -177,9 +177,6 @@ static void od_check_cpu(int cpu, unsigned int load)
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/* No longer fully busy, reset rate_mult */
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dbs_info->rate_mult = 1;
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if (freq_next < policy->min)
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freq_next = policy->min;
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if (!od_tuners->powersave_bias) {
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__cpufreq_driver_target(policy, freq_next,
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CPUFREQ_RELATION_L);
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@ -117,28 +117,11 @@ static int imx6q_set_target(struct cpufreq_policy *policy,
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* - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it
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* - Disable pll2_pfd2_396m_clk
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*/
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clk_prepare_enable(pll2_pfd2_396m_clk);
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clk_set_parent(step_clk, pll2_pfd2_396m_clk);
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clk_set_parent(pll1_sw_clk, step_clk);
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if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk)) {
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clk_set_rate(pll1_sys_clk, freqs.new * 1000);
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/*
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* If we are leaving 396 MHz set-point, we need to enable
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* pll1_sys_clk and disable pll2_pfd2_396m_clk to keep
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* their use count correct.
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*/
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if (freqs.old * 1000 <= clk_get_rate(pll2_pfd2_396m_clk)) {
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clk_prepare_enable(pll1_sys_clk);
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clk_disable_unprepare(pll2_pfd2_396m_clk);
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}
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clk_set_parent(pll1_sw_clk, pll1_sys_clk);
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clk_disable_unprepare(pll2_pfd2_396m_clk);
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} else {
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/*
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* Disable pll1_sys_clk if pll2_pfd2_396m_clk is sufficient
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* to provide the frequency.
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*/
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clk_disable_unprepare(pll1_sys_clk);
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}
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/* Ensure the arm clock divider is what we expect */
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@ -255,7 +255,7 @@ static struct cpufreq_driver tegra_cpufreq_driver = {
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static int __init tegra_cpufreq_init(void)
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{
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cpu_clk = clk_get_sys(NULL, "cpu");
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cpu_clk = clk_get_sys(NULL, "cclk");
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if (IS_ERR(cpu_clk))
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return PTR_ERR(cpu_clk);
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@ -263,7 +263,7 @@ static int __init tegra_cpufreq_init(void)
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if (IS_ERR(pll_x_clk))
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return PTR_ERR(pll_x_clk);
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pll_p_clk = clk_get_sys(NULL, "pll_p_cclk");
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pll_p_clk = clk_get_sys(NULL, "pll_p");
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if (IS_ERR(pll_p_clk))
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return PTR_ERR(pll_p_clk);
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