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Merge branch 'ixp4xx' of git://git.kernel.org/pub/scm/linux/kernel/git/chris/linux-2.6 

* 'ixp4xx' of git://git.kernel.org/pub/scm/linux/kernel/git/chris/linux-2.6:
  IXP4xx: GTWX5715 platform only has two PCI IRQ lines, not four.
  IXP4xx: Introduce IXP4XX_GPIO_IRQ(n) macro and convert IXP4xx platform files.
  IXP4xx: move Gemtek GTWX5715 platform macros to the platform code.
  IXP4xx: Remove unused Motorola PrPMC1100 platform macros.
  IXP4xx: move FSG platform macros to the platform code.
  IXP4xx: move DSM G600 platform macros to the platform code.
  IXP4xx: move NAS100D platform macros to the platform code.
  IXP4xx: move NSLU2 platform macros to the platform code.
  IXP4xx: move Coyote platform macros to the platform code.
  IXP4xx: move AVILA platform macros to the platform code.
  IXP4xx: move IXDP425 platform macros to the platform code.
  IXP4xx: Extend PCI MMIO indirect address space to 1 GB.
  IXP4xx: Fix compilation failure with CONFIG_IXP4XX_INDIRECT_PCI.
  IXP4xx: Drop "__ixp4xx_" prefix from in/out/ioread/iowrite functions for clarity.
  IXP4xx: Rename indirect MMIO primitives from __ixp4xx_* to __indirect_*.
  IXP4xx: Ensure index is positive in irq_to_gpio() and npe_request().
  ARM: fix insl() and outsl() endianness on IXP4xx architecture.
  IXP4xx: Fix normally-disabled debugging text in drivers/net/arm/ixp4xx_eth.c.
  IXP4xx: change the timer base frequency to 66.666000 MHz.
This commit is contained in:
Linus Torvalds 2009-12-12 15:22:22 -08:00
parent f01eb36403 0fd7dc7f6c
commit f40542532e
38 changed files with 461 additions and 911 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
arch/arm/mach-ixp4xx/Kconfig
View File

@ -179,21 +179,21 @@ config IXP4XX_INDIRECT_PCI
help
IXP4xx provides two methods of accessing PCI memory space:
1) A direct mapped window from 0x48000000 to 0x4bffffff (64MB).
1) A direct mapped window from 0x48000000 to 0x4BFFFFFF (64MB).
To access PCI via this space, we simply ioremap() the BAR
into the kernel and we can use the standard read[bwl]/write[bwl]
macros. This is the preferred method due to speed but it
limits the system to just 64MB of PCI memory. This can be
problematic if using video cards and other memory-heavy devices.
2) If > 64MB of memory space is required, the IXP4xx can be
configured to use indirect registers to access PCI This allows
for up to 128MB (0x48000000 to 0x4fffffff) of memory on the bus.
The disadvantage of this is that every PCI access requires
three local register accesses plus a spinlock, but in some
cases the performance hit is acceptable. In addition, you cannot
mmap() PCI devices in this case due to the indirect nature
of the PCI window.
2) If > 64MB of memory space is required, the IXP4xx can be
configured to use indirect registers to access the whole PCI
memory space. This currently allows for up to 1 GB (0x10000000
to 0x4FFFFFFF) of memory on the bus. The disadvantage of this
is that every PCI access requires three local register accesses
plus a spinlock, but in some cases the performance hit is
acceptable. In addition, you cannot mmap() PCI devices in this
case due to the indirect nature of the PCI window.
By default, the direct method is used. Choose this option if you
need to use the indirect method instead. If you don't know

42
arch/arm/mach-ixp4xx/avila-pci.c
View File

@ -22,40 +22,45 @@
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/delay.h>
#include <asm/mach/pci.h>
#include <asm/irq.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
#define AVILA_MAX_DEV 4
#define LOFT_MAX_DEV 6
#define IRQ_LINES 4
/* PCI controller GPIO to IRQ pin mappings */
#define INTA 11
#define INTB 10
#define INTC 9
#define INTD 8
void __init avila_pci_preinit(void)
{
set_irq_type(IRQ_AVILA_PCI_INTA, IRQ_TYPE_LEVEL_LOW);
set_irq_type(IRQ_AVILA_PCI_INTB, IRQ_TYPE_LEVEL_LOW);
set_irq_type(IRQ_AVILA_PCI_INTC, IRQ_TYPE_LEVEL_LOW);
set_irq_type(IRQ_AVILA_PCI_INTD, IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
ixp4xx_pci_preinit();
}
static int __init avila_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
static int pci_irq_table[AVILA_PCI_IRQ_LINES] = {
IRQ_AVILA_PCI_INTA,
IRQ_AVILA_PCI_INTB,
IRQ_AVILA_PCI_INTC,
IRQ_AVILA_PCI_INTD
static int pci_irq_table[IRQ_LINES] = {
IXP4XX_GPIO_IRQ(INTA),
IXP4XX_GPIO_IRQ(INTB),
IXP4XX_GPIO_IRQ(INTC),
IXP4XX_GPIO_IRQ(INTD)
};
int irq = -1;
if (slot >= 1 &&
slot <= (machine_is_loft() ? LOFT_PCI_MAX_DEV : AVILA_PCI_MAX_DEV) &&
pin >= 1 && pin <= AVILA_PCI_IRQ_LINES) {
irq = pci_irq_table[(slot + pin - 2) % 4];
}
slot <= (machine_is_loft() ? LOFT_MAX_DEV : AVILA_MAX_DEV) &&
pin >= 1 && pin <= IRQ_LINES)
return pci_irq_table[(slot + pin - 2) % 4];
return irq;
return -1;
}
struct hw_pci avila_pci __initdata = {
@ -75,4 +80,3 @@ int __init avila_pci_init(void)
}
subsys_initcall(avila_pci_init);

4
arch/arm/mach-ixp4xx/avila-setup.c
View File

@ -19,7 +19,6 @@
#include <linux/serial_8250.h>
#include <linux/slab.h>
#include <linux/i2c-gpio.h>
#include <asm/types.h>
#include <asm/setup.h>
#include <asm/memory.h>
@ -29,6 +28,9 @@
#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
#define AVILA_SDA_PIN 7
#define AVILA_SCL_PIN 6
static struct flash_platform_data avila_flash_data = {
.map_name = "cfi_probe",
.width = 2,

6
arch/arm/mach-ixp4xx/common-pci.c
View File

@ -481,11 +481,7 @@ int ixp4xx_setup(int nr, struct pci_sys_data *sys)
res[1].name = "PCI Memory Space";
res[1].start = PCIBIOS_MIN_MEM;
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
res[1].end = 0x4bffffff;
#else
res[1].end = 0x4fffffff;
#endif
res[1].end = PCIBIOS_MAX_MEM;
res[1].flags = IORESOURCE_MEM;
request_resource(&ioport_resource, &res[0]);

2
arch/arm/mach-ixp4xx/common.c
View File

@ -117,7 +117,7 @@ int gpio_to_irq(int gpio)
}
EXPORT_SYMBOL(gpio_to_irq);
int irq_to_gpio(int irq)
int irq_to_gpio(unsigned int irq)
{
int gpio = (irq < 32) ? irq2gpio[irq] : -EINVAL;

22
arch/arm/mach-ixp4xx/coyote-pci.c
View File

@ -18,27 +18,31 @@
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <asm/mach-types.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/mach/pci.h>
#define SLOT0_DEVID 14
#define SLOT1_DEVID 15
/* PCI controller GPIO to IRQ pin mappings */
#define SLOT0_INTA 6
#define SLOT1_INTA 11
void __init coyote_pci_preinit(void)
{
set_irq_type(IRQ_COYOTE_PCI_SLOT0, IRQ_TYPE_LEVEL_LOW);
set_irq_type(IRQ_COYOTE_PCI_SLOT1, IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(SLOT0_INTA), IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(SLOT1_INTA), IRQ_TYPE_LEVEL_LOW);
ixp4xx_pci_preinit();
}
static int __init coyote_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
if (slot == COYOTE_PCI_SLOT0_DEVID)
return IRQ_COYOTE_PCI_SLOT0;
else if (slot == COYOTE_PCI_SLOT1_DEVID)
return IRQ_COYOTE_PCI_SLOT1;
if (slot == SLOT0_DEVID)
return IXP4XX_GPIO_IRQ(SLOT0_INTA);
else if (slot == SLOT1_DEVID)
return IXP4XX_GPIO_IRQ(SLOT1_INTA);
else return -1;
}

9
arch/arm/mach-ixp4xx/coyote-setup.c
View File

@ -25,6 +25,15 @@
#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
#define COYOTE_IDE_BASE_PHYS IXP4XX_EXP_BUS_BASE(3)
#define COYOTE_IDE_BASE_VIRT 0xFFFE1000
#define COYOTE_IDE_REGION_SIZE 0x1000
#define COYOTE_IDE_DATA_PORT 0xFFFE10E0
#define COYOTE_IDE_CTRL_PORT 0xFFFE10FC
#define COYOTE_IDE_ERROR_PORT 0xFFFE10E2
#define IRQ_COYOTE_IDE IRQ_IXP4XX_GPIO5
static struct flash_platform_data coyote_flash_data = {
.map_name = "cfi_probe",
.width = 2,

46
arch/arm/mach-ixp4xx/dsmg600-pci.c
View File

@ -19,39 +19,45 @@
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <asm/mach/pci.h>
#include <asm/mach-types.h>
#define MAX_DEV 4
#define IRQ_LINES 3
/* PCI controller GPIO to IRQ pin mappings */
#define INTA 11
#define INTB 10
#define INTC 9
#define INTD 8
#define INTE 7
#define INTF 6
void __init dsmg600_pci_preinit(void)
{
set_irq_type(IRQ_DSMG600_PCI_INTA, IRQ_TYPE_LEVEL_LOW);
set_irq_type(IRQ_DSMG600_PCI_INTB, IRQ_TYPE_LEVEL_LOW);
set_irq_type(IRQ_DSMG600_PCI_INTC, IRQ_TYPE_LEVEL_LOW);
set_irq_type(IRQ_DSMG600_PCI_INTD, IRQ_TYPE_LEVEL_LOW);
set_irq_type(IRQ_DSMG600_PCI_INTE, IRQ_TYPE_LEVEL_LOW);
set_irq_type(IRQ_DSMG600_PCI_INTF, IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(INTF), IRQ_TYPE_LEVEL_LOW);
ixp4xx_pci_preinit();
}
static int __init dsmg600_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
static int pci_irq_table[DSMG600_PCI_MAX_DEV][DSMG600_PCI_IRQ_LINES] =
{
{ IRQ_DSMG600_PCI_INTE, -1, -1 },
{ IRQ_DSMG600_PCI_INTA, -1, -1 },
{ IRQ_DSMG600_PCI_INTB, IRQ_DSMG600_PCI_INTC, IRQ_DSMG600_PCI_INTD },
{ IRQ_DSMG600_PCI_INTF, -1, -1 },
static int pci_irq_table[MAX_DEV][IRQ_LINES] = {
{ IXP4XX_GPIO_IRQ(INTE), -1, -1 },
{ IXP4XX_GPIO_IRQ(INTA), -1, -1 },
{ IXP4XX_GPIO_IRQ(INTB), IXP4XX_GPIO_IRQ(INTC),
IXP4XX_GPIO_IRQ(INTD) },
{ IXP4XX_GPIO_IRQ(INTF), -1, -1 },
};
int irq = -1;
if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES)
return pci_irq_table[slot - 1][pin - 1];
if (slot >= 1 && slot <= DSMG600_PCI_MAX_DEV &&
pin >= 1 && pin <= DSMG600_PCI_IRQ_LINES)
irq = pci_irq_table[slot-1][pin-1];
return irq;
return -1;
}
struct hw_pci __initdata dsmg600_pci = {

17
arch/arm/mach-ixp4xx/dsmg600-setup.c
View File

@ -33,6 +33,23 @@
#include <asm/mach/time.h>
#include <asm/gpio.h>
#define DSMG600_SDA_PIN 5
#define DSMG600_SCL_PIN 4
/* DSM-G600 Timer Setting */
#define DSMG600_FREQ 66000000
/* Buttons */
#define DSMG600_PB_GPIO 15 /* power button */
#define DSMG600_RB_GPIO 3 /* reset button */
/* Power control */
#define DSMG600_PO_GPIO 2 /* power off */
/* LEDs */
#define DSMG600_LED_PWR_GPIO 0
#define DSMG600_LED_WLAN_GPIO 14
static struct flash_platform_data dsmg600_flash_data = {
.map_name = "cfi_probe",
.width = 2,

31
arch/arm/mach-ixp4xx/fsg-pci.c
View File

@ -19,33 +19,38 @@
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <asm/mach/pci.h>
#include <asm/mach-types.h>
#define MAX_DEV 3
#define IRQ_LINES 3
/* PCI controller GPIO to IRQ pin mappings */
#define INTA 6
#define INTB 7
#define INTC 5
void __init fsg_pci_preinit(void)
{
set_irq_type(IRQ_FSG_PCI_INTA, IRQ_TYPE_LEVEL_LOW);
set_irq_type(IRQ_FSG_PCI_INTB, IRQ_TYPE_LEVEL_LOW);
set_irq_type(IRQ_FSG_PCI_INTC, IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
ixp4xx_pci_preinit();
}
static int __init fsg_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
static int pci_irq_table[FSG_PCI_IRQ_LINES] = {
IRQ_FSG_PCI_INTC,
IRQ_FSG_PCI_INTB,
IRQ_FSG_PCI_INTA,
static int pci_irq_table[IRQ_LINES] = {
IXP4XX_GPIO_IRQ(INTC),
IXP4XX_GPIO_IRQ(INTB),
IXP4XX_GPIO_IRQ(INTA),
};
int irq = -1;
slot = slot - 11;
slot -= 11;
if (slot >= 1 && slot <= FSG_PCI_MAX_DEV &&
pin >= 1 && pin <= FSG_PCI_IRQ_LINES)
irq = pci_irq_table[(slot - 1)];
if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES)
irq = pci_irq_table[slot - 1];
printk(KERN_INFO "%s: Mapped slot %d pin %d to IRQ %d\n",
__func__, slot, pin, irq);

8
arch/arm/mach-ixp4xx/fsg-setup.c
View File

@ -24,12 +24,18 @@
#include <linux/i2c.h>
#include <linux/i2c-gpio.h>
#include <linux/io.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
#include <asm/gpio.h>
#define FSG_SDA_PIN 12
#define FSG_SCL_PIN 13
#define FSG_SB_GPIO 4 /* sync button */
#define FSG_RB_GPIO 9 /* reset button */
#define FSG_UB_GPIO 10 /* usb button */
static struct flash_platform_data fsg_flash_data = {
.map_name = "cfi_probe",
.width = 2,

45
arch/arm/mach-ixp4xx/goramo_mlr.c
View File

@ -17,29 +17,28 @@
#include <asm/mach/flash.h>
#include <asm/mach/pci.h>
#define xgpio_irq(n) (IRQ_IXP4XX_GPIO ## n)
#define gpio_irq(n) xgpio_irq(n)
#define SLOT_ETHA 0x0B /* IDSEL = AD21 */
#define SLOT_ETHB 0x0C /* IDSEL = AD20 */
#define SLOT_MPCI 0x0D /* IDSEL = AD19 */
#define SLOT_NEC 0x0E /* IDSEL = AD18 */
#define IRQ_ETHA IRQ_IXP4XX_GPIO4
#define IRQ_ETHB IRQ_IXP4XX_GPIO5
#define IRQ_NEC IRQ_IXP4XX_GPIO3
#define IRQ_MPCI IRQ_IXP4XX_GPIO12
/* GPIO lines */
#define GPIO_SCL 0
#define GPIO_SDA 1
#define GPIO_STR 2
#define GPIO_IRQ_NEC 3
#define GPIO_IRQ_ETHA 4
#define GPIO_IRQ_ETHB 5
#define GPIO_HSS0_DCD_N 6
#define GPIO_HSS1_DCD_N 7
#define GPIO_UART0_DCD 8
#define GPIO_UART1_DCD 9
#define GPIO_HSS0_CTS_N 10
#define GPIO_HSS1_CTS_N 11
#define GPIO_IRQ_MPCI 12
#define GPIO_HSS1_RTS_N 13
#define GPIO_HSS0_RTS_N 14
/* GPIO15 is not connected */
/* Control outputs from 74HC4094 */
#define CONTROL_HSS0_CLK_INT 0
@ -152,7 +151,7 @@ static int hss_set_clock(int port, unsigned int clock_type)
static irqreturn_t hss_dcd_irq(int irq, void *pdev)
{
int i, port = (irq == gpio_irq(GPIO_HSS1_DCD_N));
int i, port = (irq == IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N));
gpio_line_get(port ? GPIO_HSS1_DCD_N : GPIO_HSS0_DCD_N, &i);
set_carrier_cb_tab[port](pdev, !i);
return IRQ_HANDLED;
@ -165,9 +164,9 @@ static int hss_open(int port, void *pdev,
int i, irq;
if (!port)
irq = gpio_irq(GPIO_HSS0_DCD_N);
irq = IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N);
else
irq = gpio_irq(GPIO_HSS1_DCD_N);
irq = IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N);
gpio_line_get(port ? GPIO_HSS1_DCD_N : GPIO_HSS0_DCD_N, &i);
set_carrier_cb(pdev, !i);
@ -188,8 +187,8 @@ static int hss_open(int port, void *pdev,
static void hss_close(int port, void *pdev)
{
free_irq(port ? gpio_irq(GPIO_HSS1_DCD_N) : gpio_irq(GPIO_HSS0_DCD_N),
pdev);
free_irq(port ? IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N) :
IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N), pdev);
set_carrier_cb_tab[!!port] = NULL; /* catch bugs */
set_control(port ? CONTROL_HSS1_DTR_N : CONTROL_HSS0_DTR_N, 1);
@ -421,8 +420,8 @@ static void __init gmlr_init(void)
gpio_line_config(GPIO_HSS1_RTS_N, IXP4XX_GPIO_OUT);
gpio_line_config(GPIO_HSS0_DCD_N, IXP4XX_GPIO_IN);
gpio_line_config(GPIO_HSS1_DCD_N, IXP4XX_GPIO_IN);
set_irq_type(gpio_irq(GPIO_HSS0_DCD_N), IRQ_TYPE_EDGE_BOTH);
set_irq_type(gpio_irq(GPIO_HSS1_DCD_N), IRQ_TYPE_EDGE_BOTH);
set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N), IRQ_TYPE_EDGE_BOTH);
set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N), IRQ_TYPE_EDGE_BOTH);
set_control(CONTROL_HSS0_DTR_N, 1);
set_control(CONTROL_HSS1_DTR_N, 1);
@ -442,10 +441,10 @@ static void __init gmlr_init(void)
#ifdef CONFIG_PCI
static void __init gmlr_pci_preinit(void)
{
set_irq_type(IRQ_ETHA, IRQ_TYPE_LEVEL_LOW);
set_irq_type(IRQ_ETHB, IRQ_TYPE_LEVEL_LOW);
set_irq_type(IRQ_NEC, IRQ_TYPE_LEVEL_LOW);
set_irq_type(IRQ_MPCI, IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHA), IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHB), IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_NEC), IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_MPCI), IRQ_TYPE_LEVEL_LOW);
ixp4xx_pci_preinit();
}
@ -466,10 +465,10 @@ static void __init gmlr_pci_postinit(void)
static int __init gmlr_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
switch(slot) {
case SLOT_ETHA: return IRQ_ETHA;
case SLOT_ETHB: return IRQ_ETHB;
case SLOT_NEC: return IRQ_NEC;
default: return IRQ_MPCI;
case SLOT_ETHA: return IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHA);
case SLOT_ETHB: return IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHB);
case SLOT_NEC: return IXP4XX_GPIO_IRQ(GPIO_IRQ_NEC);
default: return IXP4XX_GPIO_IRQ(GPIO_IRQ_MPCI);
}
}

40
arch/arm/mach-ixp4xx/gtwx5715-pci.c
View File

@ -26,14 +26,16 @@
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/irq.h>
#include <asm/mach-types.h>
#include <mach/hardware.h>
#include <mach/gtwx5715.h>
#include <asm/mach/pci.h>
#define SLOT0_DEVID 0
#define SLOT1_DEVID 1
#define INTA 10 /* slot 1 has INTA and INTB crossed */
#define INTB 11
/*
* The exact GPIO pins and IRQs are defined in arch-ixp4xx/gtwx5715.h
* Slot 0 isn't actually populated with a card connector but
* we initialize it anyway in case a future version has the
* slot populated or someone with good soldering skills has
@ -41,32 +43,26 @@
*/
void __init gtwx5715_pci_preinit(void)
{
set_irq_type(GTWX5715_PCI_SLOT0_INTA_IRQ, IRQ_TYPE_LEVEL_LOW);
set_irq_type(GTWX5715_PCI_SLOT0_INTB_IRQ, IRQ_TYPE_LEVEL_LOW);
set_irq_type(GTWX5715_PCI_SLOT1_INTA_IRQ, IRQ_TYPE_LEVEL_LOW);
set_irq_type(GTWX5715_PCI_SLOT1_INTB_IRQ, IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
ixp4xx_pci_preinit();
}
static int __init gtwx5715_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
int rc;
static int gtwx5715_irqmap
[GTWX5715_PCI_SLOT_COUNT]
[GTWX5715_PCI_INT_PIN_COUNT] = {
{GTWX5715_PCI_SLOT0_INTA_IRQ, GTWX5715_PCI_SLOT0_INTB_IRQ},
{GTWX5715_PCI_SLOT1_INTA_IRQ, GTWX5715_PCI_SLOT1_INTB_IRQ},
};
int rc = -1;
if (slot >= GTWX5715_PCI_SLOT_COUNT ||
pin >= GTWX5715_PCI_INT_PIN_COUNT) rc = -1;
else
rc = gtwx5715_irqmap[slot][pin-1];
if ((slot == SLOT0_DEVID && pin == 1) ||
(slot == SLOT1_DEVID && pin == 2))
rc = IXP4XX_GPIO_IRQ(INTA);
else if ((slot == SLOT0_DEVID && pin == 2) ||
(slot == SLOT1_DEVID && pin == 1))
rc = IXP4XX_GPIO_IRQ(INTB);
printk("%s: Mapped slot %d pin %d to IRQ %d\n", __func__, slot, pin, rc);
return(rc);
printk(KERN_INFO "%s: Mapped slot %d pin %d to IRQ %d\n",
__func__, slot, pin, rc);
return rc;
}
struct hw_pci gtwx5715_pci __initdata = {
@ -81,9 +77,7 @@ struct hw_pci gtwx5715_pci __initdata = {
int __init gtwx5715_pci_init(void)
{
if (machine_is_gtwx5715())
{
pci_common_init(&gtwx5715_pci);
}
return 0;
}

30
arch/arm/mach-ixp4xx/gtwx5715-setup.c
View File

@ -28,7 +28,6 @@
#include <linux/tty.h>
#include <linux/serial_8250.h>
#include <linux/slab.h>
#include <asm/types.h>
#include <asm/setup.h>
#include <asm/memory.h>
@ -37,7 +36,34 @@
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
#include <mach/gtwx5715.h>
/* GPIO 5,6,7 and 12 are hard wired to the Kendin KS8995M Switch
and operate as an SPI type interface. The details of the interface
are available on Kendin/Micrel's web site. */
#define GTWX5715_KSSPI_SELECT 5
#define GTWX5715_KSSPI_TXD 6
#define GTWX5715_KSSPI_CLOCK 7
#define GTWX5715_KSSPI_RXD 12
/* The "reset" button is wired to GPIO 3.
The GPIO is brought "low" when the button is pushed. */
#define GTWX5715_BUTTON_GPIO 3
/* Board Label Front Label
LED1 Power
LED2 Wireless-G
LED3 not populated but could be
LED4 Internet
LED5 - LED8 Controlled by KS8995M Switch
LED9 DMZ */
#define GTWX5715_LED1_GPIO 2
#define GTWX5715_LED2_GPIO 9
#define GTWX5715_LED3_GPIO 8
#define GTWX5715_LED4_GPIO 1
#define GTWX5715_LED9_GPIO 4
/*
* Xscale UART registers are 32 bits wide with only the least

39
arch/arm/mach-ixp4xx/include/mach/avila.h
View File

@ -1,39 +0,0 @@
/*
* arch/arm/mach-ixp4xx/include/mach/avila.h
*
* Gateworks Avila platform specific definitions
*
* Author: Michael-Luke Jones <mlj28@cam.ac.uk>
*
* Based on ixdp425.h
* Author: Deepak Saxena <dsaxena@plexity.net>
*
* Copyright 2004 (c) MontaVista, Software, Inc.
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __ASM_ARCH_HARDWARE_H__
#error "Do not include this directly, instead #include <mach/hardware.h>"
#endif
#define AVILA_SDA_PIN 7
#define AVILA_SCL_PIN 6
/*
* AVILA PCI IRQs
*/
#define AVILA_PCI_MAX_DEV 4
#define LOFT_PCI_MAX_DEV 6
#define AVILA_PCI_IRQ_LINES 4
/* PCI controller GPIO to IRQ pin mappings */
#define AVILA_PCI_INTA_PIN 11
#define AVILA_PCI_INTB_PIN 10
#define AVILA_PCI_INTC_PIN 9
#define AVILA_PCI_INTD_PIN 8

33
arch/arm/mach-ixp4xx/include/mach/coyote.h
View File

@ -1,33 +0,0 @@
/*
* arch/arm/mach-ixp4xx/include/mach/coyote.h
*
* ADI Engineering platform specific definitions
*
* Author: Deepak Saxena <dsaxena@plexity.net>
*
* Copyright 2004 (c) MontaVista, Software, Inc.
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __ASM_ARCH_HARDWARE_H__
#error "Do not include this directly, instead #include <mach/hardware.h>"
#endif
/* PCI controller GPIO to IRQ pin mappings */
#define COYOTE_PCI_SLOT0_PIN 6
#define COYOTE_PCI_SLOT1_PIN 11
#define COYOTE_PCI_SLOT0_DEVID 14
#define COYOTE_PCI_SLOT1_DEVID 15
#define COYOTE_IDE_BASE_PHYS IXP4XX_EXP_BUS_BASE(3)
#define COYOTE_IDE_BASE_VIRT 0xFFFE1000
#define COYOTE_IDE_REGION_SIZE 0x1000
#define COYOTE_IDE_DATA_PORT 0xFFFE10E0
#define COYOTE_IDE_CTRL_PORT 0xFFFE10FC
#define COYOTE_IDE_ERROR_PORT 0xFFFE10E2

52
arch/arm/mach-ixp4xx/include/mach/dsmg600.h
View File

@ -1,52 +0,0 @@
/*
* DSM-G600 platform specific definitions
*
* Copyright (C) 2006 Tower Technologies
* Author: Alessandro Zummo <a.zummo@towertech.it>
*
* based on ixdp425.h:
* Copyright 2004 (C) MontaVista, Software, Inc.
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __ASM_ARCH_HARDWARE_H__
#error "Do not include this directly, instead #include <mach/hardware.h>"
#endif
#define DSMG600_SDA_PIN 5
#define DSMG600_SCL_PIN 4
/*
* DSMG600 PCI IRQs
*/
#define DSMG600_PCI_MAX_DEV 4
#define DSMG600_PCI_IRQ_LINES 3
/* PCI controller GPIO to IRQ pin mappings */
#define DSMG600_PCI_INTA_PIN 11
#define DSMG600_PCI_INTB_PIN 10
#define DSMG600_PCI_INTC_PIN 9
#define DSMG600_PCI_INTD_PIN 8
#define DSMG600_PCI_INTE_PIN 7
#define DSMG600_PCI_INTF_PIN 6
/* DSM-G600 Timer Setting */
#define DSMG600_FREQ 66000000
/* Buttons */
#define DSMG600_PB_GPIO 15 /* power button */
#define DSMG600_RB_GPIO 3 /* reset button */
/* Power control */
#define DSMG600_PO_GPIO 2 /* power off */
/* LEDs */
#define DSMG600_LED_PWR_GPIO 0
#define DSMG600_LED_WLAN_GPIO 14

50
arch/arm/mach-ixp4xx/include/mach/fsg.h
View File

@ -1,50 +0,0 @@
/*
* arch/arm/mach-ixp4xx/include/mach/fsg.h
*
* Freecom FSG-3 platform specific definitions
*
* Author: Rod Whitby <rod@whitby.id.au>
* Author: Tomasz Chmielewski <mangoo@wpkg.org>
* Maintainers: http://www.nslu2-linux.org
*
* Based on coyote.h by
* Copyright 2004 (c) MontaVista, Software, Inc.
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __ASM_ARCH_HARDWARE_H__
#error "Do not include this directly, instead #include <mach/hardware.h>"
#endif
#define FSG_SDA_PIN 12
#define FSG_SCL_PIN 13
/*
* FSG PCI IRQs
*/
#define FSG_PCI_MAX_DEV 3
#define FSG_PCI_IRQ_LINES 3
/* PCI controller GPIO to IRQ pin mappings */
#define FSG_PCI_INTA_PIN 6
#define FSG_PCI_INTB_PIN 7
#define FSG_PCI_INTC_PIN 5
/* Buttons */
#define FSG_SB_GPIO 4 /* sync button */
#define FSG_RB_GPIO 9 /* reset button */
#define FSG_UB_GPIO 10 /* usb button */
/* LEDs */
#define FSG_LED_WLAN_BIT 0
#define FSG_LED_WAN_BIT 1
#define FSG_LED_SATA_BIT 2
#define FSG_LED_USB_BIT 4
#define FSG_LED_RING_BIT 5
#define FSG_LED_SYNC_BIT 7

2
arch/arm/mach-ixp4xx/include/mach/gpio.h
View File

@ -70,7 +70,7 @@ static inline void gpio_set_value(unsigned gpio, int value)
#include <asm-generic/gpio.h> /* cansleep wrappers */
extern int gpio_to_irq(int gpio);
extern int irq_to_gpio(int gpio);
extern int irq_to_gpio(unsigned int irq);
#endif

116
arch/arm/mach-ixp4xx/include/mach/gtwx5715.h
View File

@ -1,116 +0,0 @@
/*
* arch/arm/mach-ixp4xx/include/mach/gtwx5715.h
*
* Gemtek GTWX5715 Gateway (Linksys WRV54G)
*
* Copyright 2004 (c) George T. Joseph
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#ifndef __ASM_ARCH_HARDWARE_H__
#error "Do not include this directly, instead #include <mach/hardware.h>"
#endif
#include "irqs.h"
#define GTWX5715_GPIO0 0
#define GTWX5715_GPIO1 1
#define GTWX5715_GPIO2 2
#define GTWX5715_GPIO3 3
#define GTWX5715_GPIO4 4
#define GTWX5715_GPIO5 5
#define GTWX5715_GPIO6 6
#define GTWX5715_GPIO7 7
#define GTWX5715_GPIO8 8
#define GTWX5715_GPIO9 9
#define GTWX5715_GPIO10 10
#define GTWX5715_GPIO11 11
#define GTWX5715_GPIO12 12
#define GTWX5715_GPIO13 13
#define GTWX5715_GPIO14 14
#define GTWX5715_GPIO0_IRQ IRQ_IXP4XX_GPIO0
#define GTWX5715_GPIO1_IRQ IRQ_IXP4XX_GPIO1
#define GTWX5715_GPIO2_IRQ IRQ_IXP4XX_GPIO2
#define GTWX5715_GPIO3_IRQ IRQ_IXP4XX_GPIO3
#define GTWX5715_GPIO4_IRQ IRQ_IXP4XX_GPIO4
#define GTWX5715_GPIO5_IRQ IRQ_IXP4XX_GPIO5
#define GTWX5715_GPIO6_IRQ IRQ_IXP4XX_GPIO6
#define GTWX5715_GPIO7_IRQ IRQ_IXP4XX_GPIO7
#define GTWX5715_GPIO8_IRQ IRQ_IXP4XX_GPIO8
#define GTWX5715_GPIO9_IRQ IRQ_IXP4XX_GPIO9
#define GTWX5715_GPIO10_IRQ IRQ_IXP4XX_GPIO10
#define GTWX5715_GPIO11_IRQ IRQ_IXP4XX_GPIO11
#define GTWX5715_GPIO12_IRQ IRQ_IXP4XX_GPIO12
#define GTWX5715_GPIO13_IRQ IRQ_IXP4XX_SW_INT1
#define GTWX5715_GPIO14_IRQ IRQ_IXP4XX_SW_INT2
/* PCI controller GPIO to IRQ pin mappings
INTA INTB
SLOT 0 10 11
SLOT 1 11 10
*/
#define GTWX5715_PCI_SLOT0_DEVID 0
#define GTWX5715_PCI_SLOT0_INTA_GPIO GTWX5715_GPIO10
#define GTWX5715_PCI_SLOT0_INTB_GPIO GTWX5715_GPIO11
#define GTWX5715_PCI_SLOT0_INTA_IRQ GTWX5715_GPIO10_IRQ
#define GTWX5715_PCI_SLOT0_INTB_IRQ GTWX5715_GPIO11_IRQ
#define GTWX5715_PCI_SLOT1_DEVID 1
#define GTWX5715_PCI_SLOT1_INTA_GPIO GTWX5715_GPIO11
#define GTWX5715_PCI_SLOT1_INTB_GPIO GTWX5715_GPIO10
#define GTWX5715_PCI_SLOT1_INTA_IRQ GTWX5715_GPIO11_IRQ
#define GTWX5715_PCI_SLOT1_INTB_IRQ GTWX5715_GPIO10_IRQ
#define GTWX5715_PCI_SLOT_COUNT 2
#define GTWX5715_PCI_INT_PIN_COUNT 2
/*
* GPIO 5,6,7 and12 are hard wired to the Kendin KS8995M Switch
* and operate as an SPI type interface. The details of the interface
* are available on Kendin/Micrel's web site.
*/
#define GTWX5715_KSSPI_SELECT GTWX5715_GPIO5
#define GTWX5715_KSSPI_TXD GTWX5715_GPIO6
#define GTWX5715_KSSPI_CLOCK GTWX5715_GPIO7
#define GTWX5715_KSSPI_RXD GTWX5715_GPIO12
/*
* The "reset" button is wired to GPIO 3.
* The GPIO is brought "low" when the button is pushed.
*/
#define GTWX5715_BUTTON_GPIO GTWX5715_GPIO3
#define GTWX5715_BUTTON_IRQ GTWX5715_GPIO3_IRQ
/*
* Board Label Front Label
* LED1 Power
* LED2 Wireless-G
* LED3 not populated but could be
* LED4 Internet
* LED5 - LED8 Controlled by KS8995M Switch
* LED9 DMZ
*/
#define GTWX5715_LED1_GPIO GTWX5715_GPIO2
#define GTWX5715_LED2_GPIO GTWX5715_GPIO9
#define GTWX5715_LED3_GPIO GTWX5715_GPIO8
#define GTWX5715_LED4_GPIO GTWX5715_GPIO1
#define GTWX5715_LED9_GPIO GTWX5715_GPIO4

18
arch/arm/mach-ixp4xx/include/mach/hardware.h
View File

@ -18,7 +18,13 @@
#define __ASM_ARCH_HARDWARE_H__
#define PCIBIOS_MIN_IO 0x00001000
#define PCIBIOS_MIN_MEM (cpu_is_ixp43x() ? 0x40000000 : 0x48000000)
#ifdef CONFIG_IXP4XX_INDIRECT_PCI
#define PCIBIOS_MIN_MEM 0x10000000 /* 1 GB of indirect PCI MMIO space */
#define PCIBIOS_MAX_MEM 0x4FFFFFFF
#else
#define PCIBIOS_MIN_MEM 0x48000000 /* 64 MB of PCI MMIO space */
#define PCIBIOS_MAX_MEM 0x4BFFFFFF
#endif
/*
* We override the standard dma-mask routines for bouncing.
@ -37,14 +43,4 @@
/* Platform helper functions and definitions */
#include "platform.h"
/* Platform specific details */
#include "ixdp425.h"
#include "avila.h"
#include "coyote.h"
#include "prpmc1100.h"
#include "nslu2.h"
#include "nas100d.h"
#include "dsmg600.h"
#include "fsg.h"
#endif /* _ASM_ARCH_HARDWARE_H */

301
arch/arm/mach-ixp4xx/include/mach/io.h
View File

@ -26,22 +26,20 @@ extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data);
/*
* IXP4xx provides two methods of accessing PCI memory space:
*
* 1) A direct mapped window from 0x48000000 to 0x4bffffff (64MB).
* 1) A direct mapped window from 0x48000000 to 0x4BFFFFFF (64MB).
* To access PCI via this space, we simply ioremap() the BAR
* into the kernel and we can use the standard read[bwl]/write[bwl]
* macros. This is the preffered method due to speed but it
* limits the system to just 64MB of PCI memory. This can be
* problamatic if using video cards and other memory-heavy
* targets.
*
* 2) If > 64MB of memory space is required, the IXP4xx can be configured
* to use indirect registers to access PCI (as we do below for I/O
* transactions). This allows for up to 128MB (0x48000000 to 0x4fffffff)
* of memory on the bus. The disadvantage of this is that every
* PCI access requires three local register accesses plus a spinlock,
* but in some cases the performance hit is acceptable. In addition,
* you cannot mmap() PCI devices in this case.
* problematic if using video cards and other memory-heavy targets.
*
* 2) If > 64MB of memory space is required, the IXP4xx can use indirect
* registers to access the whole 4 GB of PCI memory space (as we do below
* for I/O transactions). This allows currently for up to 1 GB (0x10000000
* to 0x4FFFFFFF) of memory on the bus. The disadvantage of this is that
* every PCI access requires three local register accesses plus a spinlock,
* but in some cases the performance hit is acceptable. In addition, you
* cannot mmap() PCI devices in this case.
*/
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
@ -55,48 +53,52 @@ extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data);
* access registers. If something outside of PCI is ioremap'd, we
* fallback to the default.
*/
static inline void __iomem *
__ixp4xx_ioremap(unsigned long addr, size_t size, unsigned int mtype)
static inline int is_pci_memory(u32 addr)
{
if((addr < PCIBIOS_MIN_MEM) || (addr > 0x4fffffff))
return (addr >= PCIBIOS_MIN_MEM) && (addr <= 0x4FFFFFFF);
}
static inline void __iomem * __indirect_ioremap(unsigned long addr, size_t size,
unsigned int mtype)
{
if (!is_pci_memory(addr))
return __arm_ioremap(addr, size, mtype);
return (void __iomem *)addr;
}
static inline void
__ixp4xx_iounmap(void __iomem *addr)
static inline void __indirect_iounmap(void __iomem *addr)
{
if ((__force u32)addr >= VMALLOC_START)
if (!is_pci_memory((__force u32)addr))
__iounmap(addr);
}
#define __arch_ioremap(a, s, f) __ixp4xx_ioremap(a, s, f)
#define __arch_iounmap(a) __ixp4xx_iounmap(a)
#define __arch_ioremap(a, s, f) __indirect_ioremap(a, s, f)
#define __arch_iounmap(a) __indirect_iounmap(a)
#define writeb(v, p) __ixp4xx_writeb(v, p)
#define writew(v, p) __ixp4xx_writew(v, p)
#define writel(v, p) __ixp4xx_writel(v, p)
#define writeb(v, p) __indirect_writeb(v, p)
#define writew(v, p) __indirect_writew(v, p)
#define writel(v, p) __indirect_writel(v, p)
#define writesb(p, v, l) __ixp4xx_writesb(p, v, l)
#define writesw(p, v, l) __ixp4xx_writesw(p, v, l)
#define writesl(p, v, l) __ixp4xx_writesl(p, v, l)
#define writesb(p, v, l) __indirect_writesb(p, v, l)
#define writesw(p, v, l) __indirect_writesw(p, v, l)
#define writesl(p, v, l) __indirect_writesl(p, v, l)
#define readb(p) __ixp4xx_readb(p)
#define readw(p) __ixp4xx_readw(p)
#define readl(p) __ixp4xx_readl(p)
#define readb(p) __indirect_readb(p)
#define readw(p) __indirect_readw(p)
#define readl(p) __indirect_readl(p)
#define readsb(p, v, l) __ixp4xx_readsb(p, v, l)
#define readsw(p, v, l) __ixp4xx_readsw(p, v, l)
#define readsl(p, v, l) __ixp4xx_readsl(p, v, l)
#define readsb(p, v, l) __indirect_readsb(p, v, l)
#define readsw(p, v, l) __indirect_readsw(p, v, l)
#define readsl(p, v, l) __indirect_readsl(p, v, l)
static inline void
__ixp4xx_writeb(u8 value, volatile void __iomem *p)
static inline void __indirect_writeb(u8 value, volatile void __iomem *p)
{
u32 addr = (u32)p;
u32 n, byte_enables, data;
if (addr >= VMALLOC_START) {
if (!is_pci_memory(addr)) {
__raw_writeb(value, addr);
return;
}
@ -107,20 +109,19 @@ __ixp4xx_writeb(u8 value, volatile void __iomem *p)
ixp4xx_pci_write(addr, byte_enables | NP_CMD_MEMWRITE, data);
}
static inline void
__ixp4xx_writesb(volatile void __iomem *bus_addr, const u8 *vaddr, int count)
static inline void __indirect_writesb(volatile void __iomem *bus_addr,
const u8 *vaddr, int count)
{
while (count--)
writeb(*vaddr++, bus_addr);
}
static inline void
__ixp4xx_writew(u16 value, volatile void __iomem *p)
static inline void __indirect_writew(u16 value, volatile void __iomem *p)
{
u32 addr = (u32)p;
u32 n, byte_enables, data;
if (addr >= VMALLOC_START) {
if (!is_pci_memory(addr)) {
__raw_writew(value, addr);
return;
}
@ -131,18 +132,18 @@ __ixp4xx_writew(u16 value, volatile void __iomem *p)
ixp4xx_pci_write(addr, byte_enables | NP_CMD_MEMWRITE, data);
}
static inline void
__ixp4xx_writesw(volatile void __iomem *bus_addr, const u16 *vaddr, int count)
static inline void __indirect_writesw(volatile void __iomem *bus_addr,
const u16 *vaddr, int count)
{
while (count--)
writew(*vaddr++, bus_addr);
}
static inline void
__ixp4xx_writel(u32 value, volatile void __iomem *p)
static inline void __indirect_writel(u32 value, volatile void __iomem *p)
{
u32 addr = (__force u32)p;
if (addr >= VMALLOC_START) {
if (!is_pci_memory(addr)) {
__raw_writel(value, p);
return;
}
@ -150,20 +151,19 @@ __ixp4xx_writel(u32 value, volatile void __iomem *p)
ixp4xx_pci_write(addr, NP_CMD_MEMWRITE, value);
}
static inline void
__ixp4xx_writesl(volatile void __iomem *bus_addr, const u32 *vaddr, int count)
static inline void __indirect_writesl(volatile void __iomem *bus_addr,
const u32 *vaddr, int count)
{
while (count--)
writel(*vaddr++, bus_addr);
}
static inline unsigned char
__ixp4xx_readb(const volatile void __iomem *p)
static inline unsigned char __indirect_readb(const volatile void __iomem *p)
{
u32 addr = (u32)p;
u32 n, byte_enables, data;
if (addr >= VMALLOC_START)
if (!is_pci_memory(addr))
return __raw_readb(addr);
n = addr % 4;
@ -174,20 +174,19 @@ __ixp4xx_readb(const volatile void __iomem *p)
return data >> (8*n);
}
static inline void
__ixp4xx_readsb(const volatile void __iomem *bus_addr, u8 *vaddr, u32 count)
static inline void __indirect_readsb(const volatile void __iomem *bus_addr,
u8 *vaddr, u32 count)
{
while (count--)
*vaddr++ = readb(bus_addr);
}
static inline unsigned short
__ixp4xx_readw(const volatile void __iomem *p)
static inline unsigned short __indirect_readw(const volatile void __iomem *p)
{
u32 addr = (u32)p;
u32 n, byte_enables, data;
if (addr >= VMALLOC_START)
if (!is_pci_memory(addr))
return __raw_readw(addr);
n = addr % 4;
@ -198,20 +197,19 @@ __ixp4xx_readw(const volatile void __iomem *p)
return data>>(8*n);
}
static inline void
__ixp4xx_readsw(const volatile void __iomem *bus_addr, u16 *vaddr, u32 count)
static inline void __indirect_readsw(const volatile void __iomem *bus_addr,
u16 *vaddr, u32 count)
{
while (count--)
*vaddr++ = readw(bus_addr);
}
static inline unsigned long
__ixp4xx_readl(const volatile void __iomem *p)
static inline unsigned long __indirect_readl(const volatile void __iomem *p)
{
u32 addr = (__force u32)p;
u32 data;
if (addr >= VMALLOC_START)
if (!is_pci_memory(addr))
return __raw_readl(p);
if (ixp4xx_pci_read(addr, NP_CMD_MEMREAD, &data))
@ -220,8 +218,8 @@ __ixp4xx_readl(const volatile void __iomem *p)
return data;
}
static inline void
__ixp4xx_readsl(const volatile void __iomem *bus_addr, u32 *vaddr, u32 count)
static inline void __indirect_readsl(const volatile void __iomem *bus_addr,
u32 *vaddr, u32 count)
{
while (count--)
*vaddr++ = readl(bus_addr);
@ -235,7 +233,7 @@ __ixp4xx_readsl(const volatile void __iomem *bus_addr, u32 *vaddr, u32 count)
#define memcpy_fromio(a,c,l) _memcpy_fromio((a),(c),(l))
#define memcpy_toio(c,a,l) _memcpy_toio((c),(a),(l))
#endif
#endif /* CONFIG_IXP4XX_INDIRECT_PCI */
#ifndef CONFIG_PCI
@ -250,25 +248,8 @@ __ixp4xx_readsl(const volatile void __iomem *bus_addr, u32 *vaddr, u32 count)
* transaction. This means that we need to override the default
* I/O functions.
*/
#define outb(p, v) __ixp4xx_outb(p, v)
#define outw(p, v) __ixp4xx_outw(p, v)
#define outl(p, v) __ixp4xx_outl(p, v)
#define outsb(p, v, l) __ixp4xx_outsb(p, v, l)
#define outsw(p, v, l) __ixp4xx_outsw(p, v, l)
#define outsl(p, v, l) __ixp4xx_outsl(p, v, l)
#define inb(p) __ixp4xx_inb(p)
#define inw(p) __ixp4xx_inw(p)
#define inl(p) __ixp4xx_inl(p)
#define insb(p, v, l) __ixp4xx_insb(p, v, l)
#define insw(p, v, l) __ixp4xx_insw(p, v, l)
#define insl(p, v, l) __ixp4xx_insl(p, v, l)
static inline void
__ixp4xx_outb(u8 value, u32 addr)
static inline void outb(u8 value, u32 addr)
{
u32 n, byte_enables, data;
n = addr % 4;
@ -277,15 +258,13 @@ __ixp4xx_outb(u8 value, u32 addr)
ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data);
}
static inline void
__ixp4xx_outsb(u32 io_addr, const u8 *vaddr, u32 count)
static inline void outsb(u32 io_addr, const u8 *vaddr, u32 count)
{
while (count--)
outb(*vaddr++, io_addr);
}
static inline void
__ixp4xx_outw(u16 value, u32 addr)
static inline void outw(u16 value, u32 addr)
{
u32 n, byte_enables, data;
n = addr % 4;
@ -294,28 +273,24 @@ __ixp4xx_outw(u16 value, u32 addr)
ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data);
}
static inline void
__ixp4xx_outsw(u32 io_addr, const u16 *vaddr, u32 count)
static inline void outsw(u32 io_addr, const u16 *vaddr, u32 count)
{
while (count--)
outw(cpu_to_le16(*vaddr++), io_addr);
}
static inline void
__ixp4xx_outl(u32 value, u32 addr)
static inline void outl(u32 value, u32 addr)
{
ixp4xx_pci_write(addr, NP_CMD_IOWRITE, value);
}
static inline void
__ixp4xx_outsl(u32 io_addr, const u32 *vaddr, u32 count)
static inline void outsl(u32 io_addr, const u32 *vaddr, u32 count)
{
while (count--)
outl(*vaddr++, io_addr);
outl(cpu_to_le32(*vaddr++), io_addr);
}
static inline u8
__ixp4xx_inb(u32 addr)
static inline u8 inb(u32 addr)
{
u32 n, byte_enables, data;
n = addr % 4;
@ -326,15 +301,13 @@ __ixp4xx_inb(u32 addr)
return data >> (8*n);
}
static inline void
__ixp4xx_insb(u32 io_addr, u8 *vaddr, u32 count)
static inline void insb(u32 io_addr, u8 *vaddr, u32 count)
{
while (count--)
*vaddr++ = inb(io_addr);
}
static inline u16
__ixp4xx_inw(u32 addr)
static inline u16 inw(u32 addr)
{
u32 n, byte_enables, data;
n = addr % 4;
@ -345,15 +318,13 @@ __ixp4xx_inw(u32 addr)
return data>>(8*n);
}
static inline void
__ixp4xx_insw(u32 io_addr, u16 *vaddr, u32 count)
static inline void insw(u32 io_addr, u16 *vaddr, u32 count)
{
while (count--)
*vaddr++ = le16_to_cpu(inw(io_addr));
}
static inline u32
__ixp4xx_inl(u32 addr)
static inline u32 inl(u32 addr)
{
u32 data;
if (ixp4xx_pci_read(addr, NP_CMD_IOREAD, &data))
@ -362,11 +333,10 @@ __ixp4xx_inl(u32 addr)
return data;
}
static inline void
__ixp4xx_insl(u32 io_addr, u32 *vaddr, u32 count)
static inline void insl(u32 io_addr, u32 *vaddr, u32 count)
{
while (count--)
*vaddr++ = inl(io_addr);
*vaddr++ = le32_to_cpu(inl(io_addr));
}
#define PIO_OFFSET 0x10000UL
@ -374,194 +344,183 @@ __ixp4xx_insl(u32 io_addr, u32 *vaddr, u32 count)
#define __is_io_address(p) (((unsigned long)p >= PIO_OFFSET) && \
((unsigned long)p <= (PIO_MASK + PIO_OFFSET)))
static inline unsigned int
__ixp4xx_ioread8(const void __iomem *addr)
#define ioread8(p) ioread8(p)
static inline unsigned int ioread8(const void __iomem *addr)
{
unsigned long port = (unsigned long __force)addr;
if (__is_io_address(port))
return (unsigned int)__ixp4xx_inb(port & PIO_MASK);
return (unsigned int)inb(port & PIO_MASK);
else
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
return (unsigned int)__raw_readb(port);
#else
return (unsigned int)__ixp4xx_readb(addr);
return (unsigned int)__indirect_readb(addr);
#endif
}
static inline void
__ixp4xx_ioread8_rep(const void __iomem *addr, void *vaddr, u32 count)
#define ioread8_rep(p, v, c) ioread8_rep(p, v, c)
static inline void ioread8_rep(const void __iomem *addr, void *vaddr, u32 count)
{
unsigned long port = (unsigned long __force)addr;
if (__is_io_address(port))
__ixp4xx_insb(port & PIO_MASK, vaddr, count);
insb(port & PIO_MASK, vaddr, count);
else
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
__raw_readsb(addr, vaddr, count);
#else
__ixp4xx_readsb(addr, vaddr, count);
__indirect_readsb(addr, vaddr, count);
#endif
}
static inline unsigned int
__ixp4xx_ioread16(const void __iomem *addr)
#define ioread16(p) ioread16(p)
static inline unsigned int ioread16(const void __iomem *addr)
{
unsigned long port = (unsigned long __force)addr;
if (__is_io_address(port))
return (unsigned int)__ixp4xx_inw(port & PIO_MASK);
return (unsigned int)inw(port & PIO_MASK);
else
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
return le16_to_cpu(__raw_readw((u32)port));
#else
return (unsigned int)__ixp4xx_readw(addr);
return (unsigned int)__indirect_readw(addr);
#endif
}
static inline void
__ixp4xx_ioread16_rep(const void __iomem *addr, void *vaddr, u32 count)
#define ioread16_rep(p, v, c) ioread16_rep(p, v, c)
static inline void ioread16_rep(const void __iomem *addr, void *vaddr,
u32 count)
{
unsigned long port = (unsigned long __force)addr;
if (__is_io_address(port))
__ixp4xx_insw(port & PIO_MASK, vaddr, count);
insw(port & PIO_MASK, vaddr, count);
else
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
__raw_readsw(addr, vaddr, count);
#else
__ixp4xx_readsw(addr, vaddr, count);
__indirect_readsw(addr, vaddr, count);
#endif
}
static inline unsigned int
__ixp4xx_ioread32(const void __iomem *addr)
#define ioread32(p) ioread32(p)
static inline unsigned int ioread32(const void __iomem *addr)
{
unsigned long port = (unsigned long __force)addr;
if (__is_io_address(port))
return (unsigned int)__ixp4xx_inl(port & PIO_MASK);
return (unsigned int)inl(port & PIO_MASK);
else {
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
return le32_to_cpu((__force __le32)__raw_readl(addr));
#else
return (unsigned int)__ixp4xx_readl(addr);
return (unsigned int)__indirect_readl(addr);
#endif
}
}
static inline void
__ixp4xx_ioread32_rep(const void __iomem *addr, void *vaddr, u32 count)
#define ioread32_rep(p, v, c) ioread32_rep(p, v, c)
static inline void ioread32_rep(const void __iomem *addr, void *vaddr,
u32 count)
{
unsigned long port = (unsigned long __force)addr;
if (__is_io_address(port))
__ixp4xx_insl(port & PIO_MASK, vaddr, count);
insl(port & PIO_MASK, vaddr, count);
else
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
__raw_readsl(addr, vaddr, count);
#else
__ixp4xx_readsl(addr, vaddr, count);
__indirect_readsl(addr, vaddr, count);
#endif
}
static inline void
__ixp4xx_iowrite8(u8 value, void __iomem *addr)
#define iowrite8(v, p) iowrite8(v, p)
static inline void iowrite8(u8 value, void __iomem *addr)
{
unsigned long port = (unsigned long __force)addr;
if (__is_io_address(port))
__ixp4xx_outb(value, port & PIO_MASK);
outb(value, port & PIO_MASK);
else
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
__raw_writeb(value, port);
#else
__ixp4xx_writeb(value, addr);
__indirect_writeb(value, addr);
#endif
}
static inline void
__ixp4xx_iowrite8_rep(void __iomem *addr, const void *vaddr, u32 count)
#define iowrite8_rep(p, v, c) iowrite8_rep(p, v, c)
static inline void iowrite8_rep(void __iomem *addr, const void *vaddr,
u32 count)
{
unsigned long port = (unsigned long __force)addr;
if (__is_io_address(port))
__ixp4xx_outsb(port & PIO_MASK, vaddr, count);
outsb(port & PIO_MASK, vaddr, count);
else
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
__raw_writesb(addr, vaddr, count);
#else
__ixp4xx_writesb(addr, vaddr, count);
__indirect_writesb(addr, vaddr, count);
#endif
}
static inline void
__ixp4xx_iowrite16(u16 value, void __iomem *addr)
#define iowrite16(v, p) iowrite16(v, p)
static inline void iowrite16(u16 value, void __iomem *addr)
{
unsigned long port = (unsigned long __force)addr;
if (__is_io_address(port))
__ixp4xx_outw(value, port & PIO_MASK);
outw(value, port & PIO_MASK);
else
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
__raw_writew(cpu_to_le16(value), addr);
#else
__ixp4xx_writew(value, addr);
__indirect_writew(value, addr);
#endif
}
static inline void
__ixp4xx_iowrite16_rep(void __iomem *addr, const void *vaddr, u32 count)
#define iowrite16_rep(p, v, c) iowrite16_rep(p, v, c)
static inline void iowrite16_rep(void __iomem *addr, const void *vaddr,
u32 count)
{
unsigned long port = (unsigned long __force)addr;
if (__is_io_address(port))
__ixp4xx_outsw(port & PIO_MASK, vaddr, count);
outsw(port & PIO_MASK, vaddr, count);
else
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
__raw_writesw(addr, vaddr, count);
#else
__ixp4xx_writesw(addr, vaddr, count);
__indirect_writesw(addr, vaddr, count);
#endif
}
static inline void
__ixp4xx_iowrite32(u32 value, void __iomem *addr)
#define iowrite32(v, p) iowrite32(v, p)
static inline void iowrite32(u32 value, void __iomem *addr)
{
unsigned long port = (unsigned long __force)addr;
if (__is_io_address(port))
__ixp4xx_outl(value, port & PIO_MASK);
outl(value, port & PIO_MASK);
else
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
__raw_writel((u32 __force)cpu_to_le32(value), addr);
#else
__ixp4xx_writel(value, addr);
__indirect_writel(value, addr);
#endif
}
static inline void
__ixp4xx_iowrite32_rep(void __iomem *addr, const void *vaddr, u32 count)
#define iowrite32_rep(p, v, c) iowrite32_rep(p, v, c)
static inline void iowrite32_rep(void __iomem *addr, const void *vaddr,
u32 count)
{
unsigned long port = (unsigned long __force)addr;
if (__is_io_address(port))
__ixp4xx_outsl(port & PIO_MASK, vaddr, count);
outsl(port & PIO_MASK, vaddr, count);
else
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
__raw_writesl(addr, vaddr, count);
#else
__ixp4xx_writesl(addr, vaddr, count);
__indirect_writesl(addr, vaddr, count);
#endif
}
#define ioread8(p) __ixp4xx_ioread8(p)
#define ioread16(p) __ixp4xx_ioread16(p)
#define ioread32(p) __ixp4xx_ioread32(p)
#define ioread8_rep(p, v, c) __ixp4xx_ioread8_rep(p, v, c)
#define ioread16_rep(p, v, c) __ixp4xx_ioread16_rep(p, v, c)
#define ioread32_rep(p, v, c) __ixp4xx_ioread32_rep(p, v, c)
#define iowrite8(v,p) __ixp4xx_iowrite8(v,p)
#define iowrite16(v,p) __ixp4xx_iowrite16(v,p)
#define iowrite32(v,p) __ixp4xx_iowrite32(v,p)
#define iowrite8_rep(p, v, c) __ixp4xx_iowrite8_rep(p, v, c)
#define iowrite16_rep(p, v, c) __ixp4xx_iowrite16_rep(p, v, c)
#define iowrite32_rep(p, v, c) __ixp4xx_iowrite32_rep(p, v, c)
#define ioport_map(port, nr) ((void __iomem*)(port + PIO_OFFSET))
#define ioport_unmap(addr)
#endif // !CONFIG_PCI
#endif // __ASM_ARM_ARCH_IO_H
#endif /* CONFIG_PCI */
#endif /* __ASM_ARM_ARCH_IO_H */

69
arch/arm/mach-ixp4xx/include/mach/irqs.h
View File

@ -15,7 +15,6 @@
#ifndef _ARCH_IXP4XX_IRQS_H_
#define _ARCH_IXP4XX_IRQS_H_
#define IRQ_IXP4XX_NPEA 0
#define IRQ_IXP4XX_NPEB 1
#define IRQ_IXP4XX_NPEC 2
@ -59,6 +58,9 @@
#define IRQ_IXP4XX_MCU_ECC 61
#define IRQ_IXP4XX_EXP_PE 62
#define _IXP4XX_GPIO_IRQ(n) (IRQ_IXP4XX_GPIO ## n)
#define IXP4XX_GPIO_IRQ(n) _IXP4XX_GPIO_IRQ(n)
/*
* Only first 32 sources are valid if running on IXP42x systems
*/
@ -70,69 +72,4 @@
#define XSCALE_PMU_IRQ (IRQ_IXP4XX_XSCALE_PMU)
/*
* IXDP425 board IRQs
*/
#define IRQ_IXDP425_PCI_INTA IRQ_IXP4XX_GPIO11
#define IRQ_IXDP425_PCI_INTB IRQ_IXP4XX_GPIO10
#define IRQ_IXDP425_PCI_INTC IRQ_IXP4XX_GPIO9
#define IRQ_IXDP425_PCI_INTD IRQ_IXP4XX_GPIO8
/*
* Gateworks Avila board IRQs
*/
#define IRQ_AVILA_PCI_INTA IRQ_IXP4XX_GPIO11
#define IRQ_AVILA_PCI_INTB IRQ_IXP4XX_GPIO10
#define IRQ_AVILA_PCI_INTC IRQ_IXP4XX_GPIO9
#define IRQ_AVILA_PCI_INTD IRQ_IXP4XX_GPIO8
/*
* PrPMC1100 Board IRQs
*/
#define IRQ_PRPMC1100_PCI_INTA IRQ_IXP4XX_GPIO11
#define IRQ_PRPMC1100_PCI_INTB IRQ_IXP4XX_GPIO10
#define IRQ_PRPMC1100_PCI_INTC IRQ_IXP4XX_GPIO9
#define IRQ_PRPMC1100_PCI_INTD IRQ_IXP4XX_GPIO8
/*
* ADI Coyote Board IRQs
*/
#define IRQ_COYOTE_PCI_SLOT0 IRQ_IXP4XX_GPIO6
#define IRQ_COYOTE_PCI_SLOT1 IRQ_IXP4XX_GPIO11
#define IRQ_COYOTE_IDE IRQ_IXP4XX_GPIO5
/*
* NSLU2 board IRQs
*/
#define IRQ_NSLU2_PCI_INTA IRQ_IXP4XX_GPIO11
#define IRQ_NSLU2_PCI_INTB IRQ_IXP4XX_GPIO10
#define IRQ_NSLU2_PCI_INTC IRQ_IXP4XX_GPIO9
/*
* NAS100D board IRQs
*/
#define IRQ_NAS100D_PCI_INTA IRQ_IXP4XX_GPIO11
#define IRQ_NAS100D_PCI_INTB IRQ_IXP4XX_GPIO10
#define IRQ_NAS100D_PCI_INTC IRQ_IXP4XX_GPIO9
#define IRQ_NAS100D_PCI_INTD IRQ_IXP4XX_GPIO8
#define IRQ_NAS100D_PCI_INTE IRQ_IXP4XX_GPIO7
/*
* D-Link DSM-G600 RevA board IRQs
*/
#define IRQ_DSMG600_PCI_INTA IRQ_IXP4XX_GPIO11
#define IRQ_DSMG600_PCI_INTB IRQ_IXP4XX_GPIO10
#define IRQ_DSMG600_PCI_INTC IRQ_IXP4XX_GPIO9
#define IRQ_DSMG600_PCI_INTD IRQ_IXP4XX_GPIO8
#define IRQ_DSMG600_PCI_INTE IRQ_IXP4XX_GPIO7
#define IRQ_DSMG600_PCI_INTF IRQ_IXP4XX_GPIO6
/*
* Freecom FSG-3 Board IRQs
*/
#define IRQ_FSG_PCI_INTA IRQ_IXP4XX_GPIO6
#define IRQ_FSG_PCI_INTB IRQ_IXP4XX_GPIO7
#define IRQ_FSG_PCI_INTC IRQ_IXP4XX_GPIO5
#endif

39
arch/arm/mach-ixp4xx/include/mach/ixdp425.h
View File

@ -1,39 +0,0 @@
/*
* arch/arm/mach-ixp4xx/include/mach/ixdp425.h
*
* IXDP425 platform specific definitions
*
* Author: Deepak Saxena <dsaxena@plexity.net>
*
* Copyright 2004 (c) MontaVista, Software, Inc.
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __ASM_ARCH_HARDWARE_H__
#error "Do not include this directly, instead #include <mach/hardware.h>"
#endif
#define IXDP425_SDA_PIN 7
#define IXDP425_SCL_PIN 6
/*
* IXDP425 PCI IRQs
*/
#define IXDP425_PCI_MAX_DEV 4
#define IXDP425_PCI_IRQ_LINES 4
/* PCI controller GPIO to IRQ pin mappings */
#define IXDP425_PCI_INTA_PIN 11
#define IXDP425_PCI_INTB_PIN 10
#define IXDP425_PCI_INTC_PIN 9
#define IXDP425_PCI_INTD_PIN 8
/* NAND Flash pins */
#define IXDP425_NAND_NCE_PIN 12
#define IXDP425_NAND_CMD_BYTE 0x01
#define IXDP425_NAND_ADDR_BYTE 0x02

52
arch/arm/mach-ixp4xx/include/mach/nas100d.h
View File

@ -1,52 +0,0 @@
/*
* arch/arm/mach-ixp4xx/include/mach/nas100d.h
*
* NAS100D platform specific definitions
*
* Copyright (c) 2005 Tower Technologies
*
* Author: Alessandro Zummo <a.zummo@towertech.it>
*
* based on ixdp425.h:
* Copyright 2004 (c) MontaVista, Software, Inc.
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __ASM_ARCH_HARDWARE_H__
#error "Do not include this directly, instead #include <mach/hardware.h>"
#endif
#define NAS100D_SDA_PIN 5
#define NAS100D_SCL_PIN 6
/*
* NAS100D PCI IRQs
*/
#define NAS100D_PCI_MAX_DEV 3
#define NAS100D_PCI_IRQ_LINES 3
/* PCI controller GPIO to IRQ pin mappings */
#define NAS100D_PCI_INTA_PIN 11
#define NAS100D_PCI_INTB_PIN 10
#define NAS100D_PCI_INTC_PIN 9
#define NAS100D_PCI_INTD_PIN 8
#define NAS100D_PCI_INTE_PIN 7
/* Buttons */
#define NAS100D_PB_GPIO 14 /* power button */
#define NAS100D_RB_GPIO 4 /* reset button */
/* Power control */
#define NAS100D_PO_GPIO 12 /* power off */
/* LEDs */
#define NAS100D_LED_WLAN_GPIO 0
#define NAS100D_LED_DISK_GPIO 3
#define NAS100D_LED_PWR_GPIO 15

2
arch/arm/mach-ixp4xx/include/mach/npe.h
View File

@ -33,7 +33,7 @@ int npe_send_message(struct npe *npe, const void *msg, const char *what);
int npe_recv_message(struct npe *npe, void *msg, const char *what);
int npe_send_recv_message(struct npe *npe, void *msg, const char *what);
int npe_load_firmware(struct npe *npe, const char *name, struct device *dev);
struct npe *npe_request(int id);
struct npe *npe_request(unsigned id);
void npe_release(struct npe *npe);
#endif /* __IXP4XX_NPE_H */

55
arch/arm/mach-ixp4xx/include/mach/nslu2.h
View File

@ -1,55 +0,0 @@
/*
* arch/arm/mach-ixp4xx/include/mach/nslu2.h
*
* NSLU2 platform specific definitions
*
* Author: Mark Rakes <mrakes AT mac.com>
* Maintainers: http://www.nslu2-linux.org
*
* based on ixdp425.h:
* Copyright 2004 (c) MontaVista, Software, Inc.
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __ASM_ARCH_HARDWARE_H__
#error "Do not include this directly, instead #include <mach/hardware.h>"
#endif
#define NSLU2_SDA_PIN 7
#define NSLU2_SCL_PIN 6
/*
* NSLU2 PCI IRQs
*/
#define NSLU2_PCI_MAX_DEV 3
#define NSLU2_PCI_IRQ_LINES 3
/* PCI controller GPIO to IRQ pin mappings */
#define NSLU2_PCI_INTA_PIN 11
#define NSLU2_PCI_INTB_PIN 10
#define NSLU2_PCI_INTC_PIN 9
#define NSLU2_PCI_INTD_PIN 8
/* NSLU2 Timer */
#define NSLU2_FREQ 66000000
/* Buttons */
#define NSLU2_PB_GPIO 5 /* power button */
#define NSLU2_PO_GPIO 8 /* power off */
#define NSLU2_RB_GPIO 12 /* reset button */
/* Buzzer */
#define NSLU2_GPIO_BUZZ 4
/* LEDs */
#define NSLU2_LED_RED_GPIO 0
#define NSLU2_LED_GRN_GPIO 1
#define NSLU2_LED_DISK1_GPIO 3
#define NSLU2_LED_DISK2_GPIO 2

33
arch/arm/mach-ixp4xx/include/mach/prpmc1100.h
View File

@ -1,33 +0,0 @@
/*
* arch/arm/mach-ixp4xx/include/mach/prpmc1100.h
*
* Motorolla PrPMC1100 platform specific definitions
*
* Author: Deepak Saxena <dsaxena@plexity.net>
*
* Copyright 2004 (c) MontaVista, Software, Inc.
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __ASM_ARCH_HARDWARE_H__
#error "Do not include this directly, instead #include <mach/hardware.h>"
#endif
#define PRPMC1100_FLASH_BASE IXP4XX_EXP_BUS_CS0_BASE_PHYS
#define PRPMC1100_FLASH_SIZE IXP4XX_EXP_BUS_CSX_REGION_SIZE
#define PRPMC1100_PCI_MIN_DEVID 10
#define PRPMC1100_PCI_MAX_DEVID 16
#define PRPMC1100_PCI_IRQ_LINES 4
/* PCI controller GPIO to IRQ pin mappings */
#define PRPMC1100_PCI_INTA_PIN 11
#define PRPMC1100_PCI_INTB_PIN 10
#define PRPMC1100_PCI_INTC_PIN 9
#define PRPMC1100_PCI_INTD_PIN 8

2
arch/arm/mach-ixp4xx/include/mach/timex.h
View File

@ -10,6 +10,6 @@
* 66.66... MHz. We do a convulted calculation of CLOCK_TICK_RATE b/c the
* timer register ignores the bottom 2 bits of the LATCH value.
*/
#define FREQ 66666666
#define FREQ 66666000
#define CLOCK_TICK_RATE (((FREQ / HZ & ~IXP4XX_OST_RELOAD_MASK) + 1) * HZ)

41
arch/arm/mach-ixp4xx/ixdp425-pci.c
View File

@ -19,39 +19,43 @@
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/delay.h>
#include <asm/mach/pci.h>
#include <asm/irq.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
#define MAX_DEV 4
#define IRQ_LINES 4
/* PCI controller GPIO to IRQ pin mappings */
#define INTA 11
#define INTB 10
#define INTC 9
#define INTD 8
void __init ixdp425_pci_preinit(void)
{
set_irq_type(IRQ_IXDP425_PCI_INTA, IRQ_TYPE_LEVEL_LOW);
set_irq_type(IRQ_IXDP425_PCI_INTB, IRQ_TYPE_LEVEL_LOW);
set_irq_type(IRQ_IXDP425_PCI_INTC, IRQ_TYPE_LEVEL_LOW);
set_irq_type(IRQ_IXDP425_PCI_INTD, IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
ixp4xx_pci_preinit();
}
static int __init ixdp425_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
static int pci_irq_table[IXDP425_PCI_IRQ_LINES] = {
IRQ_IXDP425_PCI_INTA,
IRQ_IXDP425_PCI_INTB,
IRQ_IXDP425_PCI_INTC,
IRQ_IXDP425_PCI_INTD
static int pci_irq_table[IRQ_LINES] = {
IXP4XX_GPIO_IRQ(INTA),
IXP4XX_GPIO_IRQ(INTB),
IXP4XX_GPIO_IRQ(INTC),
IXP4XX_GPIO_IRQ(INTD)
};
int irq = -1;
if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES)
return pci_irq_table[(slot + pin - 2) % 4];
if (slot >= 1 && slot <= IXDP425_PCI_MAX_DEV &&
pin >= 1 && pin <= IXDP425_PCI_IRQ_LINES) {
irq = pci_irq_table[(slot + pin - 2) % 4];
}
return irq;
return -1;
}
struct hw_pci ixdp425_pci __initdata = {
@ -72,4 +76,3 @@ int __init ixdp425_pci_init(void)
}
subsys_initcall(ixdp425_pci_init);

10
arch/arm/mach-ixp4xx/ixdp425-setup.c
View File

@ -21,7 +21,6 @@
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>
#include <linux/delay.h>
#include <asm/types.h>
#include <asm/setup.h>
#include <asm/memory.h>
@ -31,6 +30,15 @@
#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
#define IXDP425_SDA_PIN 7
#define IXDP425_SCL_PIN 6
/* NAND Flash pins */
#define IXDP425_NAND_NCE_PIN 12
#define IXDP425_NAND_CMD_BYTE 0x01
#define IXDP425_NAND_ADDR_BYTE 0x02
static struct flash_platform_data ixdp425_flash_data = {
.map_name = "cfi_probe",
.width = 2,

2
arch/arm/mach-ixp4xx/ixp4xx_npe.c
View File

@ -665,7 +665,7 @@ err:
}
struct npe *npe_request(int id)
struct npe *npe_request(unsigned id)
{
if (id < NPE_COUNT)
if (npe_tab[id].valid)

41
arch/arm/mach-ixp4xx/nas100d-pci.c
View File

@ -18,37 +18,42 @@
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <asm/mach/pci.h>
#include <asm/mach-types.h>
#define MAX_DEV 3
#define IRQ_LINES 3
/* PCI controller GPIO to IRQ pin mappings */
#define INTA 11
#define INTB 10
#define INTC 9
#define INTD 8
#define INTE 7
void __init nas100d_pci_preinit(void)
{
set_irq_type(IRQ_NAS100D_PCI_INTA, IRQ_TYPE_LEVEL_LOW);
set_irq_type(IRQ_NAS100D_PCI_INTB, IRQ_TYPE_LEVEL_LOW);
set_irq_type(IRQ_NAS100D_PCI_INTC, IRQ_TYPE_LEVEL_LOW);
set_irq_type(IRQ_NAS100D_PCI_INTD, IRQ_TYPE_LEVEL_LOW);
set_irq_type(IRQ_NAS100D_PCI_INTE, IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW);
ixp4xx_pci_preinit();
}
static int __init nas100d_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
static int pci_irq_table[NAS100D_PCI_MAX_DEV][NAS100D_PCI_IRQ_LINES] =
{
{ IRQ_NAS100D_PCI_INTA, -1, -1 },
{ IRQ_NAS100D_PCI_INTB, -1, -1 },
{ IRQ_NAS100D_PCI_INTC, IRQ_NAS100D_PCI_INTD, IRQ_NAS100D_PCI_INTE },
static int pci_irq_table[MAX_DEV][IRQ_LINES] = {
{ IXP4XX_GPIO_IRQ(INTA), -1, -1 },
{ IXP4XX_GPIO_IRQ(INTB), -1, -1 },
{ IXP4XX_GPIO_IRQ(INTC), IXP4XX_GPIO_IRQ(INTD),
IXP4XX_GPIO_IRQ(INTE) },
};
int irq = -1;
if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES)
return pci_irq_table[slot - 1][pin - 1];
if (slot >= 1 && slot <= NAS100D_PCI_MAX_DEV &&
pin >= 1 && pin <= NAS100D_PCI_IRQ_LINES)
irq = pci_irq_table[slot-1][pin-1];
return irq;
return -1;
}
struct hw_pci __initdata nas100d_pci = {

16
arch/arm/mach-ixp4xx/nas100d-setup.c
View File

@ -29,12 +29,26 @@
#include <linux/i2c.h>
#include <linux/i2c-gpio.h>
#include <linux/io.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
#include <asm/gpio.h>
#define NAS100D_SDA_PIN 5
#define NAS100D_SCL_PIN 6
/* Buttons */
#define NAS100D_PB_GPIO 14 /* power button */
#define NAS100D_RB_GPIO 4 /* reset button */
/* Power control */
#define NAS100D_PO_GPIO 12 /* power off */
/* LEDs */
#define NAS100D_LED_WLAN_GPIO 0
#define NAS100D_LED_DISK_GPIO 3
#define NAS100D_LED_PWR_GPIO 15
static struct flash_platform_data nas100d_flash_data = {
.map_name = "cfi_probe",
.width = 2,

35
arch/arm/mach-ixp4xx/nslu2-pci.c
View File

@ -18,35 +18,38 @@
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <asm/mach/pci.h>
#include <asm/mach-types.h>
#define MAX_DEV 3
#define IRQ_LINES 3
/* PCI controller GPIO to IRQ pin mappings */
#define INTA 11
#define INTB 10
#define INTC 9
#define INTD 8
void __init nslu2_pci_preinit(void)
{
set_irq_type(IRQ_NSLU2_PCI_INTA, IRQ_TYPE_LEVEL_LOW);
set_irq_type(IRQ_NSLU2_PCI_INTB, IRQ_TYPE_LEVEL_LOW);
set_irq_type(IRQ_NSLU2_PCI_INTC, IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
ixp4xx_pci_preinit();
}
static int __init nslu2_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
static int pci_irq_table[NSLU2_PCI_IRQ_LINES] = {
IRQ_NSLU2_PCI_INTA,
IRQ_NSLU2_PCI_INTB,
IRQ_NSLU2_PCI_INTC,
static int pci_irq_table[IRQ_LINES] = {
IXP4XX_GPIO_IRQ(INTA),
IXP4XX_GPIO_IRQ(INTB),
IXP4XX_GPIO_IRQ(INTC),
};
int irq = -1;
if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES)
return pci_irq_table[(slot + pin - 2) % IRQ_LINES];
if (slot >= 1 && slot <= NSLU2_PCI_MAX_DEV &&
pin >= 1 && pin <= NSLU2_PCI_IRQ_LINES) {
irq = pci_irq_table[(slot + pin - 2) % NSLU2_PCI_IRQ_LINES];
}
return irq;
return -1;
}
struct hw_pci __initdata nslu2_pci = {

21
arch/arm/mach-ixp4xx/nslu2-setup.c
View File

@ -26,13 +26,32 @@
#include <linux/i2c.h>
#include <linux/i2c-gpio.h>
#include <linux/io.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
#include <asm/mach/time.h>
#include <asm/gpio.h>
#define NSLU2_SDA_PIN 7
#define NSLU2_SCL_PIN 6
/* NSLU2 Timer */
#define NSLU2_FREQ 66000000
/* Buttons */
#define NSLU2_PB_GPIO 5 /* power button */
#define NSLU2_PO_GPIO 8 /* power off */
#define NSLU2_RB_GPIO 12 /* reset button */
/* Buzzer */
#define NSLU2_GPIO_BUZZ 4
/* LEDs */
#define NSLU2_LED_RED_GPIO 0
#define NSLU2_LED_GRN_GPIO 1
#define NSLU2_LED_DISK1_GPIO 3
#define NSLU2_LED_DISK2_GPIO 2
static struct flash_platform_data nslu2_flash_data = {
.map_name = "cfi_probe",
.width = 2,

7
drivers/leds/leds-fsg.c
View File

@ -22,6 +22,13 @@
#include <mach/hardware.h>
#include <asm/io.h>
#define FSG_LED_WLAN_BIT 0
#define FSG_LED_WAN_BIT 1
#define FSG_LED_SATA_BIT 2
#define FSG_LED_USB_BIT 4
#define FSG_LED_RING_BIT 5
#define FSG_LED_SYNC_BIT 7
static short __iomem *latch_address;
static unsigned short latch_value;

2
drivers/net/arm/ixp4xx_eth.c
View File

@ -322,7 +322,7 @@ static int ixp4xx_mdio_write(struct mii_bus *bus, int phy_id, int location,
ret = ixp4xx_mdio_cmd(bus, phy_id, location, 1, val);
spin_unlock_irqrestore(&mdio_lock, flags);
#if DEBUG_MDIO
printk(KERN_DEBUG "%s #%i: MII read [%i] <- 0x%X, err = %i\n",
printk(KERN_DEBUG "%s #%i: MII write [%i] <- 0x%X, err = %i\n",
bus->name, phy_id, location, val, ret);
#endif
return ret;