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ARM: arm-soc fixes for 3.8, part 2 

Here are a few more fixes for 3.8. Two branches of fixes for Samsung
 platforms, including fixes for the audio build errors on all non-DT
 platforms. There's also a fixup to the sunxi device-tree file renames
 due to a bad patch application by me, and a fix for OMAP due to function
 renames merged through the powerpc tree.
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Merge tag 'fixes2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC fixes part 2 from Olof Johansson:
 "Here are a few more fixes for 3.8.  Two branches of fixes for Samsung
  platforms, including fixes for the audio build errors on all non-DT
  platforms.  There's also a fixup to the sunxi device-tree file renames
  due to a bad patch application by me, and a fix for OMAP due to
  function renames merged through the powerpc tree."

* tag 'fixes2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
  ARM: OMAP2+: Fix compillation error in mach-omap2/timer.c
  ARM: sunxi: rename device tree source files
  ARM: EXYNOS: Avoid passing the clks through platform data
  ARM: S5PV210: Avoid passing the clks through platform data
  ARM: S5P64X0: Add I2S clkdev support
  ARM: S5PC100: Add I2S clkdev support
  ARM: S3C64XX: Add I2S clkdev support
  ARM: EXYNOS: Fix MSHC clocks instance names
  ARM: EXYNOS: Fix NULL pointer dereference bug in SMDKV310
  ARM: EXYNOS: Fix NULL pointer dereference bug in SMDK4X12
  ARM: EXYNOS: Fix NULL pointer dereference bug in Origen
  ARM: SAMSUNG: Add missing include guard to gpio-core.h
  pinctrl: exynos5440/samsung: Staticize pcfgs
  pinctrl: samsung: Fix a typo in pinctrl-samsung.h
  ARM: EXYNOS: fix skip scu_enable() for EXYNOS5440
  ARM: EXYNOS: fix GIC using for EXYNOS5440
  ARM: EXYNOS: fix build error when MFC is not selected
This commit is contained in:
Linus Torvalds 2012-12-20 17:55:34 -08:00
parent af487e4209 2727da8595
commit f3dc1294c8
25 changed files with 204 additions and 183 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

0
arch/arm/boot/dts/sun4i-cubieboard.dts → arch/arm/boot/dts/sun4i-a10-cubieboard.dts
View File

0
arch/arm/boot/dts/sun4i.dtsi → arch/arm/boot/dts/sun4i-a10.dtsi
View File

0
arch/arm/boot/dts/sun5i-olinuxino.dts → arch/arm/boot/dts/sun5i-a13-olinuxino.dts
View File

0
arch/arm/boot/dts/sun5i.dtsi → arch/arm/boot/dts/sun5i-a13.dtsi
View File

4
arch/arm/mach-exynos/clock-exynos4.c
View File

@ -529,7 +529,7 @@ static struct clk exynos4_init_clocks_off[] = {
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 8),
}, {
.name = "dwmmc",
.name = "biu",
.parent = &exynos4_clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 9),
@ -1134,7 +1134,7 @@ static struct clksrc_clk exynos4_clksrcs[] = {
.reg_div = { .reg = EXYNOS4_CLKDIV_MFC, .shift = 0, .size = 4 },
}, {
.clk = {
.name = "sclk_dwmmc",
.name = "ciu",
.parent = &exynos4_clk_dout_mmc4.clk,
.enable = exynos4_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 16),

3
arch/arm/mach-exynos/common.c
View File

@ -679,7 +679,8 @@ void __init exynos5_init_irq(void)
* Theses parameters should be NULL and 0 because EXYNOS4
* uses GIC instead of VIC.
*/
s5p_init_irq(NULL, 0);
if (!of_machine_is_compatible("samsung,exynos5440"))
s5p_init_irq(NULL, 0);
gic_arch_extn.irq_set_wake = s3c_irq_wake;
}

12
arch/arm/mach-exynos/dev-audio.c
View File

@ -23,11 +23,6 @@
#include <mach/irqs.h>
#include <mach/regs-audss.h>
static const char *rclksrc[] = {
[0] = "busclk",
[1] = "i2sclk",
};
static int exynos4_cfg_i2s(struct platform_device *pdev)
{
/* configure GPIO for i2s port */
@ -55,7 +50,6 @@ static struct s3c_audio_pdata i2sv5_pdata = {
.i2s = {
.quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI
| QUIRK_NEED_RSTCLR,
.src_clk = rclksrc,
.idma_addr = EXYNOS4_AUDSS_INT_MEM,
},
},
@ -78,17 +72,11 @@ struct platform_device exynos4_device_i2s0 = {
},
};
static const char *rclksrc_v3[] = {
[0] = "sclk_i2s",
[1] = "no_such_clock",
};
static struct s3c_audio_pdata i2sv3_pdata = {
.cfg_gpio = exynos4_cfg_i2s,
.type = {
.i2s = {
.quirks = QUIRK_NO_MUXPSR,
.src_clk = rclksrc_v3,
},
},
};

2
arch/arm/mach-exynos/mach-exynos5-dt.c
View File

@ -163,6 +163,7 @@ static char const *exynos5_dt_compat[] __initdata = {
static void __init exynos5_reserve(void)
{
#ifdef CONFIG_S5P_DEV_MFC
struct s5p_mfc_dt_meminfo mfc_mem;
/* Reserve memory for MFC only if it's available */
@ -170,6 +171,7 @@ static void __init exynos5_reserve(void)
if (of_scan_flat_dt(s5p_fdt_find_mfc_mem, &mfc_mem))
s5p_mfc_reserve_mem(mfc_mem.roff, mfc_mem.rsize, mfc_mem.loff,
mfc_mem.lsize);
#endif
}
DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)")

4
arch/arm/mach-exynos/mach-origen.c
View File

@ -621,7 +621,7 @@ static struct pwm_lookup origen_pwm_lookup[] = {
PWM_LOOKUP("s3c24xx-pwm.0", 0, "pwm-backlight.0", NULL),
};
#ifdef CONFIG_DRM_EXYNOS
#ifdef CONFIG_DRM_EXYNOS_FIMD
static struct exynos_drm_fimd_pdata drm_fimd_pdata = {
.panel = {
.timing = {
@ -793,7 +793,7 @@ static void __init origen_machine_init(void)
s5p_i2c_hdmiphy_set_platdata(NULL);
s5p_hdmi_set_platdata(&hdmiphy_info, NULL, 0);
#ifdef CONFIG_DRM_EXYNOS
#ifdef CONFIG_DRM_EXYNOS_FIMD
s5p_device_fimd0.dev.platform_data = &drm_fimd_pdata;
exynos4_fimd0_gpio_setup_24bpp();
#else

4
arch/arm/mach-exynos/mach-smdk4x12.c
View File

@ -246,7 +246,7 @@ static struct samsung_keypad_platdata smdk4x12_keypad_data __initdata = {
.cols = 8,
};
#ifdef CONFIG_DRM_EXYNOS
#ifdef CONFIG_DRM_EXYNOS_FIMD
static struct exynos_drm_fimd_pdata drm_fimd_pdata = {
.panel = {
.timing = {
@ -360,7 +360,7 @@ static void __init smdk4x12_machine_init(void)
s3c_hsotg_set_platdata(&smdk4x12_hsotg_pdata);
#ifdef CONFIG_DRM_EXYNOS
#ifdef CONFIG_DRM_EXYNOS_FIMD
s5p_device_fimd0.dev.platform_data = &drm_fimd_pdata;
exynos4_fimd0_gpio_setup_24bpp();
#else

4
arch/arm/mach-exynos/mach-smdkv310.c
View File

@ -159,7 +159,7 @@ static struct platform_device smdkv310_lcd_lte480wv = {
.dev.platform_data = &smdkv310_lcd_lte480wv_data,
};
#ifdef CONFIG_DRM_EXYNOS
#ifdef CONFIG_DRM_EXYNOS_FIMD
static struct exynos_drm_fimd_pdata drm_fimd_pdata = {
.panel = {
.timing = {
@ -402,7 +402,7 @@ static void __init smdkv310_machine_init(void)
samsung_bl_set(&smdkv310_bl_gpio_info, &smdkv310_bl_data);
pwm_add_table(smdkv310_pwm_lookup, ARRAY_SIZE(smdkv310_pwm_lookup));
#ifdef CONFIG_DRM_EXYNOS
#ifdef CONFIG_DRM_EXYNOS_FIMD
s5p_device_fimd0.dev.platform_data = &drm_fimd_pdata;
exynos4_fimd0_gpio_setup_24bpp();
#else

2
arch/arm/mach-exynos/platsmp.c
View File

@ -198,7 +198,7 @@ static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)
{
int i;
if (!soc_is_exynos5250())
if (!(soc_is_exynos5250() || soc_is_exynos5440()))
scu_enable(scu_base_addr());
/*

2
arch/arm/mach-omap2/timer.c
View File

@ -175,7 +175,7 @@ static struct device_node * __init omap_get_timer_dt(struct of_device_id *match,
continue;
}
prom_add_property(np, &device_disabled);
of_add_property(np, &device_disabled);
return np;
}

126
arch/arm/mach-s3c64xx/clock.c
View File

@ -149,25 +149,6 @@ static struct clk init_clocks_off[] = {
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C6410_CLKCON_PCLK_I2C1,
}, {
.name = "iis",
.devname = "samsung-i2s.0",
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_IIS0,
}, {
.name = "iis",
.devname = "samsung-i2s.1",
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_IIS1,
}, {
#ifdef CONFIG_CPU_S3C6410
.name = "iis",
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C6410_CLKCON_PCLK_IIS2,
}, {
#endif
.name = "keypad",
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
@ -337,6 +318,32 @@ static struct clk clk_48m_spi1 = {
.ctrlbit = S3C_CLKCON_SCLK_SPI1_48,
};
static struct clk clk_i2s0 = {
.name = "iis",
.devname = "samsung-i2s.0",
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_IIS0,
};
static struct clk clk_i2s1 = {
.name = "iis",
.devname = "samsung-i2s.1",
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_IIS1,
};
#ifdef CONFIG_CPU_S3C6410
static struct clk clk_i2s2 = {
.name = "iis",
.devname = "samsung-i2s.2",
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C6410_CLKCON_PCLK_IIS2,
};
#endif
static struct clk init_clocks[] = {
{
.name = "lcd",
@ -660,6 +667,7 @@ static struct clksrc_sources clkset_audio1 = {
.nr_sources = ARRAY_SIZE(clkset_audio1_list),
};
#ifdef CONFIG_CPU_S3C6410
static struct clk *clkset_audio2_list[] = {
[0] = &clk_mout_epll.clk,
[1] = &clk_dout_mpll,
@ -672,6 +680,7 @@ static struct clksrc_sources clkset_audio2 = {
.sources = clkset_audio2_list,
.nr_sources = ARRAY_SIZE(clkset_audio2_list),
};
#endif
static struct clksrc_clk clksrcs[] = {
{
@ -683,36 +692,6 @@ static struct clksrc_clk clksrcs[] = {
.reg_src = { .reg = S3C_CLK_SRC, .shift = 5, .size = 2 },
.reg_div = { .reg = S3C_CLK_DIV1, .shift = 20, .size = 4 },
.sources = &clkset_uhost,
}, {
.clk = {
.name = "audio-bus",
.devname = "samsung-i2s.0",
.ctrlbit = S3C_CLKCON_SCLK_AUDIO0,
.enable = s3c64xx_sclk_ctrl,
},
.reg_src = { .reg = S3C_CLK_SRC, .shift = 7, .size = 3 },
.reg_div = { .reg = S3C_CLK_DIV2, .shift = 8, .size = 4 },
.sources = &clkset_audio0,
}, {
.clk = {
.name = "audio-bus",
.devname = "samsung-i2s.1",
.ctrlbit = S3C_CLKCON_SCLK_AUDIO1,
.enable = s3c64xx_sclk_ctrl,
},
.reg_src = { .reg = S3C_CLK_SRC, .shift = 10, .size = 3 },
.reg_div = { .reg = S3C_CLK_DIV2, .shift = 12, .size = 4 },
.sources = &clkset_audio1,
}, {
.clk = {
.name = "audio-bus",
.devname = "samsung-i2s.2",
.ctrlbit = S3C6410_CLKCON_SCLK_AUDIO2,
.enable = s3c64xx_sclk_ctrl,
},
.reg_src = { .reg = S3C6410_CLK_SRC2, .shift = 0, .size = 3 },
.reg_div = { .reg = S3C_CLK_DIV2, .shift = 24, .size = 4 },
.sources = &clkset_audio2,
}, {
.clk = {
.name = "irda-bus",
@ -805,6 +784,43 @@ static struct clksrc_clk clk_sclk_spi1 = {
.sources = &clkset_spi_mmc,
};
static struct clksrc_clk clk_audio_bus0 = {
.clk = {
.name = "audio-bus",
.devname = "samsung-i2s.0",
.ctrlbit = S3C_CLKCON_SCLK_AUDIO0,
.enable = s3c64xx_sclk_ctrl,
},
.reg_src = { .reg = S3C_CLK_SRC, .shift = 7, .size = 3 },
.reg_div = { .reg = S3C_CLK_DIV2, .shift = 8, .size = 4 },
.sources = &clkset_audio0,
};
static struct clksrc_clk clk_audio_bus1 = {
.clk = {
.name = "audio-bus",
.devname = "samsung-i2s.1",
.ctrlbit = S3C_CLKCON_SCLK_AUDIO1,
.enable = s3c64xx_sclk_ctrl,
},
.reg_src = { .reg = S3C_CLK_SRC, .shift = 10, .size = 3 },
.reg_div = { .reg = S3C_CLK_DIV2, .shift = 12, .size = 4 },
.sources = &clkset_audio1,
};
#ifdef CONFIG_CPU_S3C6410
static struct clksrc_clk clk_audio_bus2 = {
.clk = {
.name = "audio-bus",
.devname = "samsung-i2s.2",
.ctrlbit = S3C6410_CLKCON_SCLK_AUDIO2,
.enable = s3c64xx_sclk_ctrl,
},
.reg_src = { .reg = S3C6410_CLK_SRC2, .shift = 0, .size = 3 },
.reg_div = { .reg = S3C_CLK_DIV2, .shift = 24, .size = 4 },
.sources = &clkset_audio2,
};
#endif
/* Clock initialisation code */
static struct clksrc_clk *init_parents[] = {
@ -820,6 +836,8 @@ static struct clksrc_clk *clksrc_cdev[] = {
&clk_sclk_mmc2,
&clk_sclk_spi0,
&clk_sclk_spi1,
&clk_audio_bus0,
&clk_audio_bus1,
};
static struct clk *clk_cdev[] = {
@ -828,6 +846,8 @@ static struct clk *clk_cdev[] = {
&clk_hsmmc2,
&clk_48m_spi0,
&clk_48m_spi1,
&clk_i2s0,
&clk_i2s1,
};
static struct clk_lookup s3c64xx_clk_lookup[] = {
@ -844,6 +864,14 @@ static struct clk_lookup s3c64xx_clk_lookup[] = {
CLKDEV_INIT("s3c6410-spi.0", "spi_busclk2", &clk_48m_spi0),
CLKDEV_INIT("s3c6410-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
CLKDEV_INIT("s3c6410-spi.1", "spi_busclk2", &clk_48m_spi1),
CLKDEV_INIT("samsung-i2s.0", "i2s_opclk0", &clk_i2s0),
CLKDEV_INIT("samsung-i2s.0", "i2s_opclk1", &clk_audio_bus0.clk),
CLKDEV_INIT("samsung-i2s.1", "i2s_opclk0", &clk_i2s1),
CLKDEV_INIT("samsung-i2s.1", "i2s_opclk1", &clk_audio_bus1.clk),
#ifdef CONFIG_CPU_S3C6410
CLKDEV_INIT("samsung-i2s.2", "i2s_opclk0", &clk_i2s2),
CLKDEV_INIT("samsung-i2s.2", "i2s_opclk1", &clk_audio_bus2.clk),
#endif
};
#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)

11
arch/arm/mach-s3c64xx/dev-audio.c
View File

@ -23,11 +23,6 @@
#include <linux/platform_data/asoc-s3c.h>
#include <plat/gpio-cfg.h>
static const char *rclksrc[] = {
[0] = "iis",
[1] = "audio-bus",
};
static int s3c64xx_i2s_cfg_gpio(struct platform_device *pdev)
{
unsigned int base;
@ -64,11 +59,6 @@ static struct resource s3c64xx_iis0_resource[] = {
static struct s3c_audio_pdata i2sv3_pdata = {
.cfg_gpio = s3c64xx_i2s_cfg_gpio,
.type = {
.i2s = {
.src_clk = rclksrc,
},
},
};
struct platform_device s3c64xx_device_iis0 = {
@ -110,7 +100,6 @@ static struct s3c_audio_pdata i2sv4_pdata = {
.type = {
.i2s = {
.quirks = QUIRK_PRI_6CHAN,
.src_clk = rclksrc,
},
},
};

49
arch/arm/mach-s5p64x0/clock-s5p6440.c
View File

@ -242,12 +242,6 @@ static struct clk init_clocks_off[] = {
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 25),
}, {
.name = "iis",
.devname = "samsung-i2s.0",
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 26),
}, {
.name = "dsim",
.parent = &clk_pclk_low.clk,
@ -405,15 +399,6 @@ static struct clksrc_clk clksrcs[] = {
.sources = &clkset_group1,
.reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 8, .size = 2 },
.reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 4, .size = 4 },
}, {
.clk = {
.name = "sclk_audio2",
.ctrlbit = (1 << 11),
.enable = s5p64x0_sclk_ctrl,
},
.sources = &clkset_audio,
.reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 0, .size = 3 },
.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 24, .size = 4 },
},
};
@ -464,6 +449,26 @@ static struct clksrc_clk clk_sclk_uclk = {
.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
};
static struct clk clk_i2s0 = {
.name = "iis",
.devname = "samsung-i2s.0",
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 26),
};
static struct clksrc_clk clk_audio_bus2 = {
.clk = {
.name = "sclk_audio2",
.devname = "samsung-i2s.0",
.ctrlbit = (1 << 11),
.enable = s5p64x0_sclk_ctrl,
},
.sources = &clkset_audio,
.reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 0, .size = 3 },
.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 24, .size = 4 },
};
static struct clksrc_clk clk_sclk_spi0 = {
.clk = {
.name = "sclk_spi",
@ -506,13 +511,18 @@ static struct clk dummy_apb_pclk = {
.id = -1,
};
static struct clk *clk_cdev[] = {
&clk_i2s0,
};
static struct clksrc_clk *clksrc_cdev[] = {
&clk_sclk_uclk,
&clk_sclk_spi0,
&clk_sclk_spi1,
&clk_sclk_mmc0,
&clk_sclk_mmc1,
&clk_sclk_mmc2
&clk_sclk_mmc2,
&clk_audio_bus2,
};
static struct clk_lookup s5p6440_clk_lookup[] = {
@ -524,6 +534,8 @@ static struct clk_lookup s5p6440_clk_lookup[] = {
CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
CLKDEV_INIT("samsung-i2s.0", "i2s_opclk0", &clk_i2s0),
CLKDEV_INIT("samsung-i2s.0", "i2s_opclk1", &clk_audio_bus2.clk),
};
void __init_or_cpufreq s5p6440_setup_clocks(void)
@ -596,12 +608,17 @@ static struct clk *clks[] __initdata = {
void __init s5p6440_register_clocks(void)
{
int ptr;
unsigned int cnt;
s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
s3c_register_clksrc(sysclks[ptr], 1);
s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
for (cnt = 0; cnt < ARRAY_SIZE(clk_cdev); cnt++)
s3c_disable_clocks(clk_cdev[cnt], 1);
s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)

61
arch/arm/mach-s5p64x0/clock-s5p6450.c
View File

@ -246,24 +246,6 @@ static struct clk init_clocks_off[] = {
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 22),
}, {
.name = "iis",
.devname = "samsung-i2s.0",
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 26),
}, {
.name = "iis",
.devname = "samsung-i2s.1",
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 15),
}, {
.name = "iis",
.devname = "samsung-i2s.2",
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 16),
}, {
.name = "i2c",
.devname = "s3c2440-i2c.1",
@ -402,6 +384,7 @@ static struct clksrc_sources clkset_sclk_audio0 = {
static struct clksrc_clk clk_sclk_audio0 = {
.clk = {
.name = "audio-bus",
.devname = "samsung-i2s.0",
.enable = s5p64x0_sclk_ctrl,
.ctrlbit = (1 << 8),
.parent = &clk_dout_epll.clk,
@ -549,6 +532,36 @@ static struct clksrc_clk clk_sclk_spi1 = {
.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
};
static struct clk clk_i2s0 = {
.name = "iis",
.devname = "samsung-i2s.0",
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 26),
};
static struct clk clk_i2s1 = {
.name = "iis",
.devname = "samsung-i2s.1",
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 15),
};
static struct clk clk_i2s2 = {
.name = "iis",
.devname = "samsung-i2s.2",
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 16),
};
static struct clk *clk_cdev[] = {
&clk_i2s0,
&clk_i2s1,
&clk_i2s2,
};
static struct clksrc_clk *clksrc_cdev[] = {
&clk_sclk_uclk,
&clk_sclk_spi0,
@ -556,6 +569,7 @@ static struct clksrc_clk *clksrc_cdev[] = {
&clk_sclk_mmc0,
&clk_sclk_mmc1,
&clk_sclk_mmc2,
&clk_sclk_audio0,
};
static struct clk_lookup s5p6450_clk_lookup[] = {
@ -567,6 +581,10 @@ static struct clk_lookup s5p6450_clk_lookup[] = {
CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
CLKDEV_INIT("samsung-i2s.0", "i2s_opclk0", &clk_i2s0),
CLKDEV_INIT("samsung-i2s.0", "i2s_opclk1", &clk_sclk_audio0.clk),
CLKDEV_INIT("samsung-i2s.1", "i2s_opclk0", &clk_i2s1),
CLKDEV_INIT("samsung-i2s.2", "i2s_opclk0", &clk_i2s2),
};
/* Clock initialization code */
@ -584,7 +602,6 @@ static struct clksrc_clk *sysclks[] = {
&clk_pclk,
&clk_hclk_low,
&clk_pclk_low,
&clk_sclk_audio0,
};
static struct clk dummy_apb_pclk = {
@ -661,10 +678,16 @@ void __init_or_cpufreq s5p6450_setup_clocks(void)
void __init s5p6450_register_clocks(void)
{
int ptr;
unsigned int cnt;
for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
s3c_register_clksrc(sysclks[ptr], 1);
s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
for (cnt = 0; cnt < ARRAY_SIZE(clk_cdev); cnt++)
s3c_disable_clocks(clk_cdev[cnt], 1);
s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)

12
arch/arm/mach-s5p64x0/dev-audio.c
View File

@ -19,11 +19,6 @@
#include <mach/dma.h>
#include <mach/irqs.h>
static const char *rclksrc[] = {
[0] = "iis",
[1] = "sclk_audio2",
};
static int s5p6440_cfg_i2s(struct platform_device *pdev)
{
switch (pdev->id) {
@ -45,7 +40,6 @@ static struct s3c_audio_pdata s5p6440_i2s_pdata = {
.type = {
.i2s = {
.quirks = QUIRK_PRI_6CHAN,
.src_clk = rclksrc,
},
},
};
@ -93,7 +87,6 @@ static struct s3c_audio_pdata s5p6450_i2s0_pdata = {
.type = {
.i2s = {
.quirks = QUIRK_PRI_6CHAN,
.src_clk = rclksrc,
},
},
};
@ -110,11 +103,6 @@ struct platform_device s5p6450_device_iis0 = {
static struct s3c_audio_pdata s5p6450_i2s_pdata = {
.cfg_gpio = s5p6450_cfg_i2s,
.type = {
.i2s = {
.src_clk = rclksrc,
},
},
};
static struct resource s5p6450_i2s1_resource[] = {

48
arch/arm/mach-s5pc100/clock.c
View File

@ -605,24 +605,6 @@ static struct clk init_clocks_off[] = {
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_4_ctrl,
.ctrlbit = (1 << 13),
}, {
.name = "iis",
.devname = "samsung-i2s.0",
.parent = &clk_div_pclkd1.clk,
.enable = s5pc100_d1_5_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "iis",
.devname = "samsung-i2s.1",
.parent = &clk_div_pclkd1.clk,
.enable = s5pc100_d1_5_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "iis",
.devname = "samsung-i2s.2",
.parent = &clk_div_pclkd1.clk,
.enable = s5pc100_d1_5_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "ac97",
.parent = &clk_div_pclkd1.clk,
@ -724,6 +706,30 @@ static struct clk clk_48m_spi2 = {
.ctrlbit = (1 << 9),
};
static struct clk clk_i2s0 = {
.name = "iis",
.devname = "samsung-i2s.0",
.parent = &clk_div_pclkd1.clk,
.enable = s5pc100_d1_5_ctrl,
.ctrlbit = (1 << 0),
};
static struct clk clk_i2s1 = {
.name = "iis",
.devname = "samsung-i2s.1",
.parent = &clk_div_pclkd1.clk,
.enable = s5pc100_d1_5_ctrl,
.ctrlbit = (1 << 1),
};
static struct clk clk_i2s2 = {
.name = "iis",
.devname = "samsung-i2s.2",
.parent = &clk_div_pclkd1.clk,
.enable = s5pc100_d1_5_ctrl,
.ctrlbit = (1 << 2),
};
static struct clk clk_vclk54m = {
.name = "vclk_54m",
.rate = 54000000,
@ -1154,6 +1160,9 @@ static struct clk *clk_cdev[] = {
&clk_48m_spi0,
&clk_48m_spi1,
&clk_48m_spi2,
&clk_i2s0,
&clk_i2s1,
&clk_i2s2,
};
static struct clksrc_clk *clksrc_cdev[] = {
@ -1321,6 +1330,9 @@ static struct clk_lookup s5pc100_clk_lookup[] = {
CLKDEV_INIT("s5pc100-spi.1", "spi_busclk2", &clk_sclk_spi1.clk),
CLKDEV_INIT("s5pc100-spi.2", "spi_busclk1", &clk_48m_spi2),
CLKDEV_INIT("s5pc100-spi.2", "spi_busclk2", &clk_sclk_spi2.clk),
CLKDEV_INIT("samsung-i2s.0", "i2s_opclk0", &clk_i2s0),
CLKDEV_INIT("samsung-i2s.1", "i2s_opclk0", &clk_i2s1),
CLKDEV_INIT("samsung-i2s.2", "i2s_opclk0", &clk_i2s2),
};
void __init s5pc100_register_clocks(void)

16
arch/arm/mach-s5pc100/dev-audio.c
View File

@ -39,18 +39,12 @@ static int s5pc100_cfg_i2s(struct platform_device *pdev)
return 0;
}
static const char *rclksrc_v5[] = {
[0] = "iis",
[1] = "i2sclkd2",
};
static struct s3c_audio_pdata i2sv5_pdata = {
.cfg_gpio = s5pc100_cfg_i2s,
.type = {
.i2s = {
.quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI
| QUIRK_NEED_RSTCLR,
.src_clk = rclksrc_v5,
},
},
};
@ -72,18 +66,8 @@ struct platform_device s5pc100_device_iis0 = {
},
};
static const char *rclksrc_v3[] = {
[0] = "iis",
[1] = "sclk_audio",
};
static struct s3c_audio_pdata i2sv3_pdata = {
.cfg_gpio = s5pc100_cfg_i2s,
.type = {
.i2s = {
.src_clk = rclksrc_v3,
},
},
};
static struct resource s5pc100_iis1_resource[] = {

16
arch/arm/mach-s5pv210/dev-audio.c
View File

@ -20,11 +20,6 @@
#include <mach/irqs.h>
#include <mach/regs-audss.h>
static const char *rclksrc[] = {
[0] = "busclk",
[1] = "i2sclk",
};
static int s5pv210_cfg_i2s(struct platform_device *pdev)
{
/* configure GPIO for i2s port */
@ -52,7 +47,6 @@ static struct s3c_audio_pdata i2sv5_pdata = {
.i2s = {
.quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI
| QUIRK_NEED_RSTCLR,
.src_clk = rclksrc,
.idma_addr = S5PV210_AUDSS_INT_MEM,
},
},
@ -75,18 +69,8 @@ struct platform_device s5pv210_device_iis0 = {
},
};
static const char *rclksrc_v3[] = {
[0] = "iis",
[1] = "audio-bus",
};
static struct s3c_audio_pdata i2sv3_pdata = {
.cfg_gpio = s5pv210_cfg_i2s,
.type = {
.i2s = {
.src_clk = rclksrc_v3,
},
},
};
static struct resource s5pv210_iis1_resource[] = {

5
arch/arm/plat-samsung/include/plat/gpio-core.h
View File

@ -11,6 +11,9 @@
* published by the Free Software Foundation.
*/
#ifndef __PLAT_SAMSUNG_GPIO_CORE_H
#define __PLAT_SAMSUNG_GPIO_CORE_H
#define GPIOCON_OFF (0x00)
#define GPIODAT_OFF (0x04)
@ -124,3 +127,5 @@ extern struct samsung_gpio_pm samsung_gpio_pm_4bit;
/* locking wrappers to deal with multiple access to the same gpio bank */
#define samsung_gpio_lock(_oc, _fl) spin_lock_irqsave(&(_oc)->lock, _fl)
#define samsung_gpio_unlock(_oc, _fl) spin_unlock_irqrestore(&(_oc)->lock, _fl)
#endif /* __PLAT_SAMSUNG_GPIO_CORE_H */

2
drivers/pinctrl/pinctrl-exynos5440.c
View File

@ -117,7 +117,7 @@ struct exynos5440_pinctrl_priv_data {
};
/* list of all possible config options supported */
struct pin_config {
static struct pin_config {
char *prop_cfg;
unsigned int cfg_type;
} pcfgs[] = {

2
drivers/pinctrl/pinctrl-samsung.c
View File

@ -37,7 +37,7 @@
#define FSUFFIX_LEN sizeof(FUNCTION_SUFFIX)
/* list of all possible config options supported */
struct pin_config {
static struct pin_config {
char *prop_cfg;
unsigned int cfg_type;
} pcfgs[] = {

2
drivers/pinctrl/pinctrl-samsung.h
View File

@ -104,7 +104,7 @@ struct samsung_pinctrl_drv_data;
/**
* struct samsung_pin_bank: represent a controller pin-bank.
* @reg_offset: starting offset of the pin-bank registers.
* @pctl_offset: starting offset of the pin-bank registers.
* @pin_base: starting pin number of the bank.
* @nr_pins: number of pins included in this bank.
* @func_width: width of the function selector bit field.