omap3: nand: ecc layout select from board file
This patch makes it possible to select sw or hw (different layout options) ecc scheme supported by omap nand driver. Signed-off-by: Vimal Singh <vimalsingh@ti.com> Signed-off-by: Sukumar Ghorai <s-ghorai@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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@ -148,6 +148,7 @@ __init board_nand_init(struct mtd_partition *nand_parts,
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board_nand_data.nr_parts = nr_parts;
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board_nand_data.nr_parts = nr_parts;
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board_nand_data.devsize = nand_type;
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board_nand_data.devsize = nand_type;
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board_nand_data.ecc_opt = OMAP_ECC_HAMMING_CODE_DEFAULT;
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board_nand_data.gpmc_irq = OMAP_GPMC_IRQ_BASE + cs;
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board_nand_data.gpmc_irq = OMAP_GPMC_IRQ_BASE + cs;
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gpmc_nand_init(&board_nand_data);
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gpmc_nand_init(&board_nand_data);
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}
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}
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@ -86,6 +86,12 @@
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#define PREFETCH_FIFOTHRESHOLD_MAX 0x40
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#define PREFETCH_FIFOTHRESHOLD_MAX 0x40
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#define PREFETCH_FIFOTHRESHOLD(val) ((val) << 8)
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#define PREFETCH_FIFOTHRESHOLD(val) ((val) << 8)
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enum omap_ecc {
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/* 1-bit ecc: stored at end of spare area */
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OMAP_ECC_HAMMING_CODE_DEFAULT = 0, /* Default, s/w method */
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OMAP_ECC_HAMMING_CODE_HW, /* gpmc to detect the error */
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};
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/*
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/*
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* Note that all values in this struct are in nanoseconds except sync_clk
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* Note that all values in this struct are in nanoseconds except sync_clk
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* (which is in picoseconds), while the register values are in gpmc_fck cycles.
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* (which is in picoseconds), while the register values are in gpmc_fck cycles.
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@ -8,6 +8,7 @@
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* published by the Free Software Foundation.
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* published by the Free Software Foundation.
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*/
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*/
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#include <plat/gpmc.h>
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#include <linux/mtd/partitions.h>
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#include <linux/mtd/partitions.h>
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enum nand_io {
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enum nand_io {
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@ -31,6 +32,7 @@ struct omap_nand_platform_data {
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enum nand_io xfer_type;
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enum nand_io xfer_type;
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unsigned long phys_base;
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unsigned long phys_base;
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int devsize;
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int devsize;
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enum omap_ecc ecc_opt;
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};
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};
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/* minimum size for IO mapping */
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/* minimum size for IO mapping */
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@ -626,8 +626,6 @@ static int omap_verify_buf(struct mtd_info *mtd, const u_char * buf, int len)
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return 0;
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return 0;
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}
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}
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#ifdef CONFIG_MTD_NAND_OMAP_HWECC
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/**
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/**
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* gen_true_ecc - This function will generate true ECC value
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* gen_true_ecc - This function will generate true ECC value
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* @ecc_buf: buffer to store ecc code
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* @ecc_buf: buffer to store ecc code
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@ -847,8 +845,6 @@ static void omap_enable_hwecc(struct mtd_info *mtd, int mode)
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gpmc_enable_hwecc(info->gpmc_cs, mode, dev_width, info->nand.ecc.size);
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gpmc_enable_hwecc(info->gpmc_cs, mode, dev_width, info->nand.ecc.size);
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}
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}
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#endif
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/**
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/**
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* omap_wait - wait until the command is done
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* omap_wait - wait until the command is done
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* @mtd: MTD device structure
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* @mtd: MTD device structure
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@ -1038,17 +1034,17 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
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info->nand.verify_buf = omap_verify_buf;
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info->nand.verify_buf = omap_verify_buf;
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#ifdef CONFIG_MTD_NAND_OMAP_HWECC
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/* selsect the ecc type */
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info->nand.ecc.bytes = 3;
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if (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_DEFAULT)
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info->nand.ecc.size = 512;
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info->nand.ecc.mode = NAND_ECC_SOFT;
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info->nand.ecc.calculate = omap_calculate_ecc;
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else if (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW) {
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info->nand.ecc.hwctl = omap_enable_hwecc;
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info->nand.ecc.bytes = 3;
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info->nand.ecc.correct = omap_correct_data;
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info->nand.ecc.size = 512;
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info->nand.ecc.mode = NAND_ECC_HW;
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info->nand.ecc.calculate = omap_calculate_ecc;
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info->nand.ecc.hwctl = omap_enable_hwecc;
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#else
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info->nand.ecc.correct = omap_correct_data;
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info->nand.ecc.mode = NAND_ECC_SOFT;
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info->nand.ecc.mode = NAND_ECC_HW;
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#endif
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}
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/* DIP switches on some boards change between 8 and 16 bit
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/* DIP switches on some boards change between 8 and 16 bit
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* bus widths for flash. Try the other width if the first try fails.
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* bus widths for flash. Try the other width if the first try fails.
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