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ARM: dts: exynos: Fix initial audio clocks configuration on Exynos4 boards 

Move assigned clocks properties from sound node to audio subsystem clock
controller node. This way clocks topology and rates are set just after
probing audio clocks controller. Leaving those properties under
sound node doesn't guarantee to configure them before they are being used
(for example i2s hardware module can be probed in parallel and it also
require proper audio clocks configuration).

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
This commit is contained in:
Marek Szyprowski 2016-12-09 08:22:11 +01:00 committed by Krzysztof Kozlowski
parent 087ce39cdf
commit f3a3a3bf71
2 changed files with 20 additions and 21 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
arch/arm/boot/dts/exynos4412-itop-elite.dts
View File

@ -82,17 +82,6 @@
compatible = "simple-audio-card";
simple-audio-card,name = "wm-sound";
assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>,
<&clock_audss EXYNOS_MOUT_I2S>,
<&clock_audss EXYNOS_DOUT_SRP>,
<&clock_audss EXYNOS_DOUT_AUD_BUS>;
assigned-clock-parents = <&clock CLK_FOUT_EPLL>,
<&clock_audss EXYNOS_MOUT_AUDSS>;
assigned-clock-rates = <0>,
<0>,
<112896000>,
<11289600>;
simple-audio-card,format = "i2s";
simple-audio-card,bitclock-master = <&link0_codec>;
simple-audio-card,frame-master = <&link0_codec>;
@ -145,6 +134,16 @@
status = "okay";
};
&clock_audss {
assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>,
<&clock_audss EXYNOS_MOUT_I2S>,
<&clock_audss EXYNOS_DOUT_SRP>,
<&clock_audss EXYNOS_DOUT_AUD_BUS>;
assigned-clock-parents = <&clock CLK_FOUT_EPLL>,
<&clock_audss EXYNOS_MOUT_AUDSS>;
assigned-clock-rates = <0>, <0>, <112896000>, <11289600>;
};
&ehci {
status = "okay";
/* In order to reset USB ethernet */

20
arch/arm/boot/dts/exynos4412-odroid-common.dtsi
View File

@ -43,16 +43,6 @@
sound: sound {
compatible = "simple-audio-card";
assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>,
<&clock_audss EXYNOS_MOUT_I2S>,
<&clock_audss EXYNOS_DOUT_SRP>,
<&clock_audss EXYNOS_DOUT_AUD_BUS>;
assigned-clock-parents = <&clock CLK_FOUT_EPLL>,
<&clock_audss EXYNOS_MOUT_AUDSS>;
assigned-clock-rates = <0>,
<0>,
<192000000>,
<19200000>;
simple-audio-card,format = "i2s";
simple-audio-card,bitclock-master = <&link0_codec>;
@ -157,6 +147,16 @@
status = "okay";
};
&clock_audss {
assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>,
<&clock_audss EXYNOS_MOUT_I2S>,
<&clock_audss EXYNOS_DOUT_SRP>,
<&clock_audss EXYNOS_DOUT_AUD_BUS>;
assigned-clock-parents = <&clock CLK_FOUT_EPLL>,
<&clock_audss EXYNOS_MOUT_AUDSS>;
assigned-clock-rates = <0>, <0>, <192000000>, <19200000>;
};
&cpu0 {
cpu0-supply = <&buck2_reg>;
};