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[POWERPC] fsl_spi: stop using device_type = "spi" 

Also:
- rename "fsl_spi" to "fsl,spi";
- add and use cell-index property, if found;
- split probing code out of fsl_spi_init, thus we can call
  it for legacy device_type probing and new "compatible" probing.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Anton Vorontsov 2008-01-24 18:40:07 +03:00 committed by Kumar Gala
parent 59a0ea5091
commit f3a2b29d93
14 changed files with 96 additions and 70 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
Documentation/powerpc/booting-without-of.txt
View File

@ -1568,8 +1568,8 @@ platforms are moved over to use the flattened-device-tree model.
ii) SPI (Serial Peripheral Interface)
Required properties:
- device_type : should be "spi".
- compatible : should be "fsl_spi".
- cell-index : SPI controller index.
- compatible : should be "fsl,spi".
- mode : the SPI operation mode, it can be "cpu" or "cpu-qe".
- reg : Offset and length of the register set for the device
- interrupts : <a b> where a is the interrupt number and b is a
@ -1582,8 +1582,8 @@ platforms are moved over to use the flattened-device-tree model.
Example:
spi@4c0 {
device_type = "spi";
compatible = "fsl_spi";
cell-index = <0>;
compatible = "fsl,spi";
reg = <4c0 40>;
interrupts = <82 0>;
interrupt-parent = <700>;

4
arch/powerpc/boot/dts/mpc8313erdb.dts
View File

@ -130,8 +130,8 @@
};
spi@7000 {
device_type = "spi";
compatible = "fsl_spi";
cell-index = <0>;
compatible = "fsl,spi";
reg = <7000 1000>;
interrupts = <10 8>;
interrupt-parent = < &ipic >;

8
arch/powerpc/boot/dts/mpc832x_mds.dts
View File

@ -223,8 +223,8 @@
};
spi@4c0 {
device_type = "spi";
compatible = "fsl_spi";
cell-index = <0>;
compatible = "fsl,spi";
reg = <4c0 40>;
interrupts = <2>;
interrupt-parent = < &qeic >;
@ -232,8 +232,8 @@
};
spi@500 {
device_type = "spi";
compatible = "fsl_spi";
cell-index = <1>;
compatible = "fsl,spi";
reg = <500 40>;
interrupts = <1>;
interrupt-parent = < &qeic >;

8
arch/powerpc/boot/dts/mpc832x_rdb.dts
View File

@ -184,8 +184,8 @@
};
spi@4c0 {
device_type = "spi";
compatible = "fsl_spi";
cell-index = <0>;
compatible = "fsl,spi";
reg = <4c0 40>;
interrupts = <2>;
interrupt-parent = <&qeic>;
@ -193,8 +193,8 @@
};
spi@500 {
device_type = "spi";
compatible = "fsl_spi";
cell-index = <1>;
compatible = "fsl,spi";
reg = <500 40>;
interrupts = <1>;
interrupt-parent = <&qeic>;

4
arch/powerpc/boot/dts/mpc8349emitx.dts
View File

@ -82,8 +82,8 @@
};
spi@7000 {
device_type = "spi";
compatible = "fsl_spi";
cell-index = <0>;
compatible = "fsl,spi";
reg = <7000 1000>;
interrupts = <10 8>;
interrupt-parent = < &ipic >;

4
arch/powerpc/boot/dts/mpc8349emitxgp.dts
View File

@ -80,8 +80,8 @@
};
spi@7000 {
device_type = "spi";
compatible = "fsl_spi";
cell-index = <0>;
compatible = "fsl,spi";
reg = <7000 1000>;
interrupts = <10 8>;
interrupt-parent = < &ipic >;

4
arch/powerpc/boot/dts/mpc834x_mds.dts
View File

@ -95,8 +95,8 @@
};
spi@7000 {
device_type = "spi";
compatible = "fsl_spi";
cell-index = <0>;
compatible = "fsl,spi";
reg = <0x7000 0x1000>;
interrupts = <16 8>;
interrupt-parent = <&ipic>;

8
arch/powerpc/boot/dts/mpc836x_mds.dts
View File

@ -225,8 +225,8 @@
};
spi@4c0 {
device_type = "spi";
compatible = "fsl_spi";
cell-index = <0>;
compatible = "fsl,spi";
reg = <4c0 40>;
interrupts = <2>;
interrupt-parent = < &qeic >;
@ -234,8 +234,8 @@
};
spi@500 {
device_type = "spi";
compatible = "fsl_spi";
cell-index = <1>;
compatible = "fsl,spi";
reg = <500 40>;
interrupts = <1>;
interrupt-parent = < &qeic >;

3
arch/powerpc/boot/dts/mpc8377_mds.dts
View File

@ -83,7 +83,8 @@
};
spi@7000 {
compatible = "fsl_spi";
cell-index = <0>;
compatible = "fsl,spi";
reg = <0x7000 0x1000>;
interrupts = <0x10 0x8>;
interrupt-parent = < &ipic >;

3
arch/powerpc/boot/dts/mpc8378_mds.dts
View File

@ -83,7 +83,8 @@
};
spi@7000 {
compatible = "fsl_spi";
cell-index = <0>;
compatible = "fsl,spi";
reg = <0x7000 0x1000>;
interrupts = <0x10 0x8>;
interrupt-parent = < &ipic >;

3
arch/powerpc/boot/dts/mpc8379_mds.dts
View File

@ -83,7 +83,8 @@
};
spi@7000 {
compatible = "fsl_spi";
cell-index = <0>;
compatible = "fsl,spi";
reg = <0x7000 0x1000>;
interrupts = <0x10 0x8>;
interrupt-parent = < &ipic >;

8
arch/powerpc/boot/dts/mpc8568mds.dts
View File

@ -302,8 +302,8 @@
};
spi@4c0 {
device_type = "spi";
compatible = "fsl_spi";
cell-index = <0>;
compatible = "fsl,spi";
reg = <4c0 40>;
interrupts = <2>;
interrupt-parent = <&qeic>;
@ -311,8 +311,8 @@
};
spi@500 {
device_type = "spi";
compatible = "fsl_spi";
cell-index = <1>;
compatible = "fsl,spi";
reg = <500 40>;
interrupts = <1>;
interrupt-parent = <&qeic>;

3
arch/powerpc/boot/dts/sbc8349.dts
View File

@ -87,7 +87,8 @@
};
spi@7000 {
compatible = "fsl_spi";
cell-index = <0>;
compatible = "fsl,spi";
reg = <0x7000 0x1000>;
interrupts = <0x10 0x8>;
interrupt-parent = <&ipic>;

98
arch/powerpc/sysdev/fsl_soc.c
View File

@ -1276,44 +1276,17 @@ arch_initcall(cpm_smc_uart_of_init);
#endif /* CONFIG_8xx */
#endif /* CONFIG_PPC_CPM_NEW_BINDING */
int __init fsl_spi_init(struct spi_board_info *board_infos,
unsigned int num_board_infos,
void (*activate_cs)(u8 cs, u8 polarity),
void (*deactivate_cs)(u8 cs, u8 polarity))
static int __init of_fsl_spi_probe(char *type, char *compatible, u32 sysclk,
struct spi_board_info *board_infos,
unsigned int num_board_infos,
void (*activate_cs)(u8 cs, u8 polarity),
void (*deactivate_cs)(u8 cs, u8 polarity))
{
struct device_node *np;
unsigned int i;
u32 sysclk = -1;
unsigned int i = 0;
/* SPI controller is either clocked from QE or SoC clock */
#ifdef CONFIG_QUICC_ENGINE
sysclk = get_brgfreq();
#endif
if (sysclk == -1) {
const u32 *freq;
int size;
np = of_find_node_by_type(NULL, "soc");
if (!np)
return -ENODEV;
freq = of_get_property(np, "clock-frequency", &size);
if (!freq || size != sizeof(*freq) || *freq == 0) {
freq = of_get_property(np, "bus-frequency", &size);
if (!freq || size != sizeof(*freq) || *freq == 0) {
of_node_put(np);
return -ENODEV;
}
}
sysclk = *freq;
of_node_put(np);
}
for (np = NULL, i = 1;
(np = of_find_compatible_node(np, "spi", "fsl_spi")) != NULL;
i++) {
int ret = 0;
for_each_compatible_node(np, type, compatible) {
int ret;
unsigned int j;
const void *prop;
struct resource res[2];
@ -1332,6 +1305,10 @@ int __init fsl_spi_init(struct spi_board_info *board_infos,
goto err;
pdata.bus_num = *(u32 *)prop;
prop = of_get_property(np, "cell-index", NULL);
if (prop)
i = *(u32 *)prop;
prop = of_get_property(np, "mode", NULL);
if (prop && !strcmp(prop, "cpu-qe"))
pdata.qe_mode = 1;
@ -1342,7 +1319,7 @@ int __init fsl_spi_init(struct spi_board_info *board_infos,
}
if (!pdata.max_chipselect)
goto err;
continue;
ret = of_address_to_resource(np, 0, &res[0]);
if (ret)
@ -1369,13 +1346,58 @@ int __init fsl_spi_init(struct spi_board_info *board_infos,
if (ret)
goto unreg;
continue;
goto next;
unreg:
platform_device_del(pdev);
err:
continue;
pr_err("%s: registration failed\n", np->full_name);
next:
i++;
}
return i;
}
int __init fsl_spi_init(struct spi_board_info *board_infos,
unsigned int num_board_infos,
void (*activate_cs)(u8 cs, u8 polarity),
void (*deactivate_cs)(u8 cs, u8 polarity))
{
u32 sysclk = -1;
int ret;
#ifdef CONFIG_QUICC_ENGINE
/* SPI controller is either clocked from QE or SoC clock */
sysclk = get_brgfreq();
#endif
if (sysclk == -1) {
struct device_node *np;
const u32 *freq;
int size;
np = of_find_node_by_type(NULL, "soc");
if (!np)
return -ENODEV;
freq = of_get_property(np, "clock-frequency", &size);
if (!freq || size != sizeof(*freq) || *freq == 0) {
freq = of_get_property(np, "bus-frequency", &size);
if (!freq || size != sizeof(*freq) || *freq == 0) {
of_node_put(np);
return -ENODEV;
}
}
sysclk = *freq;
of_node_put(np);
}
ret = of_fsl_spi_probe(NULL, "fsl,spi", sysclk, board_infos,
num_board_infos, activate_cs, deactivate_cs);
if (!ret)
of_fsl_spi_probe("spi", "fsl_spi", sysclk, board_infos,
num_board_infos, activate_cs, deactivate_cs);
return spi_register_board_info(board_infos, num_board_infos);
}