ARM: dts: socfpga: fix NAND support

- NAND should be using nand_x_clk, not nand_clk
 - fix NAND node compatible for Cyclone5 and Arria10
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJa+aqYAAoJEBmUBAuBoyj0RE0P/AphVDtncr7GsBtTfamrbfRZ
 ldL+zQn4RKvnbTQ+uwwNBPxlMs6MfmXkZkh53SDf67JIzHH1f1AZ3f+4DSgdeE+h
 PLDVJ4MME74CQFioB9jp+E6SHMO0VNYFXmToKUjF1yiKqDC0yRUQXpZy/T82vOC5
 XVbpNhhcN1GJpswOzh5QKigikWJmYI2rQRujvx0kq5Uxk4FYrqrRqbG5ftQ1jadS
 2mdukeNxSmBV+lAP+aXvHyY723evVAwMsDYAu+x4rI5/5jKkneAPKG7ZrfoQzGIM
 aVOVtg+6HAqs18feFNWNG/wlMx8DLzxUF184lkHfzbAfiuu9BWTzddY+Dxpir4eq
 mXF23hnF5A21bmDOsLLxFZSzbbtHCgStkPUc3GWDD8nxiNoujy1H4i60AoToUet0
 ULYI8jqP1KDW7IOIs3c5JT7kgIvX6MWM9dQEszbW2bsk2GIkvdMsjW/AhloIRg+f
 fHwrjgFCnalpMoIjV6viixC3kF57E1jT2iIZC817yKkifQGtQbzbw49nbxp+gBqZ
 la/o1pYGMGvnclwUMbCETQK97zYy8gt+uZ1+j8gOtafC3WQ9xDInNWu1L8OS7djX
 K7UpQzDOgambXPtpQWqY9XVCQ7ZM89GaLWGDU3V6yjJb3R1SYyGqL028v4dJKwnZ
 9h6lJ028jii5OKtEUfUN
 =SyHc
 -----END PGP SIGNATURE-----

Merge tag 'socfpga_nand_fix_v4.17' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into fixes

ARM: dts: socfpga: fix NAND support
- NAND should be using nand_x_clk, not nand_clk
- fix NAND node compatible for Cyclone5 and Arria10

* tag 'socfpga_nand_fix_v4.17' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
  ARM: dts: socfpga: Fix NAND controller node compatible for Arria10
  ARM: dts: socfpga: Fix NAND controller node compatible
  ARM: dts: socfpga: Fix NAND controller clock supply

Signed-off-by: Olof Johansson <olof@lixom.net>

arch/arm/boot/dts/socfpga.dtsi

@@ -748,13 +748,13 @@
 		nand0: nand@ff900000 {
 			#address-cells = <0x1>;
 			#size-cells = <0x1>;
-			compatible = "denali,denali-nand-dt";
+			compatible = "altr,socfpga-denali-nand";
 			reg = <0xff900000 0x100000>,
 			      <0xffb80000 0x10000>;
 			reg-names = "nand_data", "denali_reg";
 			interrupts = <0x0 0x90 0x4>;
 			dma-mask = <0xffffffff>;
-			clocks = <&nand_clk>;
+			clocks = <&nand_x_clk>;
 			status = "disabled";
 		};
 

arch/arm/boot/dts/socfpga_arria10.dtsi

@@ -633,7 +633,7 @@
 		nand: nand@ffb90000 {
 			#address-cells = <1>;
 			#size-cells = <1>;
-			compatible = "denali,denali-nand-dt", "altr,socfpga-denali-nand";
+			compatible = "altr,socfpga-denali-nand";
 			reg = <0xffb90000 0x72000>,
 			      <0xffb80000 0x10000>;
 			reg-names = "nand_data", "denali_reg";