dt-bindings: qoriq-clock: add more PLL divider clocks support

More PLL divider clocks are needed by clock consumer IP. So update
the PLL divider description to make it more general.

Signed-off-by: Yuantian Tang <andy.tang@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

Documentation/devicetree/bindings/clock/qoriq-clock.txt

@@ -83,8 +83,8 @@ second cell is the clock index for the specified type.
 	1	cmux		index (n in CLKCnCSR)
 	2	hwaccel		index (n in CLKCGnHWACSR)
 	3	fman		0 for fm1, 1 for fm2
-	4	platform pll	0=pll, 1=pll/2, 2=pll/3, 3=pll/4
+	4	platform pll	n=pll/(n+1). For example, when n=1,
-				4=pll/5, 5=pll/6, 6=pll/7, 7=pll/8
+				that means output_freq=PLL_freq/2.
 	5	coreclk		must be 0
 
 3. Example