hollalinux
/
linux-sg2042
mirror of https://github.com/sophgo/linux-riscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

sh: clkfwk: Build fix for non-legacy CPG changes. 

The disabling of the init op for non-legacy clocks neglected to do the
same in the core clock framework, resulting in a build failure. Fix it
up.

Reported-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Paul Mundt 2010-11-19 16:40:35 +09:00
parent 549015c36b
commit f278ea849e
2 changed files with 4 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/sh/clk/core.c
View File

@ -418,8 +418,11 @@ int clk_register(struct clk *clk)
list_add(&clk->sibling, &root_clks); list_add(&clk->sibling, &root_clks);
list_add(&clk->node, &clock_list); list_add(&clk->node, &clock_list);
#ifdef CONFIG_SH_CLK_CPG_LEGACY
if (clk->ops && clk->ops->init) if (clk->ops && clk->ops->init)
clk->ops->init(clk); clk->ops->init(clk);
#endif
out_unlock: out_unlock:
mutex_unlock(&clock_list_sem); mutex_unlock(&clock_list_sem);

2
drivers/sh/clk/cpg.c
View File

@ -131,7 +131,7 @@ static int sh_clk_div6_enable(struct clk *clk)
unsigned long value; unsigned long value;
int ret; int ret;
ret = sh_clk_div6_set_rate(clk, clk->rate, 0); ret = sh_clk_div6_set_rate(clk, clk->rate);
if (ret == 0) { if (ret == 0) {
value = __raw_readl(clk->enable_reg); value = __raw_readl(clk->enable_reg);
value &= ~0x100; /* clear stop bit to enable clock */ value &= ~0x100; /* clear stop bit to enable clock */