drm/amdgpu: move subfunctions to the front of vce_v2_0.c.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Rex Zhu
Alex Deucher
parent
ca6d35031f
commit
f1ea278d6f
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@ -42,14 +42,8 @@
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#define VCE_V2_0_DATA_SIZE (23552 * AMDGPU_MAX_VCE_HANDLES)
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#define VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK 0x02
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static void vce_v2_0_mc_resume(struct amdgpu_device *adev);
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static void vce_v2_0_set_ring_funcs(struct amdgpu_device *adev);
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static void vce_v2_0_set_irq_funcs(struct amdgpu_device *adev);
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static int vce_v2_0_wait_for_idle(void *handle);
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static void vce_v2_0_init_cg(struct amdgpu_device *adev);
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static void vce_v2_0_disable_cg(struct amdgpu_device *adev);
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static void vce_v2_0_enable_mgcg(struct amdgpu_device *adev, bool enable,
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bool sw_cg);
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/**
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* vce_v2_0_ring_get_rptr - get read pointer
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@ -145,6 +139,86 @@ static int vce_v2_0_firmware_loaded(struct amdgpu_device *adev)
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return -ETIMEDOUT;
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}
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static void vce_v2_0_disable_cg(struct amdgpu_device *adev)
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{
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WREG32(mmVCE_CGTT_CLK_OVERRIDE, 7);
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}
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static void vce_v2_0_init_cg(struct amdgpu_device *adev)
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{
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u32 tmp;
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tmp = RREG32(mmVCE_CLOCK_GATING_A);
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tmp &= ~0xfff;
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tmp |= ((0 << 0) | (4 << 4));
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tmp |= 0x40000;
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WREG32(mmVCE_CLOCK_GATING_A, tmp);
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tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
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tmp &= ~0xfff;
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tmp |= ((0 << 0) | (4 << 4));
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WREG32(mmVCE_UENC_CLOCK_GATING, tmp);
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tmp = RREG32(mmVCE_CLOCK_GATING_B);
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tmp |= 0x10;
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tmp &= ~0x100000;
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WREG32(mmVCE_CLOCK_GATING_B, tmp);
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}
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static void vce_v2_0_mc_resume(struct amdgpu_device *adev)
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{
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uint64_t addr = adev->vce.gpu_addr;
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uint32_t size;
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WREG32_P(mmVCE_CLOCK_GATING_A, 0, ~(1 << 16));
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WREG32_P(mmVCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000);
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WREG32_P(mmVCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F);
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WREG32(mmVCE_CLOCK_GATING_B, 0xf7);
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WREG32(mmVCE_LMI_CTRL, 0x00398000);
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WREG32_P(mmVCE_LMI_CACHE_CTRL, 0x0, ~0x1);
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WREG32(mmVCE_LMI_SWAP_CNTL, 0);
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WREG32(mmVCE_LMI_SWAP_CNTL1, 0);
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WREG32(mmVCE_LMI_VM_CTRL, 0);
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addr += AMDGPU_VCE_FIRMWARE_OFFSET;
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size = VCE_V2_0_FW_SIZE;
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WREG32(mmVCE_VCPU_CACHE_OFFSET0, addr & 0x7fffffff);
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WREG32(mmVCE_VCPU_CACHE_SIZE0, size);
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addr += size;
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size = VCE_V2_0_STACK_SIZE;
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WREG32(mmVCE_VCPU_CACHE_OFFSET1, addr & 0x7fffffff);
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WREG32(mmVCE_VCPU_CACHE_SIZE1, size);
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addr += size;
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size = VCE_V2_0_DATA_SIZE;
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WREG32(mmVCE_VCPU_CACHE_OFFSET2, addr & 0x7fffffff);
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WREG32(mmVCE_VCPU_CACHE_SIZE2, size);
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WREG32_P(mmVCE_LMI_CTRL2, 0x0, ~0x100);
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WREG32_FIELD(VCE_SYS_INT_EN, VCE_SYS_INT_TRAP_INTERRUPT_EN, 1);
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}
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static bool vce_v2_0_is_idle(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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return !(RREG32(mmSRBM_STATUS2) & SRBM_STATUS2__VCE_BUSY_MASK);
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}
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static int vce_v2_0_wait_for_idle(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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unsigned i;
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for (i = 0; i < adev->usec_timeout; i++) {
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if (vce_v2_0_is_idle(handle))
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return 0;
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}
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return -ETIMEDOUT;
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}
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/**
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* vce_v2_0_start - start VCE block
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*
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@ -245,6 +319,97 @@ static int vce_v2_0_stop(struct amdgpu_device *adev)
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return 0;
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}
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static void vce_v2_0_set_sw_cg(struct amdgpu_device *adev, bool gated)
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{
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u32 tmp;
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if (gated) {
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tmp = RREG32(mmVCE_CLOCK_GATING_B);
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tmp |= 0xe70000;
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WREG32(mmVCE_CLOCK_GATING_B, tmp);
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tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
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tmp |= 0xff000000;
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WREG32(mmVCE_UENC_CLOCK_GATING, tmp);
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tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
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tmp &= ~0x3fc;
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WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);
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WREG32(mmVCE_CGTT_CLK_OVERRIDE, 0);
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} else {
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tmp = RREG32(mmVCE_CLOCK_GATING_B);
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tmp |= 0xe7;
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tmp &= ~0xe70000;
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WREG32(mmVCE_CLOCK_GATING_B, tmp);
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tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
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tmp |= 0x1fe000;
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tmp &= ~0xff000000;
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WREG32(mmVCE_UENC_CLOCK_GATING, tmp);
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tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
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tmp |= 0x3fc;
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WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);
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}
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}
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static void vce_v2_0_set_dyn_cg(struct amdgpu_device *adev, bool gated)
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{
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u32 orig, tmp;
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/* LMI_MC/LMI_UMC always set in dynamic,
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* set {CGC_*_GATE_MODE, CGC_*_SW_GATE} = {0, 0}
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*/
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tmp = RREG32(mmVCE_CLOCK_GATING_B);
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tmp &= ~0x00060006;
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/* Exception for ECPU, IH, SEM, SYS blocks needs to be turned on/off by SW */
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if (gated) {
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tmp |= 0xe10000;
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WREG32(mmVCE_CLOCK_GATING_B, tmp);
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} else {
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tmp |= 0xe1;
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tmp &= ~0xe10000;
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WREG32(mmVCE_CLOCK_GATING_B, tmp);
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}
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orig = tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
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tmp &= ~0x1fe000;
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tmp &= ~0xff000000;
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if (tmp != orig)
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WREG32(mmVCE_UENC_CLOCK_GATING, tmp);
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orig = tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
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tmp &= ~0x3fc;
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if (tmp != orig)
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WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);
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/* set VCE_UENC_REG_CLOCK_GATING always in dynamic mode */
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WREG32(mmVCE_UENC_REG_CLOCK_GATING, 0x00);
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if(gated)
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WREG32(mmVCE_CGTT_CLK_OVERRIDE, 0);
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}
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static void vce_v2_0_enable_mgcg(struct amdgpu_device *adev, bool enable,
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bool sw_cg)
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{
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if (enable && (adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG)) {
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if (sw_cg)
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vce_v2_0_set_sw_cg(adev, true);
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else
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vce_v2_0_set_dyn_cg(adev, true);
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} else {
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vce_v2_0_disable_cg(adev);
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if (sw_cg)
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vce_v2_0_set_sw_cg(adev, false);
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else
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vce_v2_0_set_dyn_cg(adev, false);
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}
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}
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static int vce_v2_0_early_init(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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@ -365,177 +530,6 @@ static int vce_v2_0_resume(void *handle)
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return r;
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}
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static void vce_v2_0_set_sw_cg(struct amdgpu_device *adev, bool gated)
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{
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u32 tmp;
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if (gated) {
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tmp = RREG32(mmVCE_CLOCK_GATING_B);
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tmp |= 0xe70000;
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WREG32(mmVCE_CLOCK_GATING_B, tmp);
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tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
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tmp |= 0xff000000;
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WREG32(mmVCE_UENC_CLOCK_GATING, tmp);
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tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
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tmp &= ~0x3fc;
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WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);
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WREG32(mmVCE_CGTT_CLK_OVERRIDE, 0);
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} else {
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tmp = RREG32(mmVCE_CLOCK_GATING_B);
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tmp |= 0xe7;
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tmp &= ~0xe70000;
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WREG32(mmVCE_CLOCK_GATING_B, tmp);
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tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
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tmp |= 0x1fe000;
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tmp &= ~0xff000000;
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WREG32(mmVCE_UENC_CLOCK_GATING, tmp);
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tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
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tmp |= 0x3fc;
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WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);
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}
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}
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static void vce_v2_0_set_dyn_cg(struct amdgpu_device *adev, bool gated)
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{
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u32 orig, tmp;
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/* LMI_MC/LMI_UMC always set in dynamic,
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* set {CGC_*_GATE_MODE, CGC_*_SW_GATE} = {0, 0}
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*/
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tmp = RREG32(mmVCE_CLOCK_GATING_B);
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tmp &= ~0x00060006;
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/* Exception for ECPU, IH, SEM, SYS blocks needs to be turned on/off by SW */
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if (gated) {
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tmp |= 0xe10000;
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WREG32(mmVCE_CLOCK_GATING_B, tmp);
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} else {
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tmp |= 0xe1;
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tmp &= ~0xe10000;
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WREG32(mmVCE_CLOCK_GATING_B, tmp);
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}
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orig = tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
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tmp &= ~0x1fe000;
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tmp &= ~0xff000000;
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if (tmp != orig)
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WREG32(mmVCE_UENC_CLOCK_GATING, tmp);
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orig = tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
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tmp &= ~0x3fc;
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if (tmp != orig)
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WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);
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/* set VCE_UENC_REG_CLOCK_GATING always in dynamic mode */
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WREG32(mmVCE_UENC_REG_CLOCK_GATING, 0x00);
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if(gated)
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WREG32(mmVCE_CGTT_CLK_OVERRIDE, 0);
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}
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static void vce_v2_0_disable_cg(struct amdgpu_device *adev)
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{
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WREG32(mmVCE_CGTT_CLK_OVERRIDE, 7);
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}
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static void vce_v2_0_enable_mgcg(struct amdgpu_device *adev, bool enable,
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bool sw_cg)
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{
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if (enable && (adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG)) {
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if (sw_cg)
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vce_v2_0_set_sw_cg(adev, true);
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else
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vce_v2_0_set_dyn_cg(adev, true);
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} else {
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vce_v2_0_disable_cg(adev);
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if (sw_cg)
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vce_v2_0_set_sw_cg(adev, false);
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else
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vce_v2_0_set_dyn_cg(adev, false);
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}
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}
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static void vce_v2_0_init_cg(struct amdgpu_device *adev)
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{
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u32 tmp;
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tmp = RREG32(mmVCE_CLOCK_GATING_A);
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tmp &= ~0xfff;
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tmp |= ((0 << 0) | (4 << 4));
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tmp |= 0x40000;
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WREG32(mmVCE_CLOCK_GATING_A, tmp);
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tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
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tmp &= ~0xfff;
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tmp |= ((0 << 0) | (4 << 4));
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WREG32(mmVCE_UENC_CLOCK_GATING, tmp);
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tmp = RREG32(mmVCE_CLOCK_GATING_B);
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tmp |= 0x10;
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tmp &= ~0x100000;
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WREG32(mmVCE_CLOCK_GATING_B, tmp);
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}
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static void vce_v2_0_mc_resume(struct amdgpu_device *adev)
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{
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uint64_t addr = adev->vce.gpu_addr;
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uint32_t size;
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WREG32_P(mmVCE_CLOCK_GATING_A, 0, ~(1 << 16));
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WREG32_P(mmVCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000);
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WREG32_P(mmVCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F);
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WREG32(mmVCE_CLOCK_GATING_B, 0xf7);
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WREG32(mmVCE_LMI_CTRL, 0x00398000);
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WREG32_P(mmVCE_LMI_CACHE_CTRL, 0x0, ~0x1);
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WREG32(mmVCE_LMI_SWAP_CNTL, 0);
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WREG32(mmVCE_LMI_SWAP_CNTL1, 0);
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WREG32(mmVCE_LMI_VM_CTRL, 0);
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addr += AMDGPU_VCE_FIRMWARE_OFFSET;
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size = VCE_V2_0_FW_SIZE;
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WREG32(mmVCE_VCPU_CACHE_OFFSET0, addr & 0x7fffffff);
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WREG32(mmVCE_VCPU_CACHE_SIZE0, size);
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addr += size;
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size = VCE_V2_0_STACK_SIZE;
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WREG32(mmVCE_VCPU_CACHE_OFFSET1, addr & 0x7fffffff);
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WREG32(mmVCE_VCPU_CACHE_SIZE1, size);
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addr += size;
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size = VCE_V2_0_DATA_SIZE;
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WREG32(mmVCE_VCPU_CACHE_OFFSET2, addr & 0x7fffffff);
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WREG32(mmVCE_VCPU_CACHE_SIZE2, size);
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WREG32_P(mmVCE_LMI_CTRL2, 0x0, ~0x100);
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WREG32_FIELD(VCE_SYS_INT_EN, VCE_SYS_INT_TRAP_INTERRUPT_EN, 1);
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}
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static bool vce_v2_0_is_idle(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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return !(RREG32(mmSRBM_STATUS2) & SRBM_STATUS2__VCE_BUSY_MASK);
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}
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static int vce_v2_0_wait_for_idle(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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unsigned i;
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for (i = 0; i < adev->usec_timeout; i++) {
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if (vce_v2_0_is_idle(handle))
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return 0;
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}
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return -ETIMEDOUT;
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}
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static int vce_v2_0_soft_reset(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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