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ARM: dts: doc: Document missing binding for omap5-mpu 

The binding and support for omap5-mpu which has a cortex-a15
smp core, gic and integrated L2 cache has been existing for sometime.
So Documenting the missing binding here.

Cc: Benoit Cousson <bcousson@baylibre.com>
Signed-off-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
This commit is contained in:
Sricharan R 2013-11-08 16:08:48 +05:30 committed by Rob Herring
parent f04bda9039
commit f1e8e38114
1 changed files with 8 additions and 0 deletions
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8
Documentation/devicetree/bindings/arm/omap/mpu.txt
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@ -7,10 +7,18 @@ The MPU contain CPUs, GIC, L2 cache and a local PRCM.
Required properties: Required properties:
- compatible : Should be "ti,omap3-mpu" for OMAP3 - compatible : Should be "ti,omap3-mpu" for OMAP3
Should be "ti,omap4-mpu" for OMAP4 Should be "ti,omap4-mpu" for OMAP4
Should be "ti,omap5-mpu" for OMAP5
- ti,hwmods: "mpu" - ti,hwmods: "mpu"
Examples: Examples:
- For an OMAP5 SMP system:
mpu {
compatible = "ti,omap5-mpu";
ti,hwmods = "mpu"
};
- For an OMAP4 SMP system: - For an OMAP4 SMP system:
mpu { mpu {