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Blackfin arch: Fix CCLK and SCLK checks 

Fix CCLK and SCLK checks, combine all arch checks into one file
for maintance. Checkins that remove more lines than they add are always
good.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
This commit is contained in:
Robin Getz 2007-08-03 18:07:17 +08:00 committed by Bryan Wu
parent b99ab54d4f
commit f16295e7e7
13 changed files with 242 additions and 420 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

175
arch/blackfin/Kconfig
View File

@ -323,7 +323,7 @@ config CMDLINE
to the kernel, you may specify one here. As a minimum, you should specify
the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
comment "Board Setup"
comment "Clock/PLL Setup"
config CLKIN_HZ
int "Crystal Frequency in Hz"
@ -335,6 +335,118 @@ config CLKIN_HZ
help
The frequency of CLKIN crystal oscillator on the board in Hz.
config BFIN_KERNEL_CLOCK
bool "Re-program Clocks while Kernel boots?"
default n
help
This option decides if kernel clocks are re-programed from the
bootloader settings. If the clocks are not set, the SDRAM settings
are also not changed, and the Bootloader does 100% of the hardware
configuration.
config PLL_BYPASS
bool "Bypass PLL"
depends on BFIN_KERNEL_CLOCK
default n
config CLKIN_HALF
bool "Half Clock In"
depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
default n
help
If this is set the clock will be divided by 2, before it goes to the PLL.
config VCO_MULT
int "VCO Multiplier"
depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
range 1 64
default "22" if BFIN533_EZKIT
default "45" if BFIN533_STAMP
default "20" if BFIN537_STAMP
default "22" if BFIN533_BLUETECHNIX_CM
default "20" if BFIN537_BLUETECHNIX_CM
default "20" if BFIN561_BLUETECHNIX_CM
default "20" if BFIN561_EZKIT
help
This controls the frequency of the on-chip PLL. This can be between 1 and 64.
PLL Frequency = (Crystal Frequency) * (this setting)
choice
prompt "Core Clock Divider"
depends on BFIN_KERNEL_CLOCK
default CCLK_DIV_1
help
This sets the frequency of the core. It can be 1, 2, 4 or 8
Core Frequency = (PLL frequency) / (this setting)
config CCLK_DIV_1
bool "1"
config CCLK_DIV_2
bool "2"
config CCLK_DIV_4
bool "4"
config CCLK_DIV_8
bool "8"
endchoice
config SCLK_DIV
int "System Clock Divider"
depends on BFIN_KERNEL_CLOCK
range 1 15
default 5 if BFIN533_EZKIT
default 5 if BFIN533_STAMP
default 4 if BFIN537_STAMP
default 5 if BFIN533_BLUETECHNIX_CM
default 4 if BFIN537_BLUETECHNIX_CM
default 4 if BFIN561_BLUETECHNIX_CM
default 5 if BFIN561_EZKIT
help
This sets the frequency of the system clock (including SDRAM or DDR).
This can be between 1 and 15
System Clock = (PLL frequency) / (this setting)
#
# Max & Min Speeds for various Chips
#
config MAX_VCO_HZ
int
default 600000000 if BF522
default 600000000 if BF525
default 600000000 if BF527
default 400000000 if BF531
default 400000000 if BF532
default 750000000 if BF533
default 500000000 if BF534
default 400000000 if BF536
default 600000000 if BF537
default 533000000 if BF538
default 533000000 if BF539
default 600000000 if BF542
default 533000000 if BF544
default 533000000 if BF549
default 600000000 if BF561
config MIN_VCO_HZ
int
default 50000000
config MAX_SCLK_HZ
int
default 133000000
config MIN_SCLK_HZ
int
default 27000000
comment "Kernel Timer/Scheduler"
source kernel/Kconfig.hz
comment "Memory Setup"
config MEM_SIZE
int "SDRAM Memory Size in MBytes"
default 32 if BFIN533_EZKIT
@ -448,10 +560,6 @@ endmenu
menu "Blackfin Kernel Optimizations"
comment "Timer Tick"
source kernel/Kconfig.hz
comment "Memory Optimizations"
config I_ENTRY_L1
@ -672,63 +780,6 @@ config L1_MAX_PIECE
Set the max memory pieces for the L1 SRAM allocation algorithm.
Min value is 16. Max value is 1024.
menu "Clock Settings"
config BFIN_KERNEL_CLOCK
bool "Re-program Clocks while Kernel boots?"
default n
help
This option decides if kernel clocks are re-programed from the
bootloader settings. If the clocks are not set, the SDRAM settings
are also not changed, and the Bootloader does 100% of the hardware
configuration.
config VCO_MULT
int "VCO Multiplier"
depends on BFIN_KERNEL_CLOCK
default "22" if BFIN533_EZKIT
default "45" if BFIN533_STAMP
default "20" if BFIN537_STAMP
default "22" if BFIN533_BLUETECHNIX_CM
default "20" if BFIN537_BLUETECHNIX_CM
default "20" if BFIN561_BLUETECHNIX_CM
default "20" if BFIN561_EZKIT
config CCLK_DIV
int "Core Clock Divider"
depends on BFIN_KERNEL_CLOCK
default 1 if BFIN533_EZKIT
default 1 if BFIN533_STAMP
default 1 if BFIN537_STAMP
default 1 if BFIN533_BLUETECHNIX_CM
default 1 if BFIN537_BLUETECHNIX_CM
default 1 if BFIN561_BLUETECHNIX_CM
default 1 if BFIN561_EZKIT
config SCLK_DIV
int "System Clock Divider"
depends on BFIN_KERNEL_CLOCK
default 5 if BFIN533_EZKIT
default 5 if BFIN533_STAMP
default 4 if BFIN537_STAMP
default 5 if BFIN533_BLUETECHNIX_CM
default 4 if BFIN537_BLUETECHNIX_CM
default 4 if BFIN561_BLUETECHNIX_CM
default 5 if BFIN561_EZKIT
config CLKIN_HALF
bool "Half ClockIn"
depends on BFIN_KERNEL_CLOCK
default n
config PLL_BYPASS
bool "Bypass PLL"
depends on BFIN_KERNEL_CLOCK
default n
endmenu
comment "Asynchonous Memory Configuration"
menu "EBIU_AMBCTL Global Control"

1
arch/blackfin/mach-bf533/head.S
View File

@ -32,6 +32,7 @@
#include <asm/blackfin.h>
#include <asm/trace.h>
#if CONFIG_BFIN_KERNEL_CLOCK
#include <asm/mach-common/clocks.h>
#include <asm/mach/mem_init.h>
#endif
#if CONFIG_DEBUG_KERNEL_START

1
arch/blackfin/mach-bf537/head.S
View File

@ -33,6 +33,7 @@
#include <asm/trace.h>
#if CONFIG_BFIN_KERNEL_CLOCK
#include <asm/mach-common/clocks.h>
#include <asm/mach/mem_init.h>
#endif

1
arch/blackfin/mach-bf548/head.S
View File

@ -31,6 +31,7 @@
#include <asm/blackfin.h>
#include <asm/trace.h>
#if CONFIG_BFIN_KERNEL_CLOCK
#include <asm/mach-common/clocks.h>
#include <asm/mach/mem_init.h>
#endif

1
arch/blackfin/mach-bf561/head.S
View File

@ -33,6 +33,7 @@
#include <asm/trace.h>
#if CONFIG_BFIN_KERNEL_CLOCK
#include <asm/mach-common/clocks.h>
#include <asm/mach/mem_init.h>
#endif

2
arch/blackfin/mach-common/Makefile
View File

@ -4,7 +4,7 @@
obj-y := \
cache.o cacheinit.o cplbhdlr.o cplbmgr.o entry.o \
interrupt.o lock.o irqpanic.o
interrupt.o lock.o irqpanic.o arch_checks.o
obj-$(CONFIG_CPLB_INFO) += cplbinfo.o
obj-$(CONFIG_BFIN_SINGLE_CORE) += ints-priority-sc.o

55
arch/blackfin/mach-common/arch_checks.c Normal file
View File

@ -0,0 +1,55 @@
/*
* File: arch/blackfin/mach-common/arch_checks.c
* Based on:
* Author: Robin Getz <rgetz@blackfin.uclinux.org>
*
* Created: 25Jul07
* Description: Do some checking to make sure things are OK
*
* Modified:
* Copyright 2004-2007 Analog Devices Inc.
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, see the file COPYING, or write
* to the Free Software Foundation, Inc.,
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <asm/mach/anomaly.h>
#include <asm/mach-common/clocks.h>
#ifdef CONFIG_BFIN_KERNEL_CLOCK
# if (CONFIG_VCO_HZ > CONFIG_MAX_VCO_HZ)
# error "VCO selected is more than maximum value. Please change the VCO multipler"
# endif
# if (CONFIG_SCLK_HZ > CONFIG_MAX_SCLK_HZ)
# error "Sclk value selected is more than maximum. Please select a proper value for SCLK multiplier"
# endif
# if (CONFIG_SCLK_HZ < CONFIG_MIN_SCLK_HZ)
# error "Sclk value selected is less than minimum. Please select a proper value for SCLK multiplier"
# endif
# if (ANOMALY_05000273) && (CONFIG_SCLK_HZ * 2 > CONFIG_CCLK_HZ)
# error "ANOMALY 05000273, please make sure CCLK is at least 2x SCLK"
# endif
# if (CONFIG_SCLK_HZ > CONFIG_CCLK_HZ) && (CONFIG_SCLK_HZ != CONFIG_CLKIN_HZ) && (CONFIG_CCLK_HZ != CONFIG_CLKIN_HZ)
# error "Please select sclk less than cclk"
# endif
#endif /* CONFIG_BFIN_KERNEL_CLOCK */

2
arch/blackfin/mach-common/dpmc.S
View File

@ -300,7 +300,7 @@ ENTRY(_sleep_deeper)
P0.H = hi(PLL_CTL);
P0.L = lo(PLL_CTL);
R5 = W[P0](z);
R0.L = (MIN_VC/CONFIG_CLKIN_HZ) << 9;
R0.L = (CONFIG_MIN_VCO_HZ/CONFIG_CLKIN_HZ) << 9;
W[P0] = R0.l;
SSYNC;

91
include/asm-blackfin/mach-bf533/bf533.h
View File

@ -141,97 +141,6 @@
#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO)
#define MAX_VC 650000000
#define MIN_VC 50000000
#ifdef CONFIG_BFIN_KERNEL_CLOCK
/********************************PLL Settings **************************************/
#if (CONFIG_VCO_MULT < 0)
#error "VCO Multiplier is less than 0. Please select a different value"
#endif
#if (CONFIG_VCO_MULT == 0)
#error "VCO Multiplier should be greater than 0. Please select a different value"
#endif
#if (CONFIG_VCO_MULT > 64)
#error "VCO Multiplier is more than 64. Please select a different value"
#endif
#ifndef CONFIG_CLKIN_HALF
#define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)
#else
#define CONFIG_VCO_HZ ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)/2)
#endif
#ifndef CONFIG_PLL_BYPASS
#define CONFIG_CCLK_HZ (CONFIG_VCO_HZ/CONFIG_CCLK_DIV)
#define CONFIG_SCLK_HZ (CONFIG_VCO_HZ/CONFIG_SCLK_DIV)
#else
#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
#endif
#if (CONFIG_SCLK_DIV < 1)
#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value"
#endif
#if (CONFIG_SCLK_DIV > 15)
#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value"
#endif
#if (CONFIG_CCLK_DIV != 1)
#if (CONFIG_CCLK_DIV != 2)
#if (CONFIG_CCLK_DIV != 4)
#if (CONFIG_CCLK_DIV != 8)
#error "CCLK DIV can be 1,2,4 or 8 only. Please select a proper value"
#endif
#endif
#endif
#endif
#if (CONFIG_VCO_HZ > MAX_VC)
#error "VCO selected is more than maximum value. Please change the VCO multipler"
#endif
#if (CONFIG_SCLK_HZ > 133000000)
#error "Sclk value selected is more than maximum. Please select a proper value for SCLK multiplier"
#endif
#if (CONFIG_SCLK_HZ < 27000000)
#error "Sclk value selected is less than minimum. Please select a proper value for SCLK multiplier"
#endif
#if (CONFIG_SCLK_HZ > CONFIG_CCLK_HZ)
#if (CONFIG_SCLK_HZ != CONFIG_CLKIN_HZ)
#if (CONFIG_CCLK_HZ != CONFIG_CLKIN_HZ)
#error "Please select sclk less than cclk"
#endif
#endif
#endif
#if (CONFIG_CCLK_DIV == 1)
#define CONFIG_CCLK_ACT_DIV CCLK_DIV1
#endif
#if (CONFIG_CCLK_DIV == 2)
#define CONFIG_CCLK_ACT_DIV CCLK_DIV2
#endif
#if (CONFIG_CCLK_DIV == 4)
#define CONFIG_CCLK_ACT_DIV CCLK_DIV4
#endif
#if (CONFIG_CCLK_DIV == 8)
#define CONFIG_CCLK_ACT_DIV CCLK_DIV8
#endif
#ifndef CONFIG_CCLK_ACT_DIV
#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
#endif
#if ANOMALY_05000273 && (CONFIG_CCLK_DIV == 1)
#error ANOMALY 05000273, please make sure CCLK is at least 2x SCLK
#endif
#endif /* CONFIG_BFIN_KERNEL_CLOCK */
#ifdef CONFIG_BF533
#define CPU "BF533"
#define CPUID 0x027a5000

91
include/asm-blackfin/mach-bf537/bf537.h
View File

@ -121,97 +121,6 @@
#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO)
#define MAX_VC 650000000
#define MIN_VC 50000000
/********************************PLL Settings **************************************/
#ifdef CONFIG_BFIN_KERNEL_CLOCK
#if (CONFIG_VCO_MULT < 0)
#error "VCO Multiplier is less than 0. Please select a different value"
#endif
#if (CONFIG_VCO_MULT == 0)
#error "VCO Multiplier should be greater than 0. Please select a different value"
#endif
#if (CONFIG_VCO_MULT > 64)
#error "VCO Multiplier is more than 64. Please select a different value"
#endif
#ifndef CONFIG_CLKIN_HALF
#define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)
#else
#define CONFIG_VCO_HZ ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)/2)
#endif
#ifndef CONFIG_PLL_BYPASS
#define CONFIG_CCLK_HZ (CONFIG_VCO_HZ/CONFIG_CCLK_DIV)
#define CONFIG_SCLK_HZ (CONFIG_VCO_HZ/CONFIG_SCLK_DIV)
#else
#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
#endif
#if (CONFIG_SCLK_DIV < 1)
#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value"
#endif
#if (CONFIG_SCLK_DIV > 15)
#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value"
#endif
#if (CONFIG_CCLK_DIV != 1)
#if (CONFIG_CCLK_DIV != 2)
#if (CONFIG_CCLK_DIV != 4)
#if (CONFIG_CCLK_DIV != 8)
#error "CCLK DIV can be 1,2,4 or 8 only. Please select a proper value"
#endif
#endif
#endif
#endif
#if (CONFIG_VCO_HZ > MAX_VC)
#error "VCO selected is more than maximum value. Please change the VCO multipler"
#endif
#if (CONFIG_SCLK_HZ > 133000000)
#error "Sclk value selected is more than maximum. Please select a proper value for SCLK multiplier"
#endif
#if (CONFIG_SCLK_HZ < 27000000)
#error "Sclk value selected is less than minimum. Please select a proper value for SCLK multiplier"
#endif
#if (CONFIG_SCLK_HZ >= CONFIG_CCLK_HZ)
#if (CONFIG_SCLK_HZ != CONFIG_CLKIN_HZ)
#if (CONFIG_CCLK_HZ != CONFIG_CLKIN_HZ)
#error "Please select sclk less than cclk"
#endif
#endif
#endif
#if (CONFIG_CCLK_DIV == 1)
#define CONFIG_CCLK_ACT_DIV CCLK_DIV1
#endif
#if (CONFIG_CCLK_DIV == 2)
#define CONFIG_CCLK_ACT_DIV CCLK_DIV2
#endif
#if (CONFIG_CCLK_DIV == 4)
#define CONFIG_CCLK_ACT_DIV CCLK_DIV4
#endif
#if (CONFIG_CCLK_DIV == 8)
#define CONFIG_CCLK_ACT_DIV CCLK_DIV8
#endif
#ifndef CONFIG_CCLK_ACT_DIV
#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
#endif
#if ANOMALY_05000273 && (CONFIG_CCLK_DIV == 1)
#error ANOMALY 05000273, please make sure CCLK is at least 2x SCLK
#endif
#endif /* CONFIG_BFIN_KERNEL_CLOCK */
#ifdef CONFIG_BF537
#define CPU "BF537"
#define CPUID 0x027c8000

87
include/asm-blackfin/mach-bf548/bf548.h
View File

@ -106,93 +106,6 @@
#define AMGCTLVAL (V_AMBEN | V_AMCKEN)
#define MAX_VC 650000000
#define MIN_VC 50000000
/********************************PLL Settings **************************************/
#ifdef CONFIG_BFIN_KERNEL_CLOCK
#if (CONFIG_VCO_MULT < 0)
#error "VCO Multiplier is less than 0. Please select a different value"
#endif
#if (CONFIG_VCO_MULT == 0)
#error "VCO Multiplier should be greater than 0. Please select a different value"
#endif
#if (CONFIG_VCO_MULT > 64)
#error "VCO Multiplier is more than 64. Please select a different value"
#endif
#ifndef CONFIG_CLKIN_HALF
#define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)
#else
#define CONFIG_VCO_HZ ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)/2)
#endif
#ifndef CONFIG_PLL_BYPASS
#define CONFIG_CCLK_HZ (CONFIG_VCO_HZ/CONFIG_CCLK_DIV)
#define CONFIG_SCLK_HZ (CONFIG_VCO_HZ/CONFIG_SCLK_DIV)
#else
#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
#endif
#if (CONFIG_SCLK_DIV < 1)
#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value"
#endif
#if (CONFIG_SCLK_DIV > 15)
#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value"
#endif
#if (CONFIG_CCLK_DIV != 1)
#if (CONFIG_CCLK_DIV != 2)
#if (CONFIG_CCLK_DIV != 4)
#if (CONFIG_CCLK_DIV != 8)
#error "CCLK DIV can be 1,2,4 or 8 only. Please select a proper value"
#endif
#endif
#endif
#endif
#if (CONFIG_VCO_HZ > MAX_VC)
#error "VCO selected is more than maximum value. Please change the VCO multipler"
#endif
#if (CONFIG_SCLK_HZ > 133000000)
#error "Sclk value selected is more than maximum. Please select a proper value for SCLK multiplier"
#endif
#if (CONFIG_SCLK_HZ < 27000000)
#error "Sclk value selected is less than minimum. Please select a proper value for SCLK multiplier"
#endif
#if (CONFIG_SCLK_HZ >= CONFIG_CCLK_HZ)
#if (CONFIG_SCLK_HZ != CONFIG_CLKIN_HZ)
#if (CONFIG_CCLK_HZ != CONFIG_CLKIN_HZ)
#error "Please select sclk less than cclk"
#endif
#endif
#endif
#if (CONFIG_CCLK_DIV == 1)
#define CONFIG_CCLK_ACT_DIV CCLK_DIV1
#endif
#if (CONFIG_CCLK_DIV == 2)
#define CONFIG_CCLK_ACT_DIV CCLK_DIV2
#endif
#if (CONFIG_CCLK_DIV == 4)
#define CONFIG_CCLK_ACT_DIV CCLK_DIV4
#endif
#if (CONFIG_CCLK_DIV == 8)
#define CONFIG_CCLK_ACT_DIV CCLK_DIV8
#endif
#ifndef CONFIG_CCLK_ACT_DIV
#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
#endif
#endif /* CONFIG_BFIN_KERNEL_CLOCK */
#ifdef CONFIG_BF542
#define CPU "BF542"
#define CPUID 0x027c8000

87
include/asm-blackfin/mach-bf561/bf561.h
View File

@ -230,93 +230,6 @@
#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO | V_B0PEN | V_B1PEN | V_B2PEN | V_B3PEN | 0x0002)
#define MAX_VC 600000000
#define MIN_VC 50000000
/******************************* PLL Settings ********************************/
#ifdef CONFIG_BFIN_KERNEL_CLOCK
#if (CONFIG_VCO_MULT < 0)
#error "VCO Multiplier is less than 0. Please select a different value"
#endif
#if (CONFIG_VCO_MULT == 0)
#error "VCO Multiplier should be greater than 0. Please select a different value"
#endif
#ifndef CONFIG_CLKIN_HALF
#define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)
#else
#define CONFIG_VCO_HZ ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)/2)
#endif
#ifndef CONFIG_PLL_BYPASS
#define CONFIG_CCLK_HZ (CONFIG_VCO_HZ/CONFIG_CCLK_DIV)
#define CONFIG_SCLK_HZ (CONFIG_VCO_HZ/CONFIG_SCLK_DIV)
#else
#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
#endif
#if (CONFIG_SCLK_DIV < 1)
#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value"
#endif
#if (CONFIG_SCLK_DIV > 15)
#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value"
#endif
#if (CONFIG_CCLK_DIV != 1)
#if (CONFIG_CCLK_DIV != 2)
#if (CONFIG_CCLK_DIV != 4)
#if (CONFIG_CCLK_DIV != 8)
#error "CCLK DIV can be 1,2,4 or 8 only. Please select a proper value"
#endif
#endif
#endif
#endif
#if (CONFIG_VCO_HZ > MAX_VC)
#error "VCO selected is more than maximum value. Please change the VCO multipler"
#endif
#if (CONFIG_SCLK_HZ > 133000000)
#error "Sclk value selected is more than maximum. Please select a proper value for SCLK multiplier"
#endif
#if (CONFIG_SCLK_HZ < 27000000)
#error "Sclk value selected is less than minimum. Please select a proper value for SCLK multiplier"
#endif
#if (CONFIG_SCLK_HZ >= CONFIG_CCLK_HZ)
#if (CONFIG_SCLK_HZ != CONFIG_CLKIN_HZ)
#if (CONFIG_CCLK_HZ != CONFIG_CLKIN_HZ)
#error "Please select sclk less than cclk"
#endif
#endif
#endif
#if (CONFIG_CCLK_DIV == 1)
#define CONFIG_CCLK_ACT_DIV CCLK_DIV1
#endif
#if (CONFIG_CCLK_DIV == 2)
#define CONFIG_CCLK_ACT_DIV CCLK_DIV2
#endif
#if (CONFIG_CCLK_DIV == 4)
#define CONFIG_CCLK_ACT_DIV CCLK_DIV4
#endif
#if (CONFIG_CCLK_DIV == 8)
#define CONFIG_CCLK_ACT_DIV CCLK_DIV8
#endif
#ifndef CONFIG_CCLK_ACT_DIV
#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
#endif
#if ANOMALY_05000273 && (CONFIG_CCLK_DIV == 1)
#error ANOMALY 05000273, please make sure CCLK is at least 2x SCLK
#endif
#endif /* CONFIG_BFIN_KERNEL_CLOCK */
#ifdef CONFIG_BF561
#define CPU "BF561"
#define CPUID 0x027bb000

68
include/asm-blackfin/mach-common/clocks.h Normal file
View File

@ -0,0 +1,68 @@
/*
* File: include/asm-blackfin/mach-common/clocks.h
* Based on: include/asm-blackfin/mach-bf537/bf537.h
* Author: Robin Getz <rgetz@blackfin.uclinux.org>
*
* Created: 25Jul07
* Description: Common Clock definitions for various kernel files
*
* Modified:
* Copyright 2004-2007 Analog Devices Inc.
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, see the file COPYING, or write
* to the Free Software Foundation, Inc.,
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifdef CONFIG_CCLK_DIV_1
# define CONFIG_CCLK_ACT_DIV CCLK_DIV1
# define CONFIG_CCLK_DIV 1
#endif
#ifdef CONFIG_CCLK_DIV_2
# define CONFIG_CCLK_ACT_DIV CCLK_DIV2
# define CONFIG_CCLK_DIV 2
#endif
#ifdef CONFIG_CCLK_DIV_4
# define CONFIG_CCLK_ACT_DIV CCLK_DIV4
# define CONFIG_CCLK_DIV 4
#endif
#ifdef CONFIG_CCLK_DIV_8
# define CONFIG_CCLK_ACT_DIV CCLK_DIV8
# define CONFIG_CCLK_DIV 8
#endif
#ifndef CONFIG_PLL_BYPASS
# ifndef CONFIG_CLKIN_HALF
# define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)
# else
# define CONFIG_VCO_HZ ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)/2)
# endif
# define CONFIG_CCLK_HZ (CONFIG_VCO_HZ/CONFIG_CCLK_DIV)
# define CONFIG_SCLK_HZ (CONFIG_VCO_HZ/CONFIG_SCLK_DIV)
#else
# define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ)
# define CONFIG_CCLK_HZ (CONFIG_CLKIN_HZ)
# define CONFIG_SCLK_HZ (CONFIG_CLKIN_HZ)
# define CONFIG_VCO_MULT 0
#endif