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ARM: 7289/1: vmlinux.lds.S: do not hardcode cacheline size as 32 bytes 

The linker script assumes a cacheline size of 32 bytes when aligning
the .data..cacheline_aligned and .data..percpu sections.

This patch updates the script to use L1_CACHE_BYTES, which should be set
to 64 on platforms that require it.

Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Will Deacon 2012-01-20 11:55:54 +01:00 committed by Russell King
parent 06e9905152
commit f0d5375e3c
1 changed files with 4 additions and 3 deletions
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7
arch/arm/kernel/vmlinux.lds.S
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@ -4,6 +4,7 @@
*/
#include <asm-generic/vmlinux.lds.h>
#include <asm/cache.h>
#include <asm/thread_info.h>
#include <asm/memory.h>
#include <asm/page.h>
@ -181,7 +182,7 @@ SECTIONS
}
#endif
PERCPU_SECTION(32)
PERCPU_SECTION(L1_CACHE_BYTES)
#ifdef CONFIG_XIP_KERNEL
__data_loc = ALIGN(4); /* location in binary */
@ -212,8 +213,8 @@ SECTIONS
#endif
NOSAVE_DATA
CACHELINE_ALIGNED_DATA(32)
READ_MOSTLY_DATA(32)
CACHELINE_ALIGNED_DATA(L1_CACHE_BYTES)
READ_MOSTLY_DATA(L1_CACHE_BYTES)
/*
* The exception fixup table (might need resorting at runtime)