IXP4xx: Always ioremap() Queue Manager MMIO region at boot.
It doesn't make much sense to map QMgr dynamically - we almost always need it and the static mapping will be needed for little-endian data-coherent operation (to make QMgr region value-coherent). Signed-off-by: Krzysztof Hałasa <khc@pm.waw.pl>
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05cd3db0df
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f0cdb15329
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@ -67,6 +67,11 @@ static struct map_desc ixp4xx_io_desc[] __initdata = {
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.pfn = __phys_to_pfn(IXP4XX_PCI_CFG_BASE_PHYS),
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.pfn = __phys_to_pfn(IXP4XX_PCI_CFG_BASE_PHYS),
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.length = IXP4XX_PCI_CFG_REGION_SIZE,
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.length = IXP4XX_PCI_CFG_REGION_SIZE,
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.type = MT_DEVICE
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.type = MT_DEVICE
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}, { /* Queue Manager */
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.virtual = (unsigned long)IXP4XX_QMGR_BASE_VIRT,
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.pfn = __phys_to_pfn(IXP4XX_QMGR_BASE_PHYS),
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.length = IXP4XX_QMGR_REGION_SIZE,
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.type = MT_DEVICE
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},
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},
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#ifdef CONFIG_DEBUG_LL
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#ifdef CONFIG_DEBUG_LL
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{ /* Debug UART mapping */
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{ /* Debug UART mapping */
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@ -30,19 +30,20 @@
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*
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*
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* 0x50000000 0x10000000 ioremap'd EXP BUS
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* 0x50000000 0x10000000 ioremap'd EXP BUS
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*
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*
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* 0x6000000 0x00004000 ioremap'd QMgr
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* 0x60000000 0x00004000 0xffbe7000 QMgr
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*
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*
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* 0xC0000000 0x00001000 0xffbff000 PCI CFG
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* 0xC8000000 0x00013000 0xffbeb000 On-Chip Peripherals
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*
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*
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* 0xC4000000 0x00001000 0xffbfe000 EXP CFG
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* 0xC4000000 0x00001000 0xffbfe000 EXP CFG
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*
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*
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* 0xC8000000 0x00013000 0xffbeb000 On-Chip Peripherals
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* 0xC0000000 0x00001000 0xffbff000 PCI CFG
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*/
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*/
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/*
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/*
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* Queue Manager
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* Queue Manager
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*/
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*/
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#define IXP4XX_QMGR_BASE_PHYS (0x60000000)
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#define IXP4XX_QMGR_BASE_PHYS (0x60000000)
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#define IXP4XX_QMGR_BASE_VIRT IOMEM(0xFFBE7000)
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#define IXP4XX_QMGR_REGION_SIZE (0x00004000)
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#define IXP4XX_QMGR_REGION_SIZE (0x00004000)
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/*
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/*
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@ -86,7 +86,7 @@ void qmgr_release_queue(unsigned int queue);
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static inline void qmgr_put_entry(unsigned int queue, u32 val)
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static inline void qmgr_put_entry(unsigned int queue, u32 val)
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{
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{
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extern struct qmgr_regs __iomem *qmgr_regs;
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const struct qmgr_regs __iomem *qmgr_regs = (void __iomem *)IXP4XX_QMGR_BASE_VIRT;
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#if DEBUG_QMGR
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#if DEBUG_QMGR
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BUG_ON(!qmgr_queue_descs[queue]); /* not yet requested */
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BUG_ON(!qmgr_queue_descs[queue]); /* not yet requested */
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@ -99,7 +99,7 @@ static inline void qmgr_put_entry(unsigned int queue, u32 val)
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static inline u32 qmgr_get_entry(unsigned int queue)
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static inline u32 qmgr_get_entry(unsigned int queue)
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{
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{
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u32 val;
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u32 val;
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extern struct qmgr_regs __iomem *qmgr_regs;
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const struct qmgr_regs __iomem *qmgr_regs = (void __iomem *)IXP4XX_QMGR_BASE_VIRT;
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val = __raw_readl(&qmgr_regs->acc[queue][0]);
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val = __raw_readl(&qmgr_regs->acc[queue][0]);
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#if DEBUG_QMGR
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#if DEBUG_QMGR
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BUG_ON(!qmgr_queue_descs[queue]); /* not yet requested */
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BUG_ON(!qmgr_queue_descs[queue]); /* not yet requested */
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@ -112,14 +112,14 @@ static inline u32 qmgr_get_entry(unsigned int queue)
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static inline int __qmgr_get_stat1(unsigned int queue)
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static inline int __qmgr_get_stat1(unsigned int queue)
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{
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{
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extern struct qmgr_regs __iomem *qmgr_regs;
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const struct qmgr_regs __iomem *qmgr_regs = (void __iomem *)IXP4XX_QMGR_BASE_VIRT;
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return (__raw_readl(&qmgr_regs->stat1[queue >> 3])
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return (__raw_readl(&qmgr_regs->stat1[queue >> 3])
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>> ((queue & 7) << 2)) & 0xF;
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>> ((queue & 7) << 2)) & 0xF;
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}
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}
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static inline int __qmgr_get_stat2(unsigned int queue)
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static inline int __qmgr_get_stat2(unsigned int queue)
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{
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{
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extern struct qmgr_regs __iomem *qmgr_regs;
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const struct qmgr_regs __iomem *qmgr_regs = (void __iomem *)IXP4XX_QMGR_BASE_VIRT;
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BUG_ON(queue >= HALF_QUEUES);
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BUG_ON(queue >= HALF_QUEUES);
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return (__raw_readl(&qmgr_regs->stat2[queue >> 4])
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return (__raw_readl(&qmgr_regs->stat2[queue >> 4])
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>> ((queue & 0xF) << 1)) & 0x3;
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>> ((queue & 0xF) << 1)) & 0x3;
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@ -145,7 +145,7 @@ static inline int qmgr_stat_empty(unsigned int queue)
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*/
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*/
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static inline int qmgr_stat_below_low_watermark(unsigned int queue)
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static inline int qmgr_stat_below_low_watermark(unsigned int queue)
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{
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{
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extern struct qmgr_regs __iomem *qmgr_regs;
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const struct qmgr_regs __iomem *qmgr_regs = (void __iomem *)IXP4XX_QMGR_BASE_VIRT;
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if (queue >= HALF_QUEUES)
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if (queue >= HALF_QUEUES)
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return (__raw_readl(&qmgr_regs->statne_h) >>
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return (__raw_readl(&qmgr_regs->statne_h) >>
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(queue - HALF_QUEUES)) & 0x01;
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(queue - HALF_QUEUES)) & 0x01;
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@ -172,7 +172,7 @@ static inline int qmgr_stat_above_high_watermark(unsigned int queue)
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*/
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*/
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static inline int qmgr_stat_full(unsigned int queue)
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static inline int qmgr_stat_full(unsigned int queue)
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{
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{
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extern struct qmgr_regs __iomem *qmgr_regs;
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const struct qmgr_regs __iomem *qmgr_regs = (void __iomem *)IXP4XX_QMGR_BASE_VIRT;
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if (queue >= HALF_QUEUES)
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if (queue >= HALF_QUEUES)
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return (__raw_readl(&qmgr_regs->statf_h) >>
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return (__raw_readl(&qmgr_regs->statf_h) >>
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(queue - HALF_QUEUES)) & 0x01;
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(queue - HALF_QUEUES)) & 0x01;
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@ -14,7 +14,7 @@
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#include <linux/module.h>
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#include <linux/module.h>
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#include <mach/qmgr.h>
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#include <mach/qmgr.h>
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struct qmgr_regs __iomem *qmgr_regs;
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static const struct qmgr_regs __iomem *qmgr_regs = (void __iomem *)IXP4XX_QMGR_BASE_VIRT;
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static struct resource *mem_res;
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static struct resource *mem_res;
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static spinlock_t qmgr_lock;
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static spinlock_t qmgr_lock;
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static u32 used_sram_bitmap[4]; /* 128 16-dword pages */
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static u32 used_sram_bitmap[4]; /* 128 16-dword pages */
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@ -32,7 +32,7 @@ void qmgr_set_irq(unsigned int queue, int src,
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spin_lock_irqsave(&qmgr_lock, flags);
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spin_lock_irqsave(&qmgr_lock, flags);
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if (queue < HALF_QUEUES) {
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if (queue < HALF_QUEUES) {
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u32 __iomem *reg;
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const u32 __iomem *reg;
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int bit;
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int bit;
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BUG_ON(src > QUEUE_IRQ_SRC_NOT_FULL);
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BUG_ON(src > QUEUE_IRQ_SRC_NOT_FULL);
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reg = &qmgr_regs->irqsrc[queue >> 3]; /* 8 queues per u32 */
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reg = &qmgr_regs->irqsrc[queue >> 3]; /* 8 queues per u32 */
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@ -293,12 +293,6 @@ static int qmgr_init(void)
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if (mem_res == NULL)
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if (mem_res == NULL)
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return -EBUSY;
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return -EBUSY;
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qmgr_regs = ioremap(IXP4XX_QMGR_BASE_PHYS, IXP4XX_QMGR_REGION_SIZE);
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if (qmgr_regs == NULL) {
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err = -ENOMEM;
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goto error_map;
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}
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/* reset qmgr registers */
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/* reset qmgr registers */
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for (i = 0; i < 4; i++) {
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for (i = 0; i < 4; i++) {
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__raw_writel(0x33333333, &qmgr_regs->stat1[i]);
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__raw_writel(0x33333333, &qmgr_regs->stat1[i]);
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@ -347,8 +341,6 @@ static int qmgr_init(void)
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error_irq2:
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error_irq2:
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free_irq(IRQ_IXP4XX_QM1, NULL);
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free_irq(IRQ_IXP4XX_QM1, NULL);
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error_irq:
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error_irq:
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iounmap(qmgr_regs);
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error_map:
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release_mem_region(IXP4XX_QMGR_BASE_PHYS, IXP4XX_QMGR_REGION_SIZE);
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release_mem_region(IXP4XX_QMGR_BASE_PHYS, IXP4XX_QMGR_REGION_SIZE);
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return err;
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return err;
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}
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}
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@ -359,7 +351,6 @@ static void qmgr_remove(void)
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free_irq(IRQ_IXP4XX_QM2, NULL);
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free_irq(IRQ_IXP4XX_QM2, NULL);
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synchronize_irq(IRQ_IXP4XX_QM1);
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synchronize_irq(IRQ_IXP4XX_QM1);
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synchronize_irq(IRQ_IXP4XX_QM2);
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synchronize_irq(IRQ_IXP4XX_QM2);
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iounmap(qmgr_regs);
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release_mem_region(IXP4XX_QMGR_BASE_PHYS, IXP4XX_QMGR_REGION_SIZE);
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release_mem_region(IXP4XX_QMGR_BASE_PHYS, IXP4XX_QMGR_REGION_SIZE);
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}
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}
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@ -369,7 +360,6 @@ module_exit(qmgr_remove);
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MODULE_LICENSE("GPL v2");
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MODULE_LICENSE("GPL v2");
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MODULE_AUTHOR("Krzysztof Halasa");
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MODULE_AUTHOR("Krzysztof Halasa");
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EXPORT_SYMBOL(qmgr_regs);
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EXPORT_SYMBOL(qmgr_set_irq);
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EXPORT_SYMBOL(qmgr_set_irq);
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EXPORT_SYMBOL(qmgr_enable_irq);
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EXPORT_SYMBOL(qmgr_enable_irq);
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EXPORT_SYMBOL(qmgr_disable_irq);
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EXPORT_SYMBOL(qmgr_disable_irq);
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