nvmem: NXP LPC18xx EEPROM memory NVMEM driver
This commit adds support for NXP LPC18xx EEPROM memory found in NXP LPC185x/3x and LPC435x/3x/2x/1x devices. EEPROM size is 16384 bytes and it can be entirely read and written/erased with 1 word (4 bytes) granularity. The last page (128 bytes) contains the EEPROM initialization data and is not writable. Erase/program time is less than 3ms. The EEPROM device requires a ~1500 kHz clock (min 800 kHz, max 1600 kHz) that is generated dividing the system bus clock by the division factor, contained in the divider register (minus 1 encoded). EEPROM will be kept in Power Down mode except during read/write calls. Signed-off-by: Ariel D'Alessandro <ariel@vanguardiasur.com.ar> Acked-by: Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Ariel D'Alessandro
Greg Kroah-Hartman
parent
4020d07e91
commit
f02f8aee21
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@ -25,6 +25,15 @@ config NVMEM_IMX_OCOTP
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This driver can also be built as a module. If so, the module
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will be called nvmem-imx-ocotp.
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config NVMEM_LPC18XX_EEPROM
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tristate "NXP LPC18XX EEPROM Memory Support"
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depends on ARCH_LPC18XX || COMPILE_TEST
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help
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Say Y here to include support for NXP LPC18xx EEPROM memory found in
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NXP LPC185x/3x and LPC435x/3x/2x/1x devices.
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To compile this driver as a module, choose M here: the module
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will be called nvmem_lpc18xx_eeprom.
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config NVMEM_MXS_OCOTP
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tristate "Freescale MXS On-Chip OTP Memory Support"
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depends on ARCH_MXS || COMPILE_TEST
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@ -8,6 +8,8 @@ nvmem_core-y := core.o
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# Devices
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obj-$(CONFIG_NVMEM_IMX_OCOTP) += nvmem-imx-ocotp.o
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nvmem-imx-ocotp-y := imx-ocotp.o
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obj-$(CONFIG_NVMEM_LPC18XX_EEPROM) += nvmem_lpc18xx_eeprom.o
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nvmem_lpc18xx_eeprom-y := lpc18xx_eeprom.o
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obj-$(CONFIG_NVMEM_MXS_OCOTP) += nvmem-mxs-ocotp.o
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nvmem-mxs-ocotp-y := mxs-ocotp.o
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obj-$(CONFIG_QCOM_QFPROM) += nvmem_qfprom.o
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@ -0,0 +1,330 @@
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/*
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* NXP LPC18xx/LPC43xx EEPROM memory NVMEM driver
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*
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* Copyright (c) 2015 Ariel D'Alessandro <ariel@vanguardiasur.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*/
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/nvmem-provider.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/reset.h>
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/* Registers */
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#define LPC18XX_EEPROM_AUTOPROG 0x00c
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#define LPC18XX_EEPROM_AUTOPROG_WORD 0x1
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#define LPC18XX_EEPROM_CLKDIV 0x014
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#define LPC18XX_EEPROM_PWRDWN 0x018
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#define LPC18XX_EEPROM_PWRDWN_NO 0x0
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#define LPC18XX_EEPROM_PWRDWN_YES 0x1
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#define LPC18XX_EEPROM_INTSTAT 0xfe0
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#define LPC18XX_EEPROM_INTSTAT_END_OF_PROG BIT(2)
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#define LPC18XX_EEPROM_INTSTATCLR 0xfe8
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#define LPC18XX_EEPROM_INTSTATCLR_PROG_CLR_ST BIT(2)
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/* Fixed page size (bytes) */
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#define LPC18XX_EEPROM_PAGE_SIZE 0x80
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/* EEPROM device requires a ~1500 kHz clock (min 800 kHz, max 1600 kHz) */
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#define LPC18XX_EEPROM_CLOCK_HZ 1500000
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/* EEPROM requires 3 ms of erase/program time between each writing */
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#define LPC18XX_EEPROM_PROGRAM_TIME 3
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struct lpc18xx_eeprom_dev {
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struct clk *clk;
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void __iomem *reg_base;
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void __iomem *mem_base;
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struct nvmem_device *nvmem;
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unsigned reg_bytes;
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unsigned val_bytes;
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};
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static struct regmap_config lpc18xx_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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};
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static inline void lpc18xx_eeprom_writel(struct lpc18xx_eeprom_dev *eeprom,
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u32 reg, u32 val)
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{
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writel(val, eeprom->reg_base + reg);
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}
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static inline u32 lpc18xx_eeprom_readl(struct lpc18xx_eeprom_dev *eeprom,
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u32 reg)
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{
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return readl(eeprom->reg_base + reg);
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}
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static int lpc18xx_eeprom_busywait_until_prog(struct lpc18xx_eeprom_dev *eeprom)
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{
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unsigned long end;
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u32 val;
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/* Wait until EEPROM program operation has finished */
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end = jiffies + msecs_to_jiffies(LPC18XX_EEPROM_PROGRAM_TIME * 10);
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while (time_is_after_jiffies(end)) {
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val = lpc18xx_eeprom_readl(eeprom, LPC18XX_EEPROM_INTSTAT);
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if (val & LPC18XX_EEPROM_INTSTAT_END_OF_PROG) {
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lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_INTSTATCLR,
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LPC18XX_EEPROM_INTSTATCLR_PROG_CLR_ST);
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return 0;
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}
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usleep_range(LPC18XX_EEPROM_PROGRAM_TIME * USEC_PER_MSEC,
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(LPC18XX_EEPROM_PROGRAM_TIME + 1) * USEC_PER_MSEC);
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}
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return -ETIMEDOUT;
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}
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static int lpc18xx_eeprom_gather_write(void *context, const void *reg,
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size_t reg_size, const void *val,
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size_t val_size)
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{
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struct lpc18xx_eeprom_dev *eeprom = context;
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unsigned int offset = *(u32 *)reg;
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int ret;
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if (offset % lpc18xx_regmap_config.reg_stride)
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return -EINVAL;
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lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_PWRDWN,
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LPC18XX_EEPROM_PWRDWN_NO);
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/* Wait 100 us while the EEPROM wakes up */
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usleep_range(100, 200);
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while (val_size) {
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writel(*(u32 *)val, eeprom->mem_base + offset);
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ret = lpc18xx_eeprom_busywait_until_prog(eeprom);
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if (ret < 0)
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return ret;
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val_size -= eeprom->val_bytes;
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val += eeprom->val_bytes;
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offset += eeprom->val_bytes;
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}
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lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_PWRDWN,
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LPC18XX_EEPROM_PWRDWN_YES);
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return 0;
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}
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static int lpc18xx_eeprom_write(void *context, const void *data, size_t count)
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{
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struct lpc18xx_eeprom_dev *eeprom = context;
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unsigned int offset = eeprom->reg_bytes;
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if (count <= offset)
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return -EINVAL;
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return lpc18xx_eeprom_gather_write(context, data, eeprom->reg_bytes,
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data + offset, count - offset);
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}
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static int lpc18xx_eeprom_read(void *context, const void *reg, size_t reg_size,
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void *val, size_t val_size)
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{
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struct lpc18xx_eeprom_dev *eeprom = context;
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unsigned int offset = *(u32 *)reg;
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lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_PWRDWN,
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LPC18XX_EEPROM_PWRDWN_NO);
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/* Wait 100 us while the EEPROM wakes up */
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usleep_range(100, 200);
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while (val_size) {
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*(u32 *)val = readl(eeprom->mem_base + offset);
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val_size -= eeprom->val_bytes;
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val += eeprom->val_bytes;
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offset += eeprom->val_bytes;
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}
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lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_PWRDWN,
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LPC18XX_EEPROM_PWRDWN_YES);
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return 0;
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}
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static struct regmap_bus lpc18xx_eeprom_bus = {
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.write = lpc18xx_eeprom_write,
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.gather_write = lpc18xx_eeprom_gather_write,
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.read = lpc18xx_eeprom_read,
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.reg_format_endian_default = REGMAP_ENDIAN_NATIVE,
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.val_format_endian_default = REGMAP_ENDIAN_NATIVE,
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};
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static bool lpc18xx_eeprom_writeable_reg(struct device *dev, unsigned int reg)
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{
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/*
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* The last page contains the EEPROM initialization data and is not
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* writable.
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*/
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return reg <= lpc18xx_regmap_config.max_register -
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LPC18XX_EEPROM_PAGE_SIZE;
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}
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static bool lpc18xx_eeprom_readable_reg(struct device *dev, unsigned int reg)
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{
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return reg <= lpc18xx_regmap_config.max_register;
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}
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static struct nvmem_config lpc18xx_nvmem_config = {
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.name = "lpc18xx-eeprom",
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.owner = THIS_MODULE,
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};
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static int lpc18xx_eeprom_probe(struct platform_device *pdev)
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{
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struct lpc18xx_eeprom_dev *eeprom;
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struct device *dev = &pdev->dev;
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struct reset_control *rst;
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unsigned long clk_rate;
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struct regmap *regmap;
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struct resource *res;
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int ret;
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eeprom = devm_kzalloc(dev, sizeof(*eeprom), GFP_KERNEL);
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if (!eeprom)
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return -ENOMEM;
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "reg");
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eeprom->reg_base = devm_ioremap_resource(dev, res);
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if (IS_ERR(eeprom->reg_base))
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return PTR_ERR(eeprom->reg_base);
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem");
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eeprom->mem_base = devm_ioremap_resource(dev, res);
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if (IS_ERR(eeprom->mem_base))
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return PTR_ERR(eeprom->mem_base);
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eeprom->clk = devm_clk_get(&pdev->dev, "eeprom");
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if (IS_ERR(eeprom->clk)) {
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dev_err(&pdev->dev, "failed to get eeprom clock\n");
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return PTR_ERR(eeprom->clk);
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}
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ret = clk_prepare_enable(eeprom->clk);
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if (ret < 0) {
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dev_err(dev, "failed to prepare/enable eeprom clk: %d\n", ret);
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return ret;
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}
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rst = devm_reset_control_get(dev, NULL);
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if (IS_ERR(rst)) {
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dev_err(dev, "failed to get reset: %ld\n", PTR_ERR(rst));
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ret = PTR_ERR(rst);
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goto err_clk;
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}
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ret = reset_control_assert(rst);
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if (ret < 0) {
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dev_err(dev, "failed to assert reset: %d\n", ret);
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goto err_clk;
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}
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eeprom->val_bytes = lpc18xx_regmap_config.val_bits / BITS_PER_BYTE;
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eeprom->reg_bytes = lpc18xx_regmap_config.reg_bits / BITS_PER_BYTE;
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/*
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* Clock rate is generated by dividing the system bus clock by the
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* division factor, contained in the divider register (minus 1 encoded).
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*/
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clk_rate = clk_get_rate(eeprom->clk);
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clk_rate = DIV_ROUND_UP(clk_rate, LPC18XX_EEPROM_CLOCK_HZ) - 1;
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lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_CLKDIV, clk_rate);
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/*
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* Writing a single word to the page will start the erase/program cycle
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* automatically
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*/
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lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_AUTOPROG,
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LPC18XX_EEPROM_AUTOPROG_WORD);
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lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_PWRDWN,
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LPC18XX_EEPROM_PWRDWN_YES);
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lpc18xx_regmap_config.max_register = resource_size(res) - 1;
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lpc18xx_regmap_config.writeable_reg = lpc18xx_eeprom_writeable_reg;
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lpc18xx_regmap_config.readable_reg = lpc18xx_eeprom_readable_reg;
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regmap = devm_regmap_init(dev, &lpc18xx_eeprom_bus, eeprom,
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&lpc18xx_regmap_config);
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if (IS_ERR(regmap)) {
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dev_err(dev, "regmap init failed: %ld\n", PTR_ERR(regmap));
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ret = PTR_ERR(regmap);
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goto err_clk;
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}
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lpc18xx_nvmem_config.dev = dev;
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eeprom->nvmem = nvmem_register(&lpc18xx_nvmem_config);
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if (IS_ERR(eeprom->nvmem)) {
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ret = PTR_ERR(eeprom->nvmem);
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goto err_clk;
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}
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platform_set_drvdata(pdev, eeprom);
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return 0;
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err_clk:
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clk_disable_unprepare(eeprom->clk);
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return ret;
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}
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static int lpc18xx_eeprom_remove(struct platform_device *pdev)
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{
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struct lpc18xx_eeprom_dev *eeprom = platform_get_drvdata(pdev);
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int ret;
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ret = nvmem_unregister(eeprom->nvmem);
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if (ret < 0)
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return ret;
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clk_disable_unprepare(eeprom->clk);
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return 0;
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}
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static const struct of_device_id lpc18xx_eeprom_of_match[] = {
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{ .compatible = "nxp,lpc1857-eeprom" },
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{ },
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};
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MODULE_DEVICE_TABLE(of, lpc18xx_eeprom_of_match);
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static struct platform_driver lpc18xx_eeprom_driver = {
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.probe = lpc18xx_eeprom_probe,
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.remove = lpc18xx_eeprom_remove,
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.driver = {
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.name = "lpc18xx-eeprom",
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.of_match_table = lpc18xx_eeprom_of_match,
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},
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};
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module_platform_driver(lpc18xx_eeprom_driver);
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MODULE_AUTHOR("Ariel D'Alessandro <ariel@vanguardiasur.com.ar>");
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MODULE_DESCRIPTION("NXP LPC18xx EEPROM memory Driver");
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MODULE_LICENSE("GPL v2");
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