Qualcomm ARM64 Updates for v4.18
* Add support for SDM845 and associated peripherals * Fix gic_irq_domain_translation warnings on Qualcomm platforms * Add binding for GENI SE, Qualcomm bluetooth, and Command DB * Add support for SDHCI and ramoops on MSM8992 * Fixup qcom,pcie devices to pcie * Add wlan, bluetooth, and micro SD supplies on db820c * Add UFS related nodes on MSM8996 -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJbBO5XAAoJEFKiBbHx2RXVepsP/RLrHukvzg4uAg1jrmhoE0W8 DKdjwwXHC4gZwi7PQuB4RVMXiJKKGU83d4NjVCw54ZokkWr+Lh3wkzRr3JZLMrTM BCJO8PXMs5ScXqpWg78mBE/N2BUoL/V6A9wZZpi0Nfg+qUzMSPvkLq5ddq8AZ23E +gQ2U8IK2ndn4AgUOSefoXNwjxhHA3nL+nfReMICHIAH6S+mmYDJCjh1Jo+v1ty3 AhPnaTKwdNBMceZlr1RcST7fnas82Tc0Vs+8gI4h5LCoDNkMCxm+0HEVN7RrTTCi e7Lxn36PJ2ebaY/BF9kuZbSFoevrKpq9syV4CUkmncWuIXLAxVNnLOfsWwbuHibR m1nXP6gXCkVA+RgugYrxP2RRPwKS0tVuqjiBprPOPrGd9awjME5qSUxrhtXQtFUS ++7EXxu/2fbQyub1M0xOPk0VWXuKLB4SaeY6OUxSAm/2wFJXFYm7BI3tBAEsSGQo +D98W0c85H5tuVk9Ga3EH13U0mWKT9iBxOJUlSA+0iad5N8nZ1aQj1MVyWFzsQ5s x3bKpO2PzvoeMNi3RaJl6L1liy6e1TiQpmfgRTsHQbhtD/XCw6duozlTQFWIPV2F XwTl2EsXXQbT1YKrGelOBTS3OKrzPhYDfhTUWr9sqJ5QFMXJuENEDFIWz4PvXDqt LwrkGlUGriES0LoUQdsz =pxUm -----END PGP SIGNATURE----- Merge tag 'qcom-arm64-for-4.18' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into next/dt Qualcomm ARM64 Updates for v4.18 * Add support for SDM845 and associated peripherals * Fix gic_irq_domain_translation warnings on Qualcomm platforms * Add binding for GENI SE, Qualcomm bluetooth, and Command DB * Add support for SDHCI and ramoops on MSM8992 * Fixup qcom,pcie devices to pcie * Add wlan, bluetooth, and micro SD supplies on db820c * Add UFS related nodes on MSM8996 * tag 'qcom-arm64-for-4.18' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux: arm64: dts: qcom: msm8996: Add ufs related nodes arm64: dts: msm8996: fix gic_irq_domain_translate warnings arm64: dts: qcom: sdm845: Sort nodes in the soc by address arm64: dts: qcom: sdm845: Sort nodes in the reserved mem by address arm64: dts: sdm845: Add command DB node arm64: dts: sdm845: Fix xo_board clock name and speed arm64: dts: qcom: Add SDM845 SMEM nodes arm64: dts: qcom: Add APSS shared mailbox node to SDM845 arm64: dts: msm8916: fix gic_irq_domain_translate warnings dt-bindings: introduce Command DB for QCOM SoCs arm64: dts: apq8096-db820c: Add micro sd card supplies dt-bindings: soc: qcom: Add device tree binding for GENI SE dt-bindings: net: bluetooth: Add qualcomm-bluetooth arm64: dts: apq8096-db820c: enable bluetooth node arm64: dts: apq8096-db820c: Enable wlan and bt en pins arm64: dts: qcom: rename qcom,pcie devices to pcie arm64: dts: msm8992: add pstore-ramoops support arm64: dts: sdm845: Add minimal dts/dtsi files for sdm845 SoC and MTP arm64: dts: Enable onboard SDHCI on msm8992 Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
efe5322843
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@ -0,0 +1,30 @@
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Qualcomm Bluetooth Chips
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||||||
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---------------------
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This documents the binding structure and common properties for serial
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attached Qualcomm devices.
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Serial attached Qualcomm devices shall be a child node of the host UART
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device the slave device is attached to.
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Required properties:
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- compatible: should contain one of the following:
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* "qcom,qca6174-bt"
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Optional properties:
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- enable-gpios: gpio specifier used to enable chip
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- clocks: clock provided to the controller (SUSCLK_32KHZ)
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Example:
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serial@7570000 {
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label = "BT-UART";
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status = "okay";
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bluetooth {
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compatible = "qcom,qca6174-bt";
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enable-gpios = <&pm8994_gpios 19 GPIO_ACTIVE_HIGH>;
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clocks = <&divclk4>;
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};
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};
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@ -0,0 +1,37 @@
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Command DB
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---------
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Command DB is a database that provides a mapping between resource key and the
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resource address for a system resource managed by a remote processor. The data
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is stored in a shared memory region and is loaded by the remote processor.
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Some of the Qualcomm Technologies Inc SoC's have hardware accelerators for
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controlling shared resources. Depending on the board configuration the shared
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resource properties may change. These properties are dynamically probed by the
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remote processor and made available in the shared memory.
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The bindings for Command DB is specified in the reserved-memory section in
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devicetree. The devicetree representation of the command DB driver should be:
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Properties:
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- compatible:
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Usage: required
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Value type: <string>
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Definition: Should be "qcom,cmd-db"
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- reg:
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Usage: required
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Value type: <prop encoded array>
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Definition: The register address that points to the actual location of
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the Command DB in memory.
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Example:
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reserved-memory {
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[...]
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reserved-memory@85fe0000 {
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reg = <0x0 0x85fe0000 0x0 0x20000>;
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compatible = "qcom,cmd-db";
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no-map;
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};
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};
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@ -0,0 +1,119 @@
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Qualcomm Technologies, Inc. GENI Serial Engine QUP Wrapper Controller
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Generic Interface (GENI) based Qualcomm Universal Peripheral (QUP) wrapper
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is a programmable module for supporting a wide range of serial interfaces
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like UART, SPI, I2C, I3C, etc. A single QUP module can provide upto 8 Serial
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Interfaces, using its internal Serial Engines. The GENI Serial Engine QUP
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Wrapper controller is modeled as a node with zero or more child nodes each
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representing a serial engine.
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Required properties:
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- compatible: Must be "qcom,geni-se-qup".
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- reg: Must contain QUP register address and length.
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- clock-names: Must contain "m-ahb" and "s-ahb".
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- clocks: AHB clocks needed by the device.
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Required properties if child node exists:
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- #address-cells: Must be <1> for Serial Engine Address
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- #size-cells: Must be <1> for Serial Engine Address Size
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- ranges: Must be present
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Properties for children:
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A GENI based QUP wrapper controller node can contain 0 or more child nodes
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representing serial devices. These serial devices can be a QCOM UART, I2C
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controller, SPI controller, or some combination of aforementioned devices.
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|
Please refer below the child node definitions for the supported serial
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interface protocols.
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Qualcomm Technologies Inc. GENI Serial Engine based I2C Controller
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Required properties:
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- compatible: Must be "qcom,geni-i2c".
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- reg: Must contain QUP register address and length.
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- interrupts: Must contain I2C interrupt.
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- clock-names: Must contain "se".
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- clocks: Serial engine core clock needed by the device.
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- #address-cells: Must be <1> for I2C device address.
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- #size-cells: Must be <0> as I2C addresses have no size component.
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Optional property:
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- clock-frequency: Desired I2C bus clock frequency in Hz.
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When missing default to 400000Hz.
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Child nodes should conform to I2C bus binding as described in i2c.txt.
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Qualcomm Technologies Inc. GENI Serial Engine based UART Controller
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Required properties:
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- compatible: Must be "qcom,geni-debug-uart".
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- reg: Must contain UART register location and length.
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- interrupts: Must contain UART core interrupts.
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- clock-names: Must contain "se".
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- clocks: Serial engine core clock needed by the device.
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Qualcomm Technologies Inc. GENI Serial Engine based SPI Controller
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Required properties:
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- compatible: Must contain "qcom,geni-spi".
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- reg: Must contain SPI register location and length.
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- interrupts: Must contain SPI controller interrupts.
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- clock-names: Must contain "se".
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- clocks: Serial engine core clock needed by the device.
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- spi-max-frequency: Specifies maximum SPI clock frequency, units - Hz.
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- #address-cells: Must be <1> to define a chip select address on
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the SPI bus.
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- #size-cells: Must be <0>.
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SPI slave nodes must be children of the SPI master node and conform to SPI bus
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binding as described in Documentation/devicetree/bindings/spi/spi-bus.txt.
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Example:
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geniqup@8c0000 {
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compatible = "qcom,geni-se-qup";
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reg = <0x8c0000 0x6000>;
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clock-names = "m-ahb", "s-ahb";
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clocks = <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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i2c0: i2c@a94000 {
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compatible = "qcom,geni-i2c";
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reg = <0xa94000 0x4000>;
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interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se";
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clocks = <&clock_gcc GCC_QUPV3_WRAP0_S5_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qup_1_i2c_5_active>;
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pinctrl-1 = <&qup_1_i2c_5_sleep>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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uart0: serial@a88000 {
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compatible = "qcom,geni-debug-uart";
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reg = <0xa88000 0x7000>;
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interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se";
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clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qup_1_uart_3_active>;
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pinctrl-1 = <&qup_1_uart_3_sleep>;
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};
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spi0: spi@a84000 {
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compatible = "qcom,geni-spi";
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reg = <0xa84000 0x4000>;
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interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se";
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clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qup_1_spi_2_active>;
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pinctrl-1 = <&qup_1_spi_2_sleep>;
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spi-max-frequency = <19200000>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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}
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@ -6,3 +6,4 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8992-bullhead-rev-101.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8992-bullhead-rev-101.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8994-angler-rev-101.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8994-angler-rev-101.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8996-mtp.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8996-mtp.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sdm845-mtp.dtb
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@ -36,4 +36,30 @@
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drive-strength = <2>; /* 2 MA */
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drive-strength = <2>; /* 2 MA */
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};
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};
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};
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};
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blsp1_uart1_default: blsp1_uart1_default {
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mux {
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pins = "gpio41", "gpio42", "gpio43", "gpio44";
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function = "blsp_uart2";
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};
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config {
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pins = "gpio41", "gpio42", "gpio43", "gpio44";
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drive-strength = <16>;
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bias-disable;
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};
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};
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blsp1_uart1_sleep: blsp1_uart1_sleep {
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mux {
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pins = "gpio41", "gpio42", "gpio43", "gpio44";
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function = "gpio";
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};
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config {
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pins = "gpio41", "gpio42", "gpio43", "gpio44";
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drive-strength = <2>;
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bias-disable;
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|
};
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|
};
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};
|
};
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|
|
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|
@ -14,6 +14,28 @@
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};
|
};
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};
|
};
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|
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|
bt_en_gpios: bt_en_gpios {
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pinconf {
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|
pins = "gpio19";
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|
function = PMIC_GPIO_FUNC_NORMAL;
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|
output-low;
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|
power-source = <PM8994_GPIO_S4>; // 1.8V
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qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
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|
bias-pull-down;
|
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|
};
|
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|
};
|
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|
|
||||||
|
wlan_en_gpios: wlan_en_gpios {
|
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|
pinconf {
|
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|
pins = "gpio8";
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|
function = PMIC_GPIO_FUNC_NORMAL;
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|
output-low;
|
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|
power-source = <PM8994_GPIO_S4>; // 1.8V
|
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|
qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
|
||||||
|
bias-pull-down;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
volume_up_gpio: pm8996_gpio2 {
|
volume_up_gpio: pm8996_gpio2 {
|
||||||
pinconf {
|
pinconf {
|
||||||
pins = "gpio2";
|
pins = "gpio2";
|
||||||
|
|
@ -26,6 +48,16 @@
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
|
divclk4_pin_a: divclk4 {
|
||||||
|
pinconf {
|
||||||
|
pins = "gpio18";
|
||||||
|
function = PMIC_GPIO_FUNC_FUNC2;
|
||||||
|
|
||||||
|
bias-disable;
|
||||||
|
power-source = <PM8994_GPIO_S4>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
usb3_vbus_det_gpio: pm8996_gpio22 {
|
usb3_vbus_det_gpio: pm8996_gpio22 {
|
||||||
pinconf {
|
pinconf {
|
||||||
pins = "gpio22";
|
pins = "gpio22";
|
||||||
|
|
|
||||||
|
|
@ -23,6 +23,7 @@
|
||||||
aliases {
|
aliases {
|
||||||
serial0 = &blsp2_uart1;
|
serial0 = &blsp2_uart1;
|
||||||
serial1 = &blsp2_uart2;
|
serial1 = &blsp2_uart2;
|
||||||
|
serial2 = &blsp1_uart1;
|
||||||
i2c0 = &blsp1_i2c2;
|
i2c0 = &blsp1_i2c2;
|
||||||
i2c1 = &blsp2_i2c1;
|
i2c1 = &blsp2_i2c1;
|
||||||
i2c2 = &blsp2_i2c0;
|
i2c2 = &blsp2_i2c0;
|
||||||
|
|
@ -34,7 +35,36 @@
|
||||||
stdout-path = "serial0:115200n8";
|
stdout-path = "serial0:115200n8";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
clocks {
|
||||||
|
divclk4: divclk4 {
|
||||||
|
compatible = "fixed-clock";
|
||||||
|
#clock-cells = <0>;
|
||||||
|
clock-frequency = <32768>;
|
||||||
|
clock-output-names = "divclk4";
|
||||||
|
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&divclk4_pin_a>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
soc {
|
soc {
|
||||||
|
serial@7570000 {
|
||||||
|
label = "BT-UART";
|
||||||
|
status = "okay";
|
||||||
|
pinctrl-names = "default", "sleep";
|
||||||
|
pinctrl-0 = <&blsp1_uart1_default>;
|
||||||
|
pinctrl-1 = <&blsp1_uart1_sleep>;
|
||||||
|
|
||||||
|
bluetooth {
|
||||||
|
compatible = "qcom,qca6174-bt";
|
||||||
|
|
||||||
|
/* bt_disable_n gpio */
|
||||||
|
enable-gpios = <&pm8994_gpios 19 GPIO_ACTIVE_HIGH>;
|
||||||
|
|
||||||
|
clocks = <&divclk4>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
serial@75b0000 {
|
serial@75b0000 {
|
||||||
label = "LS-UART1";
|
label = "LS-UART1";
|
||||||
status = "okay";
|
status = "okay";
|
||||||
|
|
@ -87,6 +117,16 @@
|
||||||
pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
|
pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
|
||||||
pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
|
pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
|
||||||
cd-gpios = <&msmgpio 38 0x1>;
|
cd-gpios = <&msmgpio 38 0x1>;
|
||||||
|
vmmc-supply = <&pm8994_l21>;
|
||||||
|
vqmmc-supply = <&pm8994_l13>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
phy@627000 {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
ufshc@624000 {
|
||||||
status = "okay";
|
status = "okay";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -139,17 +179,48 @@
|
||||||
pinctrl-0 = <&usb2_vbus_det_gpio>;
|
pinctrl-0 = <&usb2_vbus_det_gpio>;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
bt_en: bt-en-1-8v {
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&bt_en_gpios>;
|
||||||
|
compatible = "regulator-fixed";
|
||||||
|
regulator-name = "bt-en-regulator";
|
||||||
|
regulator-min-microvolt = <1800000>;
|
||||||
|
regulator-max-microvolt = <1800000>;
|
||||||
|
|
||||||
|
/* WLAN card specific delay */
|
||||||
|
startup-delay-us = <70000>;
|
||||||
|
enable-active-high;
|
||||||
|
};
|
||||||
|
|
||||||
|
wlan_en: wlan-en-1-8v {
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&wlan_en_gpios>;
|
||||||
|
compatible = "regulator-fixed";
|
||||||
|
regulator-name = "wlan-en-regulator";
|
||||||
|
regulator-min-microvolt = <1800000>;
|
||||||
|
regulator-max-microvolt = <1800000>;
|
||||||
|
|
||||||
|
gpio = <&pm8994_gpios 8 0>;
|
||||||
|
|
||||||
|
/* WLAN card specific delay */
|
||||||
|
startup-delay-us = <70000>;
|
||||||
|
enable-active-high;
|
||||||
|
};
|
||||||
|
|
||||||
agnoc@0 {
|
agnoc@0 {
|
||||||
qcom,pcie@600000 {
|
pcie@600000 {
|
||||||
|
status = "okay";
|
||||||
perst-gpio = <&msmgpio 35 GPIO_ACTIVE_LOW>;
|
perst-gpio = <&msmgpio 35 GPIO_ACTIVE_LOW>;
|
||||||
|
vddpe-supply = <&wlan_en>;
|
||||||
|
vddpe1-supply = <&bt_en>;
|
||||||
};
|
};
|
||||||
|
|
||||||
qcom,pcie@608000 {
|
pcie@608000 {
|
||||||
status = "okay";
|
status = "okay";
|
||||||
perst-gpio = <&msmgpio 130 GPIO_ACTIVE_LOW>;
|
perst-gpio = <&msmgpio 130 GPIO_ACTIVE_LOW>;
|
||||||
};
|
};
|
||||||
|
|
||||||
qcom,pcie@610000 {
|
pcie@610000 {
|
||||||
status = "okay";
|
status = "okay";
|
||||||
perst-gpio = <&msmgpio 114 GPIO_ACTIVE_LOW>;
|
perst-gpio = <&msmgpio 114 GPIO_ACTIVE_LOW>;
|
||||||
};
|
};
|
||||||
|
|
|
||||||
|
|
@ -179,7 +179,7 @@
|
||||||
|
|
||||||
pmu {
|
pmu {
|
||||||
compatible = "arm,cortex-a53-pmu";
|
compatible = "arm,cortex-a53-pmu";
|
||||||
interrupts = <GIC_PPI 7 GIC_CPU_MASK_SIMPLE(4)>;
|
interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4)| IRQ_TYPE_LEVEL_HIGH)>;
|
||||||
};
|
};
|
||||||
|
|
||||||
thermal-zones {
|
thermal-zones {
|
||||||
|
|
@ -512,7 +512,7 @@
|
||||||
blsp_i2c2: i2c@78b6000 {
|
blsp_i2c2: i2c@78b6000 {
|
||||||
compatible = "qcom,i2c-qup-v2.2.1";
|
compatible = "qcom,i2c-qup-v2.2.1";
|
||||||
reg = <0x078b6000 0x500>;
|
reg = <0x078b6000 0x500>;
|
||||||
interrupts = <GIC_SPI 96 0>;
|
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
|
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
|
||||||
<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
|
<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
|
||||||
clock-names = "iface", "core";
|
clock-names = "iface", "core";
|
||||||
|
|
@ -527,7 +527,7 @@
|
||||||
blsp_i2c4: i2c@78b8000 {
|
blsp_i2c4: i2c@78b8000 {
|
||||||
compatible = "qcom,i2c-qup-v2.2.1";
|
compatible = "qcom,i2c-qup-v2.2.1";
|
||||||
reg = <0x078b8000 0x500>;
|
reg = <0x078b8000 0x500>;
|
||||||
interrupts = <GIC_SPI 98 0>;
|
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
|
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
|
||||||
<&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
|
<&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
|
||||||
clock-names = "iface", "core";
|
clock-names = "iface", "core";
|
||||||
|
|
@ -542,7 +542,7 @@
|
||||||
blsp_i2c6: i2c@78ba000 {
|
blsp_i2c6: i2c@78ba000 {
|
||||||
compatible = "qcom,i2c-qup-v2.2.1";
|
compatible = "qcom,i2c-qup-v2.2.1";
|
||||||
reg = <0x078ba000 0x500>;
|
reg = <0x078ba000 0x500>;
|
||||||
interrupts = <GIC_SPI 100 0>;
|
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
|
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
|
||||||
<&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
|
<&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
|
||||||
clock-names = "iface", "core";
|
clock-names = "iface", "core";
|
||||||
|
|
@ -574,7 +574,7 @@
|
||||||
"mi2s-bit-clk3";
|
"mi2s-bit-clk3";
|
||||||
#sound-dai-cells = <1>;
|
#sound-dai-cells = <1>;
|
||||||
|
|
||||||
interrupts = <0 160 0>;
|
interrupts = <0 160 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
interrupt-names = "lpass-irq-lpaif";
|
interrupt-names = "lpass-irq-lpaif";
|
||||||
reg = <0x07708000 0x10000>;
|
reg = <0x07708000 0x10000>;
|
||||||
reg-names = "lpass-lpaif";
|
reg-names = "lpass-lpaif";
|
||||||
|
|
@ -594,7 +594,7 @@
|
||||||
reg = <0x07824900 0x11c>, <0x07824000 0x800>;
|
reg = <0x07824900 0x11c>, <0x07824000 0x800>;
|
||||||
reg-names = "hc_mem", "core_mem";
|
reg-names = "hc_mem", "core_mem";
|
||||||
|
|
||||||
interrupts = <0 123 0>, <0 138 0>;
|
interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>, <0 138 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
interrupt-names = "hc_irq", "pwr_irq";
|
interrupt-names = "hc_irq", "pwr_irq";
|
||||||
clocks = <&gcc GCC_SDCC1_APPS_CLK>,
|
clocks = <&gcc GCC_SDCC1_APPS_CLK>,
|
||||||
<&gcc GCC_SDCC1_AHB_CLK>,
|
<&gcc GCC_SDCC1_AHB_CLK>,
|
||||||
|
|
@ -611,7 +611,7 @@
|
||||||
reg = <0x07864900 0x11c>, <0x07864000 0x800>;
|
reg = <0x07864900 0x11c>, <0x07864000 0x800>;
|
||||||
reg-names = "hc_mem", "core_mem";
|
reg-names = "hc_mem", "core_mem";
|
||||||
|
|
||||||
interrupts = <0 125 0>, <0 221 0>;
|
interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>, <0 221 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
interrupt-names = "hc_irq", "pwr_irq";
|
interrupt-names = "hc_irq", "pwr_irq";
|
||||||
clocks = <&gcc GCC_SDCC2_APPS_CLK>,
|
clocks = <&gcc GCC_SDCC2_APPS_CLK>,
|
||||||
<&gcc GCC_SDCC2_AHB_CLK>,
|
<&gcc GCC_SDCC2_AHB_CLK>,
|
||||||
|
|
@ -818,7 +818,7 @@
|
||||||
iommu-ctx@2000 {
|
iommu-ctx@2000 {
|
||||||
compatible = "qcom,msm-iommu-v1-ns";
|
compatible = "qcom,msm-iommu-v1-ns";
|
||||||
reg = <0x2000 0x1000>;
|
reg = <0x2000 0x1000>;
|
||||||
interrupts = <GIC_SPI 242 0>;
|
interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -862,7 +862,7 @@
|
||||||
"bus_clk",
|
"bus_clk",
|
||||||
"vsync_clk";
|
"vsync_clk";
|
||||||
|
|
||||||
interrupts = <0 72 0>;
|
interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
|
||||||
interrupt-controller;
|
interrupt-controller;
|
||||||
#interrupt-cells = <1>;
|
#interrupt-cells = <1>;
|
||||||
|
|
|
||||||
|
|
@ -38,4 +38,21 @@
|
||||||
pinctrl-1 = <&blsp1_uart2_sleep>;
|
pinctrl-1 = <&blsp1_uart2_sleep>;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
|
reserved-memory {
|
||||||
|
#address-cells = <2>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
ranges;
|
||||||
|
|
||||||
|
ramoops@1ff00000 {
|
||||||
|
compatible = "ramoops";
|
||||||
|
reg = <0x0 0x1ff00000 0x0 0x40000>;
|
||||||
|
console-size = <0x10000>;
|
||||||
|
record-size = <0x10000>;
|
||||||
|
ftrace-size = <0x10000>;
|
||||||
|
pmsg-size = <0x20000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
|
#include "msm8994-smd-rpm.dtsi"
|
||||||
|
|
|
||||||
|
|
@ -35,4 +35,64 @@
|
||||||
bias-pull-down;
|
bias-pull-down;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
|
/* 0-3 for sdc1 4-6 for sdc2 */
|
||||||
|
/* Order of pins */
|
||||||
|
/* SDC1: CLK -> 0, CMD -> 1, DATA -> 2, RCLK -> 3 */
|
||||||
|
/* SDC2: CLK -> 4, CMD -> 5, DATA -> 6 */
|
||||||
|
sdc1_clk_on: clk-on {
|
||||||
|
pinconf {
|
||||||
|
pins = "sdc1_clk";
|
||||||
|
bias-disable = <0>; /* No pull */
|
||||||
|
drive-strength = <16>; /* 16mA */
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
sdc1_clk_off: clk-off {
|
||||||
|
pinconf {
|
||||||
|
pins = "sdc1_clk";
|
||||||
|
bias-disable = <0>; /* No pull */
|
||||||
|
drive-strength = <2>; /* 2mA */
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
sdc1_cmd_on: cmd-on {
|
||||||
|
pinconf {
|
||||||
|
pins = "sdc1_cmd";
|
||||||
|
bias-pull-up;
|
||||||
|
drive-strength = <8>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
sdc1_cmd_off: cmd-off {
|
||||||
|
pinconf {
|
||||||
|
pins = "sdc1_cmd";
|
||||||
|
bias-pull-up = <0x3>; /* same as 3.10 ?? */
|
||||||
|
drive-strength = <2>; /* 2mA */
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
sdc1_data_on: data-on {
|
||||||
|
pinconf {
|
||||||
|
pins = "sdc1_data";
|
||||||
|
bias-pull-up;
|
||||||
|
drive-strength = <8>; /* 8mA */
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
sdc1_data_off: data-off {
|
||||||
|
pinconf {
|
||||||
|
pins = "sdc1_data";
|
||||||
|
bias-pull-up;
|
||||||
|
drive-strength = <2>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
sdc1_rclk_on: rclk-on {
|
||||||
|
bias-pull-down; /* pull down */
|
||||||
|
};
|
||||||
|
|
||||||
|
sdc1_rclk_off: rclk-off {
|
||||||
|
bias-pull-down; /* pull down */
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
|
||||||
|
|
@ -202,6 +202,31 @@
|
||||||
reg = <0xfc400000 0x2000>;
|
reg = <0xfc400000 0x2000>;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
sdhci1: mmc@f9824900 {
|
||||||
|
compatible = "qcom,sdhci-msm-v4";
|
||||||
|
reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>;
|
||||||
|
reg-names = "hc_mem", "core_mem";
|
||||||
|
|
||||||
|
interrupts = <GIC_SPI 123 IRQ_TYPE_NONE>,
|
||||||
|
<GIC_SPI 138 IRQ_TYPE_NONE>;
|
||||||
|
interrupt-names = "hc_irq", "pwr_irq";
|
||||||
|
|
||||||
|
clocks = <&clock_gcc GCC_SDCC1_APPS_CLK>,
|
||||||
|
<&clock_gcc GCC_SDCC1_AHB_CLK>;
|
||||||
|
clock-names = "core", "iface";
|
||||||
|
|
||||||
|
pinctrl-names = "default", "sleep";
|
||||||
|
pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on
|
||||||
|
&sdc1_rclk_on>;
|
||||||
|
pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off
|
||||||
|
&sdc1_rclk_off>;
|
||||||
|
|
||||||
|
regulator-always-on;
|
||||||
|
bus-width = <8>;
|
||||||
|
mmc-hs400-1_8v;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
rpm_msg_ram: memory@fc428000 {
|
rpm_msg_ram: memory@fc428000 {
|
||||||
compatible = "qcom,rpm-msg-ram";
|
compatible = "qcom,rpm-msg-ram";
|
||||||
reg = <0xfc428000 0x4000>;
|
reg = <0xfc428000 0x4000>;
|
||||||
|
|
@ -231,7 +256,67 @@
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
|
smd_rpm: smd {
|
||||||
|
compatible = "qcom,smd";
|
||||||
|
rpm {
|
||||||
|
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
|
||||||
|
qcom,ipc = <&apcs 8 0>;
|
||||||
|
qcom,smd-edge = <15>;
|
||||||
|
qcom,local-pid = <0>;
|
||||||
|
qcom,remote-pid = <6>;
|
||||||
|
|
||||||
|
rpm-requests {
|
||||||
|
compatible = "qcom,rpm-msm8994";
|
||||||
|
qcom,smd-channels = "rpm_requests";
|
||||||
|
|
||||||
|
pm8994-regulators {
|
||||||
|
compatible = "qcom,rpm-pm8994-regulators";
|
||||||
|
|
||||||
|
pm8994_s1: s1 {};
|
||||||
|
pm8994_s2: s2 {};
|
||||||
|
pm8994_s3: s3 {};
|
||||||
|
pm8994_s4: s4 {};
|
||||||
|
pm8994_s5: s5 {};
|
||||||
|
pm8994_s6: s6 {};
|
||||||
|
pm8994_s7: s7 {};
|
||||||
|
|
||||||
|
pm8994_l1: l1 {};
|
||||||
|
pm8994_l2: l2 {};
|
||||||
|
pm8994_l3: l3 {};
|
||||||
|
pm8994_l4: l4 {};
|
||||||
|
pm8994_l6: l6 {};
|
||||||
|
pm8994_l8: l8 {};
|
||||||
|
pm8994_l9: l9 {};
|
||||||
|
pm8994_l10: l10 {};
|
||||||
|
pm8994_l11: l11 {};
|
||||||
|
pm8994_l12: l12 {};
|
||||||
|
pm8994_l13: l13 {};
|
||||||
|
pm8994_l14: l14 {};
|
||||||
|
pm8994_l15: l15 {};
|
||||||
|
pm8994_l16: l16 {};
|
||||||
|
pm8994_l17: l17 {};
|
||||||
|
pm8994_l18: l18 {};
|
||||||
|
pm8994_l19: l19 {};
|
||||||
|
pm8994_l20: l20 {};
|
||||||
|
pm8994_l21: l21 {};
|
||||||
|
pm8994_l22: l22 {};
|
||||||
|
pm8994_l23: l23 {};
|
||||||
|
pm8994_l24: l24 {};
|
||||||
|
pm8994_l25: l25 {};
|
||||||
|
pm8994_l26: l26 {};
|
||||||
|
pm8994_l27: l27 {};
|
||||||
|
pm8994_l28: l28 {};
|
||||||
|
pm8994_l29: l29 {};
|
||||||
|
pm8994_l30: l30 {};
|
||||||
|
pm8994_l31: l31 {};
|
||||||
|
pm8994_l32: l32 {};
|
||||||
|
|
||||||
|
pm8994_lvs1: lvs1 {};
|
||||||
|
pm8994_lvs2: lvs2 {};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
||||||
#include "msm8992-pins.dtsi"
|
#include "msm8992-pins.dtsi"
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,276 @@
|
||||||
|
/* Copyright (c) 2015, LGE Inc. All rights reserved.
|
||||||
|
* Copyright (c) 2016, The Linux Foundation. All rights reserved.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License version 2 and
|
||||||
|
* only version 2 as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*/
|
||||||
|
|
||||||
|
&smd_rpm {
|
||||||
|
rpm {
|
||||||
|
rpm_requests {
|
||||||
|
pm8994-regulators {
|
||||||
|
|
||||||
|
vdd_l1-supply = <&pm8994_s1>;
|
||||||
|
vdd_l2_26_28-supply = <&pm8994_s3>;
|
||||||
|
vdd_l3_11-supply = <&pm8994_s3>;
|
||||||
|
vdd_l4_27_31-supply = <&pm8994_s3>;
|
||||||
|
vdd_l5_7-supply = <&pm8994_s3>;
|
||||||
|
vdd_l6_12_32-supply = <&pm8994_s5>;
|
||||||
|
vdd_l8_16_30-supply = <&vreg_vph_pwr>;
|
||||||
|
vdd_l9_10_18_22-supply = <&vreg_vph_pwr>;
|
||||||
|
vdd_l13_19_23_24-supply = <&vreg_vph_pwr>;
|
||||||
|
vdd_l14_15-supply = <&pm8994_s5>;
|
||||||
|
vdd_l17_29-supply = <&vreg_vph_pwr>;
|
||||||
|
vdd_l20_21-supply = <&vreg_vph_pwr>;
|
||||||
|
vdd_l25-supply = <&pm8994_s5>;
|
||||||
|
vdd_lvs1_2 = <&pm8994_s4>;
|
||||||
|
|
||||||
|
s1 {
|
||||||
|
regulator-min-microvolt = <800000>;
|
||||||
|
regulator-max-microvolt = <800000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
s2 {
|
||||||
|
/* TODO */
|
||||||
|
};
|
||||||
|
|
||||||
|
s3 {
|
||||||
|
regulator-min-microvolt = <1300000>;
|
||||||
|
regulator-max-microvolt = <1300000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
s4 {
|
||||||
|
regulator-min-microvolt = <1800000>;
|
||||||
|
regulator-max-microvolt = <1800000>;
|
||||||
|
regulator-allow-set-load;
|
||||||
|
regulator-system-load = <325000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
s5 {
|
||||||
|
regulator-min-microvolt = <2150000>;
|
||||||
|
regulator-max-microvolt = <2150000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
s7 {
|
||||||
|
regulator-min-microvolt = <1000000>;
|
||||||
|
regulator-max-microvolt = <1000000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
l1 {
|
||||||
|
regulator-min-microvolt = <1000000>;
|
||||||
|
regulator-max-microvolt = <1000000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
l2 {
|
||||||
|
regulator-min-microvolt = <1250000>;
|
||||||
|
regulator-max-microvolt = <1250000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
l3 {
|
||||||
|
regulator-min-microvolt = <1200000>;
|
||||||
|
regulator-max-microvolt = <1200000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
l4 {
|
||||||
|
regulator-min-microvolt = <1225000>;
|
||||||
|
regulator-max-microvolt = <1225000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
l5 {
|
||||||
|
/* TODO */
|
||||||
|
};
|
||||||
|
|
||||||
|
l6 {
|
||||||
|
regulator-min-microvolt = <1800000>;
|
||||||
|
regulator-max-microvolt = <1800000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
l7 {
|
||||||
|
/* TODO */
|
||||||
|
};
|
||||||
|
|
||||||
|
l8 {
|
||||||
|
regulator-min-microvolt = <1800000>;
|
||||||
|
regulator-max-microvolt = <1800000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
l9 {
|
||||||
|
regulator-min-microvolt = <1800000>;
|
||||||
|
regulator-max-microvolt = <1800000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
l10 {
|
||||||
|
regulator-min-microvolt = <1800000>;
|
||||||
|
regulator-max-microvolt = <1800000>;
|
||||||
|
qcom,init-voltage = <1800000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
l11 {
|
||||||
|
regulator-min-microvolt = <1200000>;
|
||||||
|
regulator-max-microvolt = <1200000>;
|
||||||
|
qcom,init-voltage = <1200000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
l12 {
|
||||||
|
regulator-min-microvolt = <1800000>;
|
||||||
|
regulator-max-microvolt = <1800000>;
|
||||||
|
qcom,init-voltage = <1800000>;
|
||||||
|
proxy-supply = <&pm8994_l12>;
|
||||||
|
qcom,proxy-consumer-enable;
|
||||||
|
qcom,proxy-consumer-current = <10000>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
l13 {
|
||||||
|
regulator-min-microvolt = <1800000>;
|
||||||
|
regulator-max-microvolt = <2950000>;
|
||||||
|
qcom,init-voltage = <2950000>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
l14 {
|
||||||
|
regulator-min-microvolt = <1200000>;
|
||||||
|
regulator-max-microvolt = <1200000>;
|
||||||
|
qcom,init-voltage = <1200000>;
|
||||||
|
proxy-supply = <&pm8994_l14>;
|
||||||
|
qcom,proxy-consumer-enable;
|
||||||
|
qcom,proxy-consumer-current = <10000>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
l15 {
|
||||||
|
regulator-min-microvolt = <1800000>;
|
||||||
|
regulator-max-microvolt = <1800000>;
|
||||||
|
qcom,init-voltage = <1800000>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
l16 {
|
||||||
|
regulator-min-microvolt = <2700000>;
|
||||||
|
regulator-max-microvolt = <2700000>;
|
||||||
|
qcom,init-voltage = <2700000>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
l17 {
|
||||||
|
regulator-min-microvolt = <2700000>;
|
||||||
|
regulator-max-microvolt = <2700000>;
|
||||||
|
qcom,init-voltage = <2700000>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
l18 {
|
||||||
|
regulator-min-microvolt = <3000000>;
|
||||||
|
regulator-max-microvolt = <3000000>;
|
||||||
|
regulator-always-on;
|
||||||
|
qcom,init-voltage = <3000000>;
|
||||||
|
qcom,init-ldo-mode = <1>;
|
||||||
|
};
|
||||||
|
|
||||||
|
l19 {
|
||||||
|
regulator-min-microvolt = <1800000>;
|
||||||
|
regulator-max-microvolt = <1800000>;
|
||||||
|
qcom,init-voltage = <1800000>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
l20 {
|
||||||
|
regulator-min-microvolt = <2950000>;
|
||||||
|
regulator-max-microvolt = <2950000>;
|
||||||
|
regulator-always-on;
|
||||||
|
regulator-boot-on;
|
||||||
|
regulator-allow-set-load;
|
||||||
|
regulator-system-load = <570000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
l21 {
|
||||||
|
regulator-min-microvolt = <1800000>;
|
||||||
|
regulator-max-microvolt = <1800000>;
|
||||||
|
regulator-always-on;
|
||||||
|
qcom,init-voltage = <1800000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
l22 {
|
||||||
|
regulator-min-microvolt = <3100000>;
|
||||||
|
regulator-max-microvolt = <3100000>;
|
||||||
|
qcom,init-voltage = <3100000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
l23 {
|
||||||
|
regulator-min-microvolt = <2800000>;
|
||||||
|
regulator-max-microvolt = <2800000>;
|
||||||
|
qcom,init-voltage = <2800000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
l24 {
|
||||||
|
regulator-min-microvolt = <3075000>;
|
||||||
|
regulator-max-microvolt = <3150000>;
|
||||||
|
qcom,init-voltage = <3075000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
l25 {
|
||||||
|
regulator-min-microvolt = <1800000>;
|
||||||
|
regulator-max-microvolt = <1800000>;
|
||||||
|
qcom,init-voltage = <1800000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
l26 {
|
||||||
|
/* TODO: value from downstream
|
||||||
|
regulator-min-microvolt = <987500>;
|
||||||
|
fails to apply */
|
||||||
|
};
|
||||||
|
|
||||||
|
l27 {
|
||||||
|
regulator-min-microvolt = <1050000>;
|
||||||
|
regulator-max-microvolt = <1050000>;
|
||||||
|
qcom,init-voltage = <1050000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
l28 {
|
||||||
|
regulator-min-microvolt = <1000000>;
|
||||||
|
regulator-max-microvolt = <1000000>;
|
||||||
|
qcom,init-voltage = <1000000>;
|
||||||
|
proxy-supply = <&pm8994_l28>;
|
||||||
|
qcom,proxy-consumer-enable;
|
||||||
|
qcom,proxy-consumer-current = <10000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
l29 {
|
||||||
|
/* TODO: Unsupported voltage range.
|
||||||
|
regulator-min-microvolt = <2800000>;
|
||||||
|
regulator-max-microvolt = <2800000>;
|
||||||
|
qcom,init-voltage = <2800000>;
|
||||||
|
*/
|
||||||
|
};
|
||||||
|
|
||||||
|
l30 {
|
||||||
|
/* TODO: get this verified
|
||||||
|
regulator-min-microvolt = <1800000>;
|
||||||
|
regulator-max-microvolt = <1800000>;
|
||||||
|
qcom,init-voltage = <1800000>;
|
||||||
|
*/
|
||||||
|
};
|
||||||
|
|
||||||
|
l31 {
|
||||||
|
regulator-min-microvolt = <1262500>;
|
||||||
|
regulator-max-microvolt = <1262500>;
|
||||||
|
qcom,init-voltage = <1262500>;
|
||||||
|
};
|
||||||
|
|
||||||
|
l32 {
|
||||||
|
/* TODO: get this verified
|
||||||
|
regulator-min-microvolt = <1800000>;
|
||||||
|
regulator-max-microvolt = <1800000>;
|
||||||
|
qcom,init-voltage = <1800000>;
|
||||||
|
*/
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
@ -419,6 +419,16 @@
|
||||||
#clock-cells = <1>;
|
#clock-cells = <1>;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
blsp1_uart1: serial@7570000 {
|
||||||
|
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
|
||||||
|
reg = <0x07570000 0x1000>;
|
||||||
|
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
|
||||||
|
<&gcc GCC_BLSP1_AHB_CLK>;
|
||||||
|
clock-names = "core", "iface";
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
blsp1_spi0: spi@7575000 {
|
blsp1_spi0: spi@7575000 {
|
||||||
compatible = "qcom,spi-qup-v2.2.1";
|
compatible = "qcom,spi-qup-v2.2.1";
|
||||||
reg = <0x07575000 0x600>;
|
reg = <0x07575000 0x600>;
|
||||||
|
|
@ -437,7 +447,7 @@
|
||||||
blsp2_i2c0: i2c@75b5000 {
|
blsp2_i2c0: i2c@75b5000 {
|
||||||
compatible = "qcom,i2c-qup-v2.2.1";
|
compatible = "qcom,i2c-qup-v2.2.1";
|
||||||
reg = <0x075b5000 0x1000>;
|
reg = <0x075b5000 0x1000>;
|
||||||
interrupts = <GIC_SPI 101 0>;
|
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
clocks = <&gcc GCC_BLSP2_AHB_CLK>,
|
clocks = <&gcc GCC_BLSP2_AHB_CLK>,
|
||||||
<&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
|
<&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
|
||||||
clock-names = "iface", "core";
|
clock-names = "iface", "core";
|
||||||
|
|
@ -468,7 +478,7 @@
|
||||||
blsp2_i2c1: i2c@75b6000 {
|
blsp2_i2c1: i2c@75b6000 {
|
||||||
compatible = "qcom,i2c-qup-v2.2.1";
|
compatible = "qcom,i2c-qup-v2.2.1";
|
||||||
reg = <0x075b6000 0x1000>;
|
reg = <0x075b6000 0x1000>;
|
||||||
interrupts = <GIC_SPI 102 0>;
|
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
clocks = <&gcc GCC_BLSP2_AHB_CLK>,
|
clocks = <&gcc GCC_BLSP2_AHB_CLK>,
|
||||||
<&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>;
|
<&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>;
|
||||||
clock-names = "iface", "core";
|
clock-names = "iface", "core";
|
||||||
|
|
@ -493,7 +503,7 @@
|
||||||
blsp1_i2c2: i2c@7577000 {
|
blsp1_i2c2: i2c@7577000 {
|
||||||
compatible = "qcom,i2c-qup-v2.2.1";
|
compatible = "qcom,i2c-qup-v2.2.1";
|
||||||
reg = <0x07577000 0x1000>;
|
reg = <0x07577000 0x1000>;
|
||||||
interrupts = <GIC_SPI 97 0>;
|
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
|
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
|
||||||
<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
|
<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
|
||||||
clock-names = "iface", "core";
|
clock-names = "iface", "core";
|
||||||
|
|
@ -526,7 +536,8 @@
|
||||||
reg = <0x74a4900 0x314>, <0x74a4000 0x800>;
|
reg = <0x74a4900 0x314>, <0x74a4000 0x800>;
|
||||||
reg-names = "hc_mem", "core_mem";
|
reg-names = "hc_mem", "core_mem";
|
||||||
|
|
||||||
interrupts = <0 125 0>, <0 221 0>;
|
interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<0 221 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
interrupt-names = "hc_irq", "pwr_irq";
|
interrupt-names = "hc_irq", "pwr_irq";
|
||||||
|
|
||||||
clock-names = "iface", "core", "xo";
|
clock-names = "iface", "core", "xo";
|
||||||
|
|
@ -623,6 +634,91 @@
|
||||||
#interrupt-cells = <4>;
|
#interrupt-cells = <4>;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
ufsphy: phy@627000 {
|
||||||
|
compatible = "qcom,msm8996-ufs-phy-qmp-14nm";
|
||||||
|
reg = <0x627000 0xda8>;
|
||||||
|
reg-names = "phy_mem";
|
||||||
|
#phy-cells = <0>;
|
||||||
|
|
||||||
|
vdda-phy-supply = <&pm8994_l28>;
|
||||||
|
vdda-pll-supply = <&pm8994_l12>;
|
||||||
|
|
||||||
|
vdda-phy-max-microamp = <18380>;
|
||||||
|
vdda-pll-max-microamp = <9440>;
|
||||||
|
|
||||||
|
vddp-ref-clk-supply = <&pm8994_l25>;
|
||||||
|
vddp-ref-clk-max-microamp = <100>;
|
||||||
|
vddp-ref-clk-always-on;
|
||||||
|
|
||||||
|
clock-names = "ref_clk_src", "ref_clk";
|
||||||
|
clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,
|
||||||
|
<&gcc GCC_UFS_CLKREF_CLK>;
|
||||||
|
status = "disabled";
|
||||||
|
|
||||||
|
power-domains = <&gcc UFS_GDSC>;
|
||||||
|
};
|
||||||
|
|
||||||
|
ufshc@624000 {
|
||||||
|
compatible = "qcom,ufshc";
|
||||||
|
reg = <0x624000 0x2500>;
|
||||||
|
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
|
||||||
|
phys = <&ufsphy>;
|
||||||
|
phy-names = "ufsphy";
|
||||||
|
|
||||||
|
vcc-supply = <&pm8994_l20>;
|
||||||
|
vccq-supply = <&pm8994_l25>;
|
||||||
|
vccq2-supply = <&pm8994_s4>;
|
||||||
|
|
||||||
|
vcc-max-microamp = <600000>;
|
||||||
|
vccq-max-microamp = <450000>;
|
||||||
|
vccq2-max-microamp = <450000>;
|
||||||
|
|
||||||
|
clock-names =
|
||||||
|
"core_clk_src",
|
||||||
|
"core_clk",
|
||||||
|
"bus_clk",
|
||||||
|
"bus_aggr_clk",
|
||||||
|
"iface_clk",
|
||||||
|
"core_clk_unipro_src",
|
||||||
|
"core_clk_unipro",
|
||||||
|
"core_clk_ice",
|
||||||
|
"ref_clk",
|
||||||
|
"tx_lane0_sync_clk",
|
||||||
|
"rx_lane0_sync_clk";
|
||||||
|
clocks =
|
||||||
|
<&gcc UFS_AXI_CLK_SRC>,
|
||||||
|
<&gcc GCC_UFS_AXI_CLK>,
|
||||||
|
<&gcc GCC_SYS_NOC_UFS_AXI_CLK>,
|
||||||
|
<&gcc GCC_AGGRE2_UFS_AXI_CLK>,
|
||||||
|
<&gcc GCC_UFS_AHB_CLK>,
|
||||||
|
<&gcc UFS_ICE_CORE_CLK_SRC>,
|
||||||
|
<&gcc GCC_UFS_UNIPRO_CORE_CLK>,
|
||||||
|
<&gcc GCC_UFS_ICE_CORE_CLK>,
|
||||||
|
<&rpmcc RPM_SMD_LN_BB_CLK>,
|
||||||
|
<&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
|
||||||
|
<&gcc GCC_UFS_RX_SYMBOL_0_CLK>;
|
||||||
|
freq-table-hz =
|
||||||
|
<100000000 200000000>,
|
||||||
|
<0 0>,
|
||||||
|
<0 0>,
|
||||||
|
<0 0>,
|
||||||
|
<0 0>,
|
||||||
|
<150000000 300000000>,
|
||||||
|
<0 0>,
|
||||||
|
<0 0>,
|
||||||
|
<0 0>,
|
||||||
|
<0 0>,
|
||||||
|
<0 0>;
|
||||||
|
|
||||||
|
lanes-per-direction = <1>;
|
||||||
|
status = "disabled";
|
||||||
|
|
||||||
|
ufs_variant {
|
||||||
|
compatible = "qcom,ufs_variant";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
mmcc: clock-controller@8c0000 {
|
mmcc: clock-controller@8c0000 {
|
||||||
compatible = "qcom,mmcc-msm8996";
|
compatible = "qcom,mmcc-msm8996";
|
||||||
#clock-cells = <1>;
|
#clock-cells = <1>;
|
||||||
|
|
@ -809,7 +905,7 @@
|
||||||
dwc3@7600000 {
|
dwc3@7600000 {
|
||||||
compatible = "snps,dwc3";
|
compatible = "snps,dwc3";
|
||||||
reg = <0x7600000 0xcc00>;
|
reg = <0x7600000 0xcc00>;
|
||||||
interrupts = <0 138 0>;
|
interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
phys = <&hsusb_phy2>;
|
phys = <&hsusb_phy2>;
|
||||||
phy-names = "usb2-phy";
|
phy-names = "usb2-phy";
|
||||||
};
|
};
|
||||||
|
|
@ -838,7 +934,7 @@
|
||||||
dwc3@6a00000 {
|
dwc3@6a00000 {
|
||||||
compatible = "snps,dwc3";
|
compatible = "snps,dwc3";
|
||||||
reg = <0x6a00000 0xcc00>;
|
reg = <0x6a00000 0xcc00>;
|
||||||
interrupts = <0 131 0>;
|
interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
phys = <&hsusb_phy1>, <&ssusb_phy_0>;
|
phys = <&hsusb_phy1>, <&ssusb_phy_0>;
|
||||||
phy-names = "usb2-phy", "usb3-phy";
|
phy-names = "usb2-phy", "usb3-phy";
|
||||||
};
|
};
|
||||||
|
|
@ -851,7 +947,7 @@
|
||||||
#size-cells = <1>;
|
#size-cells = <1>;
|
||||||
ranges;
|
ranges;
|
||||||
|
|
||||||
pcie0: qcom,pcie@600000 {
|
pcie0: pcie@600000 {
|
||||||
compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
|
compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
power-domains = <&gcc PCIE0_GDSC>;
|
power-domains = <&gcc PCIE0_GDSC>;
|
||||||
|
|
@ -872,7 +968,7 @@
|
||||||
ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>,
|
ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>,
|
||||||
<0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
|
<0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
|
||||||
|
|
||||||
interrupts = <GIC_SPI 405 IRQ_TYPE_NONE>;
|
interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
interrupt-names = "msi";
|
interrupt-names = "msi";
|
||||||
#interrupt-cells = <1>;
|
#interrupt-cells = <1>;
|
||||||
interrupt-map-mask = <0 0 0 0x7>;
|
interrupt-map-mask = <0 0 0 0x7>;
|
||||||
|
|
@ -904,7 +1000,7 @@
|
||||||
|
|
||||||
};
|
};
|
||||||
|
|
||||||
pcie1: qcom,pcie@608000 {
|
pcie1: pcie@608000 {
|
||||||
compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
|
compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
|
||||||
power-domains = <&gcc PCIE1_GDSC>;
|
power-domains = <&gcc PCIE1_GDSC>;
|
||||||
bus-range = <0x00 0xff>;
|
bus-range = <0x00 0xff>;
|
||||||
|
|
@ -927,7 +1023,7 @@
|
||||||
ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>,
|
ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>,
|
||||||
<0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>;
|
<0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>;
|
||||||
|
|
||||||
interrupts = <GIC_SPI 413 IRQ_TYPE_NONE>;
|
interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
interrupt-names = "msi";
|
interrupt-names = "msi";
|
||||||
#interrupt-cells = <1>;
|
#interrupt-cells = <1>;
|
||||||
interrupt-map-mask = <0 0 0 0x7>;
|
interrupt-map-mask = <0 0 0 0x7>;
|
||||||
|
|
@ -957,7 +1053,7 @@
|
||||||
"bus_slave";
|
"bus_slave";
|
||||||
};
|
};
|
||||||
|
|
||||||
pcie2: qcom,pcie@610000 {
|
pcie2: pcie@610000 {
|
||||||
compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
|
compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
|
||||||
power-domains = <&gcc PCIE2_GDSC>;
|
power-domains = <&gcc PCIE2_GDSC>;
|
||||||
bus-range = <0x00 0xff>;
|
bus-range = <0x00 0xff>;
|
||||||
|
|
@ -980,7 +1076,7 @@
|
||||||
|
|
||||||
device_type = "pci";
|
device_type = "pci";
|
||||||
|
|
||||||
interrupts = <GIC_SPI 421 IRQ_TYPE_NONE>;
|
interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
interrupt-names = "msi";
|
interrupt-names = "msi";
|
||||||
#interrupt-cells = <1>;
|
#interrupt-cells = <1>;
|
||||||
interrupt-map-mask = <0 0 0 0x7>;
|
interrupt-map-mask = <0 0 0 0x7>;
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,15 @@
|
||||||
|
// SPDX-License-Identifier: GPL-2.0
|
||||||
|
/*
|
||||||
|
* SDM845 MTP board device tree source
|
||||||
|
*
|
||||||
|
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
|
||||||
|
#include "sdm845.dtsi"
|
||||||
|
|
||||||
|
/ {
|
||||||
|
model = "Qualcomm Technologies, Inc. SDM845 MTP";
|
||||||
|
compatible = "qcom,sdm845-mtp";
|
||||||
|
};
|
||||||
|
|
@ -0,0 +1,327 @@
|
||||||
|
// SPDX-License-Identifier: GPL-2.0
|
||||||
|
/*
|
||||||
|
* SDM845 SoC device tree source
|
||||||
|
*
|
||||||
|
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||||
|
|
||||||
|
/ {
|
||||||
|
interrupt-parent = <&intc>;
|
||||||
|
|
||||||
|
#address-cells = <2>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
|
||||||
|
chosen { };
|
||||||
|
|
||||||
|
memory@80000000 {
|
||||||
|
device_type = "memory";
|
||||||
|
/* We expect the bootloader to fill in the size */
|
||||||
|
reg = <0 0x80000000 0 0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
reserved-memory {
|
||||||
|
#address-cells = <2>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
ranges;
|
||||||
|
|
||||||
|
memory@85fc0000 {
|
||||||
|
reg = <0 0x85fc0000 0 0x20000>;
|
||||||
|
no-map;
|
||||||
|
};
|
||||||
|
|
||||||
|
memory@85fe0000 {
|
||||||
|
compatible = "qcom,cmd-db";
|
||||||
|
reg = <0x0 0x85fe0000 0x0 0x20000>;
|
||||||
|
no-map;
|
||||||
|
};
|
||||||
|
|
||||||
|
smem_mem: memory@86000000 {
|
||||||
|
reg = <0x0 0x86000000 0x0 0x200000>;
|
||||||
|
no-map;
|
||||||
|
};
|
||||||
|
|
||||||
|
memory@86200000 {
|
||||||
|
reg = <0 0x86200000 0 0x2d00000>;
|
||||||
|
no-map;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
cpus {
|
||||||
|
#address-cells = <2>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
|
||||||
|
CPU0: cpu@0 {
|
||||||
|
device_type = "cpu";
|
||||||
|
compatible = "qcom,kryo385";
|
||||||
|
reg = <0x0 0x0>;
|
||||||
|
enable-method = "psci";
|
||||||
|
next-level-cache = <&L2_0>;
|
||||||
|
L2_0: l2-cache {
|
||||||
|
compatible = "cache";
|
||||||
|
next-level-cache = <&L3_0>;
|
||||||
|
L3_0: l3-cache {
|
||||||
|
compatible = "cache";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
CPU1: cpu@100 {
|
||||||
|
device_type = "cpu";
|
||||||
|
compatible = "qcom,kryo385";
|
||||||
|
reg = <0x0 0x100>;
|
||||||
|
enable-method = "psci";
|
||||||
|
next-level-cache = <&L2_100>;
|
||||||
|
L2_100: l2-cache {
|
||||||
|
compatible = "cache";
|
||||||
|
next-level-cache = <&L3_0>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
CPU2: cpu@200 {
|
||||||
|
device_type = "cpu";
|
||||||
|
compatible = "qcom,kryo385";
|
||||||
|
reg = <0x0 0x200>;
|
||||||
|
enable-method = "psci";
|
||||||
|
next-level-cache = <&L2_200>;
|
||||||
|
L2_200: l2-cache {
|
||||||
|
compatible = "cache";
|
||||||
|
next-level-cache = <&L3_0>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
CPU3: cpu@300 {
|
||||||
|
device_type = "cpu";
|
||||||
|
compatible = "qcom,kryo385";
|
||||||
|
reg = <0x0 0x300>;
|
||||||
|
enable-method = "psci";
|
||||||
|
next-level-cache = <&L2_300>;
|
||||||
|
L2_300: l2-cache {
|
||||||
|
compatible = "cache";
|
||||||
|
next-level-cache = <&L3_0>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
CPU4: cpu@400 {
|
||||||
|
device_type = "cpu";
|
||||||
|
compatible = "qcom,kryo385";
|
||||||
|
reg = <0x0 0x400>;
|
||||||
|
enable-method = "psci";
|
||||||
|
next-level-cache = <&L2_400>;
|
||||||
|
L2_400: l2-cache {
|
||||||
|
compatible = "cache";
|
||||||
|
next-level-cache = <&L3_0>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
CPU5: cpu@500 {
|
||||||
|
device_type = "cpu";
|
||||||
|
compatible = "qcom,kryo385";
|
||||||
|
reg = <0x0 0x500>;
|
||||||
|
enable-method = "psci";
|
||||||
|
next-level-cache = <&L2_500>;
|
||||||
|
L2_500: l2-cache {
|
||||||
|
compatible = "cache";
|
||||||
|
next-level-cache = <&L3_0>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
CPU6: cpu@600 {
|
||||||
|
device_type = "cpu";
|
||||||
|
compatible = "qcom,kryo385";
|
||||||
|
reg = <0x0 0x600>;
|
||||||
|
enable-method = "psci";
|
||||||
|
next-level-cache = <&L2_600>;
|
||||||
|
L2_600: l2-cache {
|
||||||
|
compatible = "cache";
|
||||||
|
next-level-cache = <&L3_0>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
CPU7: cpu@700 {
|
||||||
|
device_type = "cpu";
|
||||||
|
compatible = "qcom,kryo385";
|
||||||
|
reg = <0x0 0x700>;
|
||||||
|
enable-method = "psci";
|
||||||
|
next-level-cache = <&L2_700>;
|
||||||
|
L2_700: l2-cache {
|
||||||
|
compatible = "cache";
|
||||||
|
next-level-cache = <&L3_0>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
timer {
|
||||||
|
compatible = "arm,armv8-timer";
|
||||||
|
interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
|
||||||
|
<GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
|
||||||
|
<GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
|
||||||
|
<GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
|
||||||
|
};
|
||||||
|
|
||||||
|
clocks {
|
||||||
|
xo_board: xo-board {
|
||||||
|
compatible = "fixed-clock";
|
||||||
|
#clock-cells = <0>;
|
||||||
|
clock-frequency = <38400000>;
|
||||||
|
clock-output-names = "xo_board";
|
||||||
|
};
|
||||||
|
|
||||||
|
sleep_clk: sleep-clk {
|
||||||
|
compatible = "fixed-clock";
|
||||||
|
#clock-cells = <0>;
|
||||||
|
clock-frequency = <32764>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
tcsr_mutex: hwlock {
|
||||||
|
compatible = "qcom,tcsr-mutex";
|
||||||
|
syscon = <&tcsr_mutex_regs 0 0x1000>;
|
||||||
|
#hwlock-cells = <1>;
|
||||||
|
};
|
||||||
|
|
||||||
|
smem {
|
||||||
|
compatible = "qcom,smem";
|
||||||
|
memory-region = <&smem_mem>;
|
||||||
|
hwlocks = <&tcsr_mutex 3>;
|
||||||
|
};
|
||||||
|
|
||||||
|
psci {
|
||||||
|
compatible = "arm,psci-1.0";
|
||||||
|
method = "smc";
|
||||||
|
};
|
||||||
|
|
||||||
|
soc: soc {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
ranges = <0 0 0 0xffffffff>;
|
||||||
|
compatible = "simple-bus";
|
||||||
|
|
||||||
|
gcc: clock-controller@100000 {
|
||||||
|
compatible = "qcom,gcc-sdm845";
|
||||||
|
reg = <0x100000 0x1f0000>;
|
||||||
|
#clock-cells = <1>;
|
||||||
|
#reset-cells = <1>;
|
||||||
|
#power-domain-cells = <1>;
|
||||||
|
};
|
||||||
|
|
||||||
|
tcsr_mutex_regs: syscon@1f40000 {
|
||||||
|
compatible = "syscon";
|
||||||
|
reg = <0x1f40000 0x40000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
tlmm: pinctrl@3400000 {
|
||||||
|
compatible = "qcom,sdm845-pinctrl";
|
||||||
|
reg = <0x03400000 0xc00000>;
|
||||||
|
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
gpio-controller;
|
||||||
|
#gpio-cells = <2>;
|
||||||
|
interrupt-controller;
|
||||||
|
#interrupt-cells = <2>;
|
||||||
|
};
|
||||||
|
|
||||||
|
spmi_bus: spmi@c440000 {
|
||||||
|
compatible = "qcom,spmi-pmic-arb";
|
||||||
|
reg = <0xc440000 0x1100>,
|
||||||
|
<0xc600000 0x2000000>,
|
||||||
|
<0xe600000 0x100000>,
|
||||||
|
<0xe700000 0xa0000>,
|
||||||
|
<0xc40a000 0x26000>;
|
||||||
|
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
|
||||||
|
interrupt-names = "periph_irq";
|
||||||
|
interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
qcom,ee = <0>;
|
||||||
|
qcom,channel = <0>;
|
||||||
|
#address-cells = <2>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
interrupt-controller;
|
||||||
|
#interrupt-cells = <4>;
|
||||||
|
cell-index = <0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
apss_shared: mailbox@17990000 {
|
||||||
|
compatible = "qcom,sdm845-apss-shared";
|
||||||
|
reg = <0x17990000 0x1000>;
|
||||||
|
#mbox-cells = <1>;
|
||||||
|
};
|
||||||
|
|
||||||
|
intc: interrupt-controller@17a00000 {
|
||||||
|
compatible = "arm,gic-v3";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
ranges;
|
||||||
|
#interrupt-cells = <3>;
|
||||||
|
interrupt-controller;
|
||||||
|
reg = <0x17a00000 0x10000>, /* GICD */
|
||||||
|
<0x17a60000 0x100000>; /* GICR * 8 */
|
||||||
|
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
|
||||||
|
gic-its@17a40000 {
|
||||||
|
compatible = "arm,gic-v3-its";
|
||||||
|
msi-controller;
|
||||||
|
#msi-cells = <1>;
|
||||||
|
reg = <0x17a40000 0x20000>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
timer@17c90000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
ranges;
|
||||||
|
compatible = "arm,armv7-timer-mem";
|
||||||
|
reg = <0x17c90000 0x1000>;
|
||||||
|
|
||||||
|
frame@17ca0000 {
|
||||||
|
frame-number = <0>;
|
||||||
|
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
reg = <0x17ca0000 0x1000>,
|
||||||
|
<0x17cb0000 0x1000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
frame@17cc0000 {
|
||||||
|
frame-number = <1>;
|
||||||
|
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
reg = <0x17cc0000 0x1000>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
frame@17cd0000 {
|
||||||
|
frame-number = <2>;
|
||||||
|
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
reg = <0x17cd0000 0x1000>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
frame@17ce0000 {
|
||||||
|
frame-number = <3>;
|
||||||
|
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
reg = <0x17ce0000 0x1000>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
frame@17cf0000 {
|
||||||
|
frame-number = <4>;
|
||||||
|
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
reg = <0x17cf0000 0x1000>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
frame@17d00000 {
|
||||||
|
frame-number = <5>;
|
||||||
|
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
reg = <0x17d00000 0x1000>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
frame@17d10000 {
|
||||||
|
frame-number = <6>;
|
||||||
|
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
reg = <0x17d10000 0x1000>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
Loading…
Reference in New Issue