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MIPS: only register FTLBPar exception handler for supported models 

Previously ExcCode 16 is unconditionally treated as the FTLB parity
exception (FTLBPar), but in fact its semantic is implementation-
dependent. Looking at various manuals it seems the FTLBPar exception is
only present on some recent MIPS Technologies cores, so only register
the handler on these.

Fixes: 75b5b5e0a2 ("MIPS: Add support for FTLBs")
Reviewed-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: WANG Xuerui <git@xen0n.name>
Cc: Paul Burton <paulburton@kernel.org>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
This commit is contained in:
WANG Xuerui 2020-07-29 21:14:15 +08:00 committed by Thomas Bogendoerfer
parent 48f5dd56cf
commit efd1b4ad3d
4 changed files with 20 additions and 1 deletions
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4
arch/mips/include/asm/cpu-features.h
View File

@ -568,6 +568,10 @@
# define cpu_has_mac2008_only __opt(MIPS_CPU_MAC_2008_ONLY)
#endif
#ifndef cpu_has_ftlbparex
# define cpu_has_ftlbparex __opt(MIPS_CPU_FTLBPAREX)
#endif
#ifdef CONFIG_SMP
/*
* Some systems share FTLB RAMs between threads within a core (siblings in

1
arch/mips/include/asm/cpu.h
View File

@ -427,6 +427,7 @@ enum cpu_type_enum {
#define MIPS_CPU_MM_SYSAD BIT_ULL(58) /* CPU supports write-through SysAD Valid merge */
#define MIPS_CPU_MM_FULL BIT_ULL(59) /* CPU supports write-through full merge */
#define MIPS_CPU_MAC_2008_ONLY BIT_ULL(60) /* CPU Only support MAC2008 Fused multiply-add instruction */
#define MIPS_CPU_FTLBPAREX BIT_ULL(61) /* CPU has FTLB parity exception */
/*
* CPU ASE encodings

13
arch/mips/kernel/cpu-probe.c
View File

@ -1827,6 +1827,19 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
default:
break;
}
/* Recent MIPS cores use the implementation-dependent ExcCode 16 for
* cache/FTLB parity exceptions.
*/
switch (__get_cpu_type(c->cputype)) {
case CPU_PROAPTIV:
case CPU_P5600:
case CPU_P6600:
case CPU_I6400:
case CPU_I6500:
c->options |= MIPS_CPU_FTLBPAREX;
break;
}
}
static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)

3
arch/mips/kernel/traps.c
View File

@ -2454,7 +2454,8 @@ void __init trap_init(void)
if (cpu_has_fpu && !cpu_has_nofpuex)
set_except_vector(EXCCODE_FPE, handle_fpe);
set_except_vector(MIPS_EXCCODE_TLBPAR, handle_ftlb);
if (cpu_has_ftlbparex)
set_except_vector(MIPS_EXCCODE_TLBPAR, handle_ftlb);
if (cpu_has_rixiex) {
set_except_vector(EXCCODE_TLBRI, tlb_do_page_fault_0);