drm/radeon/dpm: update cac leakage table parsing for CI
Uses a different table format if the board supports EVV. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -956,10 +956,19 @@ int r600_parse_extended_power_table(struct radeon_device *rdev)
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return -ENOMEM;
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}
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for (i = 0; i < cac_table->ucNumEntries; i++) {
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rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc =
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le16_to_cpu(cac_table->entries[i].usVddc);
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rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage =
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le32_to_cpu(cac_table->entries[i].ulLeakageValue);
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if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
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rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1 =
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le16_to_cpu(cac_table->entries[i].usVddc1);
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rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2 =
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le16_to_cpu(cac_table->entries[i].usVddc2);
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rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3 =
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le16_to_cpu(cac_table->entries[i].usVddc3);
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} else {
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rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc =
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le16_to_cpu(cac_table->entries[i].usVddc);
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rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage =
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le32_to_cpu(cac_table->entries[i].ulLeakageValue);
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}
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}
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rdev->pm.dpm.dyn_state.cac_leakage_table.count = cac_table->ucNumEntries;
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}
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@ -1256,14 +1256,21 @@ struct radeon_clock_voltage_dependency_table {
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struct radeon_clock_voltage_dependency_entry *entries;
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};
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struct radeon_cac_leakage_entry {
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u16 vddc;
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u32 leakage;
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union radeon_cac_leakage_entry {
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struct {
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u16 vddc;
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u32 leakage;
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};
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struct {
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u16 vddc1;
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u16 vddc2;
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u16 vddc3;
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};
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};
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struct radeon_cac_leakage_table {
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u32 count;
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struct radeon_cac_leakage_entry *entries;
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union radeon_cac_leakage_entry *entries;
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};
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struct radeon_phase_shedding_limits_entry {
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