ARM: sun6i: dt: Add support for the USB controllers
The A31 has two ECHI/OHCI controllers, and one OHCI-only phy-less controller. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com>
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@ -341,6 +341,83 @@
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status = "disabled";
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};
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usbphy: phy@01c19400 {
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compatible = "allwinner,sun6i-a31-usb-phy";
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reg = <0x01c19400 0x10>,
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<0x01c1a800 0x4>,
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<0x01c1b800 0x4>;
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reg-names = "phy_ctrl",
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"pmu1",
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"pmu2";
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clocks = <&usb_clk 8>,
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<&usb_clk 9>,
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<&usb_clk 10>;
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clock-names = "usb0_phy",
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"usb1_phy",
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"usb2_phy";
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resets = <&usb_clk 0>,
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<&usb_clk 1>,
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<&usb_clk 2>;
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reset-names = "usb0_reset",
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"usb1_reset",
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"usb2_reset";
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status = "disabled";
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#phy-cells = <1>;
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};
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ehci0: usb@01c1a000 {
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compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
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reg = <0x01c1a000 0x100>;
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interrupts = <0 72 4>;
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clocks = <&ahb1_gates 26>;
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resets = <&ahb1_rst 26>;
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phys = <&usbphy 1>;
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phy-names = "usb";
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status = "disabled";
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};
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ohci0: usb@01c1a400 {
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compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
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reg = <0x01c1a400 0x100>;
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interrupts = <0 73 4>;
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clocks = <&ahb1_gates 29>, <&usb_clk 16>;
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resets = <&ahb1_rst 29>;
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phys = <&usbphy 1>;
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phy-names = "usb";
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status = "disabled";
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};
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ehci1: usb@01c1b000 {
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compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
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reg = <0x01c1b000 0x100>;
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interrupts = <0 74 4>;
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clocks = <&ahb1_gates 27>;
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resets = <&ahb1_rst 27>;
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phys = <&usbphy 2>;
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phy-names = "usb";
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status = "disabled";
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};
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ohci1: usb@01c1b400 {
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compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
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reg = <0x01c1b400 0x100>;
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interrupts = <0 75 4>;
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clocks = <&ahb1_gates 30>, <&usb_clk 17>;
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resets = <&ahb1_rst 30>;
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phys = <&usbphy 2>;
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phy-names = "usb";
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status = "disabled";
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};
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ohci2: usb@01c1c000 {
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compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
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reg = <0x01c1c400 0x100>;
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interrupts = <0 77 4>;
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clocks = <&ahb1_gates 31>, <&usb_clk 18>;
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resets = <&ahb1_rst 31>;
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status = "disabled";
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};
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pio: pinctrl@01c20800 {
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compatible = "allwinner,sun6i-a31-pinctrl";
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reg = <0x01c20800 0x400>;
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