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MIPS: EMMA2RH: Remove useless CPU_IRQ_BASE 

For historical reasons, we used to put MIPS CPU IRQs behind SoC-specific
IRQs in the queue, and have been using CPU_IRQ_BASE as MIPS_CPU_IRQ_BASE.
In recent years, however, we've brought it back to normal order, and now
CPU_IRQ_BASE just redefines the generic MIPS_CPU_IRQ_BASE.

At the same time, NUM_CPU_IRQ is also removed as useless.

Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi.px@renesas.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1387/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Shinya Kuribayashi 2010-06-17 20:35:58 +09:00 committed by Ralf Baechle
parent 1d1929c766
commit eebacda40f
2 changed files with 5 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
arch/mips/emma/markeins/irq.c
View File

@ -301,7 +301,7 @@ void __init arch_init_irq(void)
/* setup cascade interrupts */ /* setup cascade interrupts */
setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_SW_CASCADE, &irq_cascade); setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_SW_CASCADE, &irq_cascade);
setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_GPIO_CASCADE, &irq_cascade); setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_GPIO_CASCADE, &irq_cascade);
setup_irq(CPU_IRQ_BASE + CPU_EMMA2RH_CASCADE, &irq_cascade); setup_irq(MIPS_CPU_IRQ_BASE + CPU_EMMA2RH_CASCADE, &irq_cascade);
} }
asmlinkage void plat_irq_dispatch(void) asmlinkage void plat_irq_dispatch(void)
@ -309,13 +309,13 @@ asmlinkage void plat_irq_dispatch(void)
unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM; unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
if (pending & STATUSF_IP7) if (pending & STATUSF_IP7)
do_IRQ(CPU_IRQ_BASE + 7); do_IRQ(MIPS_CPU_IRQ_BASE + 7);
else if (pending & STATUSF_IP2) else if (pending & STATUSF_IP2)
emma2rh_irq_dispatch(); emma2rh_irq_dispatch();
else if (pending & STATUSF_IP1) else if (pending & STATUSF_IP1)
do_IRQ(CPU_IRQ_BASE + 1); do_IRQ(MIPS_CPU_IRQ_BASE + 1);
else if (pending & STATUSF_IP0) else if (pending & STATUSF_IP0)
do_IRQ(CPU_IRQ_BASE + 0); do_IRQ(MIPS_CPU_IRQ_BASE + 0);
else else
spurious_interrupt(); spurious_interrupt();
} }

4
arch/mips/include/asm/emma/emma2rh.h
View File

@ -99,12 +99,10 @@
#define EMMA2RH_PCI_CONFIG_BASE EMMA2RH_PCI_IO_BASE #define EMMA2RH_PCI_CONFIG_BASE EMMA2RH_PCI_IO_BASE
#define EMMA2RH_PCI_CONFIG_SIZE EMMA2RH_PCI_IO_SIZE #define EMMA2RH_PCI_CONFIG_SIZE EMMA2RH_PCI_IO_SIZE
#define NUM_CPU_IRQ 8
#define NUM_EMMA2RH_IRQ 96 #define NUM_EMMA2RH_IRQ 96
#define CPU_EMMA2RH_CASCADE 2 #define CPU_EMMA2RH_CASCADE 2
#define CPU_IRQ_BASE MIPS_CPU_IRQ_BASE #define EMMA2RH_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8)
#define EMMA2RH_IRQ_BASE (CPU_IRQ_BASE + NUM_CPU_IRQ)
/* /*
* emma2rh irq defs * emma2rh irq defs