arm64: Add initial DTS for APM X-Gene Storm SOC and APM Mustang board
This patch adds initial DTS files required for APM Mustang board. Signed-off-by: Kumar Sankaran <ksankaran@apm.com> Signed-off-by: Loc Ho <lho@apm.com> Signed-off-by: Feng Kan <fkan@apm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb foundation-v8.dtb
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dtb-$(CONFIG_ARCH_XGENE) += apm-mustang.dtb
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targets += dtbs
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targets += $(dtb-y)
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/*
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* dts file for AppliedMicro (APM) Mustang Board
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*
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* Copyright (C) 2013, Applied Micro Circuits Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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/dts-v1/;
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/include/ "apm-storm.dtsi"
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/ {
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model = "APM X-Gene Mustang board";
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compatible = "apm,mustang", "apm,xgene-storm";
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chosen { };
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memory {
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device_type = "memory";
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reg = < 0x1 0x00000000 0x0 0x80000000 >; /* Updated by bootloader */
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};
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};
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/*
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* dts file for AppliedMicro (APM) X-Gene Storm SOC
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*
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* Copyright (C) 2013, Applied Micro Circuits Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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/ {
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compatible = "apm,xgene-storm";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu@000 {
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device_type = "cpu";
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compatible = "apm,potenza", "arm,armv8";
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reg = <0x0 0x000>;
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enable-method = "spin-table";
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cpu-release-addr = <0x1 0x0000fff8>;
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};
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cpu@001 {
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device_type = "cpu";
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compatible = "apm,potenza", "arm,armv8";
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reg = <0x0 0x001>;
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enable-method = "spin-table";
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cpu-release-addr = <0x1 0x0000fff8>;
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};
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cpu@100 {
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device_type = "cpu";
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compatible = "apm,potenza", "arm,armv8";
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reg = <0x0 0x100>;
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enable-method = "spin-table";
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cpu-release-addr = <0x1 0x0000fff8>;
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};
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cpu@101 {
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device_type = "cpu";
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compatible = "apm,potenza", "arm,armv8";
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reg = <0x0 0x101>;
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enable-method = "spin-table";
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cpu-release-addr = <0x1 0x0000fff8>;
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};
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cpu@200 {
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device_type = "cpu";
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compatible = "apm,potenza", "arm,armv8";
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reg = <0x0 0x200>;
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enable-method = "spin-table";
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cpu-release-addr = <0x1 0x0000fff8>;
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};
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cpu@201 {
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device_type = "cpu";
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compatible = "apm,potenza", "arm,armv8";
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reg = <0x0 0x201>;
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enable-method = "spin-table";
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cpu-release-addr = <0x1 0x0000fff8>;
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};
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cpu@300 {
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device_type = "cpu";
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compatible = "apm,potenza", "arm,armv8";
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reg = <0x0 0x300>;
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enable-method = "spin-table";
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cpu-release-addr = <0x1 0x0000fff8>;
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};
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cpu@301 {
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device_type = "cpu";
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compatible = "apm,potenza", "arm,armv8";
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reg = <0x0 0x301>;
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enable-method = "spin-table";
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cpu-release-addr = <0x1 0x0000fff8>;
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};
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};
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gic: interrupt-controller@78010000 {
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compatible = "arm,cortex-a15-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x0 0x78010000 0x0 0x1000>, /* GIC Dist */
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<0x0 0x78020000 0x0 0x1000>, /* GIC CPU */
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<0x0 0x78040000 0x0 0x2000>, /* GIC VCPU Control */
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<0x0 0x78060000 0x0 0x2000>; /* GIC VCPU */
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interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <1 0 0xff01>, /* Secure Phys IRQ */
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<1 13 0xff01>, /* Non-secure Phys IRQ */
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<1 14 0xff01>, /* Virt IRQ */
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<1 15 0xff01>; /* Hyp IRQ */
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clock-frequency = <50000000>;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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serial0: serial@1c020000 {
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device_type = "serial";
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compatible = "ns16550";
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reg = <0 0x1c020000 0x0 0x1000>;
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reg-shift = <2>;
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clock-frequency = <10000000>; /* Updated by bootloader */
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interrupt-parent = <&gic>;
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interrupts = <0x0 0x4c 0x4>;
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};
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};
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};
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