[PATCH] x86-64: Remove obsolete APIC "write around" bug workaround
No x86-64 chipset has this bug Generated code doesn't change because it was always disabled. Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
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@ -51,10 +51,10 @@ static void cluster_init_apic_ldr(void)
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count = 3;
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count = 3;
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id = my_cluster | (1UL << count);
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id = my_cluster | (1UL << count);
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x86_cpu_to_log_apicid[smp_processor_id()] = id;
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x86_cpu_to_log_apicid[smp_processor_id()] = id;
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apic_write_around(APIC_DFR, APIC_DFR_CLUSTER);
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apic_write(APIC_DFR, APIC_DFR_CLUSTER);
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val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
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val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
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val |= SET_APIC_LOGICAL_ID(id);
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val |= SET_APIC_LOGICAL_ID(id);
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apic_write_around(APIC_LDR, val);
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apic_write(APIC_LDR, val);
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}
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}
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/* Start with all IRQs pointing to boot CPU. IRQ balancing will shift them. */
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/* Start with all IRQs pointing to boot CPU. IRQ balancing will shift them. */
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@ -38,10 +38,10 @@ static void flat_init_apic_ldr(void)
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num = smp_processor_id();
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num = smp_processor_id();
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id = 1UL << num;
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id = 1UL << num;
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x86_cpu_to_log_apicid[num] = id;
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x86_cpu_to_log_apicid[num] = id;
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apic_write_around(APIC_DFR, APIC_DFR_FLAT);
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apic_write(APIC_DFR, APIC_DFR_FLAT);
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val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
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val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
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val |= SET_APIC_LOGICAL_ID(id);
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val |= SET_APIC_LOGICAL_ID(id);
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apic_write_around(APIC_LDR, val);
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apic_write(APIC_LDR, val);
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}
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}
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static void flat_send_IPI_mask(cpumask_t cpumask, int vector)
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static void flat_send_IPI_mask(cpumask_t cpumask, int vector)
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@ -62,7 +62,7 @@ static void flat_send_IPI_mask(cpumask_t cpumask, int vector)
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* prepare target chip field
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* prepare target chip field
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*/
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*/
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cfg = __prepare_ICR2(mask);
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cfg = __prepare_ICR2(mask);
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apic_write_around(APIC_ICR2, cfg);
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apic_write(APIC_ICR2, cfg);
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/*
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/*
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* program the ICR
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* program the ICR
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@ -72,7 +72,7 @@ static void flat_send_IPI_mask(cpumask_t cpumask, int vector)
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/*
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/*
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* Send the IPI. The write to APIC_ICR fires this off.
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* Send the IPI. The write to APIC_ICR fires this off.
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*/
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*/
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apic_write_around(APIC_ICR, cfg);
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apic_write(APIC_ICR, cfg);
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local_irq_restore(flags);
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local_irq_restore(flags);
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}
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}
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@ -66,7 +66,7 @@ static inline void __send_IPI_shortcut(unsigned int shortcut, int vector, unsign
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/*
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/*
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* Send the IPI. The write to APIC_ICR fires this off.
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* Send the IPI. The write to APIC_ICR fires this off.
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*/
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*/
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apic_write_around(APIC_ICR, cfg);
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apic_write(APIC_ICR, cfg);
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}
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}
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@ -92,7 +92,7 @@ static inline void send_IPI_mask_sequence(cpumask_t mask, int vector)
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* prepare target chip field
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* prepare target chip field
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*/
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*/
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cfg = __prepare_ICR2(x86_cpu_to_apicid[query_cpu]);
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cfg = __prepare_ICR2(x86_cpu_to_apicid[query_cpu]);
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apic_write_around(APIC_ICR2, cfg);
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apic_write(APIC_ICR2, cfg);
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/*
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/*
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* program the ICR
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* program the ICR
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@ -102,7 +102,7 @@ static inline void send_IPI_mask_sequence(cpumask_t mask, int vector)
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/*
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/*
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* Send the IPI. The write to APIC_ICR fires this off.
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* Send the IPI. The write to APIC_ICR fires this off.
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*/
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*/
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apic_write_around(APIC_ICR, cfg);
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apic_write(APIC_ICR, cfg);
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}
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}
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local_irq_restore(flags);
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local_irq_restore(flags);
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}
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}
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