CRISv32: use generic clockevents
Implement a oneshot-capable clockevents device so we get support for things like hrtimers and NOHZ. Signed-off-by: Rabin Vincent <rabin@rab.in> Signed-off-by: Jesper Nilsson <jespern@axis.com>
This commit is contained in:
Rabin Vincent
Jesper Nilsson
parent
16428f943d
commit
ed9fd3ff02
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@ -55,6 +55,7 @@ config CRIS
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select IRQ_DOMAIN if ETRAX_ARCH_V32
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select OF if ETRAX_ARCH_V32
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select OF_EARLY_FLATTREE if ETRAX_ARCH_V32
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select GENERIC_CLOCKEVENTS if ETRAX_ARCH_V32
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config HZ
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int
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@ -8,6 +8,7 @@
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#include <linux/timex.h>
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#include <linux/time.h>
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <linux/interrupt.h>
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#include <linux/swap.h>
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#include <linux/sched.h>
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@ -36,6 +37,8 @@
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/* Number of 763 counts before watchdog bites */
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#define ETRAX_WD_CNT ((2*ETRAX_WD_HZ)/HZ + 1)
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#define CRISV32_TIMER_FREQ (100000000lu)
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/* Register the continuos readonly timer available in FS and ARTPEC-3. */
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static cycle_t read_cont_rotime(struct clocksource *cs)
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{
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@ -186,81 +189,99 @@ void handle_watchdog_bite(struct pt_regs *regs)
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#endif
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}
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/*
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* timer_interrupt() needs to keep up the real-time clock,
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* as well as call the "xtime_update()" routine every clocktick.
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*/
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extern void cris_do_profile(struct pt_regs *regs);
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extern void cris_profile_sample(struct pt_regs *regs);
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static void __iomem *timer_base;
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static inline irqreturn_t timer_interrupt(int irq, void *dev_id)
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static void crisv32_clkevt_mode(enum clock_event_mode mode,
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struct clock_event_device *dev)
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{
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struct pt_regs *regs = get_irq_regs();
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int cpu = smp_processor_id();
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reg_timer_r_masked_intr masked_intr;
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reg_timer_rw_ack_intr ack_intr = { 0 };
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reg_timer_rw_tmr0_ctrl ctrl = {
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.op = regk_timer_hold,
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.freq = regk_timer_f100,
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};
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/* Check if the timer interrupt is for us (a tmr0 int) */
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masked_intr = REG_RD(timer, timer_regs[cpu], r_masked_intr);
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if (!masked_intr.tmr0)
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REG_WR(timer, timer_base, rw_tmr0_ctrl, ctrl);
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}
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static int crisv32_clkevt_next_event(unsigned long evt,
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struct clock_event_device *dev)
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{
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reg_timer_rw_tmr0_ctrl ctrl = {
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.op = regk_timer_ld,
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.freq = regk_timer_f100,
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};
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REG_WR(timer, timer_base, rw_tmr0_div, evt);
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REG_WR(timer, timer_base, rw_tmr0_ctrl, ctrl);
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ctrl.op = regk_timer_run;
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REG_WR(timer, timer_base, rw_tmr0_ctrl, ctrl);
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return 0;
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}
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static irqreturn_t crisv32_timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = dev_id;
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reg_timer_rw_tmr0_ctrl ctrl = {
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.op = regk_timer_hold,
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.freq = regk_timer_f100,
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};
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reg_timer_rw_ack_intr ack = { .tmr0 = 1 };
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reg_timer_r_masked_intr intr;
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intr = REG_RD(timer, timer_base, r_masked_intr);
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if (!intr.tmr0)
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return IRQ_NONE;
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/* Acknowledge the timer irq. */
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ack_intr.tmr0 = 1;
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REG_WR(timer, timer_regs[cpu], rw_ack_intr, ack_intr);
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REG_WR(timer, timer_base, rw_tmr0_ctrl, ctrl);
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REG_WR(timer, timer_base, rw_ack_intr, ack);
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/* Reset watchdog otherwise it resets us! */
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reset_watchdog();
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#ifdef CONFIG_SYSTEM_PROFILER
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cris_profile_sample(get_irq_regs());
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#endif
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/* Update statistics. */
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update_process_times(user_mode(regs));
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evt->event_handler(evt);
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cris_do_profile(regs); /* Save profiling information */
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/* The master CPU is responsible for the time keeping. */
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if (cpu != 0)
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return IRQ_HANDLED;
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/* Call the real timer interrupt handler */
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xtime_update(1);
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return IRQ_HANDLED;
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}
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/* Timer is IRQF_SHARED so drivers can add stuff to the timer irq chain. */
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static struct irqaction irq_timer = {
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.handler = timer_interrupt,
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.flags = IRQF_SHARED,
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.name = "timer"
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static struct clock_event_device crisv32_clockevent = {
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.name = "crisv32-timer",
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.rating = 300,
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.features = CLOCK_EVT_FEAT_ONESHOT,
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.set_mode = crisv32_clkevt_mode,
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.set_next_event = crisv32_clkevt_next_event,
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};
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void __init cris_timer_init(void)
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/* Timer is IRQF_SHARED so drivers can add stuff to the timer irq chain. */
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static struct irqaction irq_timer = {
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.handler = crisv32_timer_interrupt,
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.flags = IRQF_TIMER | IRQF_SHARED,
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.name = "crisv32-timer",
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.dev_id = &crisv32_clockevent,
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};
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static void __init crisv32_timer_init(void)
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{
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int cpu = smp_processor_id();
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reg_timer_rw_tmr0_ctrl tmr0_ctrl = { 0 };
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reg_timer_rw_tmr0_div tmr0_div = TIMER0_DIV;
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reg_timer_rw_intr_mask timer_intr_mask;
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reg_timer_rw_tmr0_ctrl ctrl = {
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.op = regk_timer_hold,
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.freq = regk_timer_f100,
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};
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/* Setup the etrax timers.
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* Base frequency is 100MHz, divider 1000000 -> 100 HZ
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* We use timer0, so timer1 is free.
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* The trig timer is used by the fasttimer API if enabled.
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*/
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REG_WR(timer, timer_base, rw_tmr0_ctrl, ctrl);
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tmr0_ctrl.op = regk_timer_ld;
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tmr0_ctrl.freq = regk_timer_f100;
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REG_WR(timer, timer_regs[cpu], rw_tmr0_div, tmr0_div);
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REG_WR(timer, timer_regs[cpu], rw_tmr0_ctrl, tmr0_ctrl); /* Load */
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tmr0_ctrl.op = regk_timer_run;
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REG_WR(timer, timer_regs[cpu], rw_tmr0_ctrl, tmr0_ctrl); /* Start */
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/* Enable the timer irq. */
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timer_intr_mask = REG_RD(timer, timer_regs[cpu], rw_intr_mask);
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timer_intr_mask = REG_RD(timer, timer_base, rw_intr_mask);
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timer_intr_mask.tmr0 = 1;
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REG_WR(timer, timer_regs[cpu], rw_intr_mask, timer_intr_mask);
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REG_WR(timer, timer_base, rw_intr_mask, timer_intr_mask);
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}
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void __init time_init(void)
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{
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reg_intr_vect_rw_mask intr_mask;
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int irq;
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int ret;
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/* Probe for the RTC and read it if it exists.
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* Before the RTC can be probed the loops_per_usec variable needs
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@ -270,17 +291,21 @@ void __init time_init(void)
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*/
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loops_per_usec = 50;
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/* Start CPU local timer. */
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cris_timer_init();
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irq = TIMER0_INTR_VECT;
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timer_base = (void __iomem *) regi_timer0;
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/* Enable the timer irq in global config. */
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intr_mask = REG_RD_VECT(intr_vect, regi_irq, rw_mask, 1);
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intr_mask.timer0 = 1;
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REG_WR_VECT(intr_vect, regi_irq, rw_mask, 1, intr_mask);
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crisv32_timer_init();
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/* Now actually register the timer irq handler that calls
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* timer_interrupt(). */
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setup_irq(TIMER0_INTR_VECT, &irq_timer);
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crisv32_clockevent.cpumask = cpu_possible_mask;
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crisv32_clockevent.irq = irq;
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ret = setup_irq(irq, &irq_timer);
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if (ret)
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pr_warn("failed to setup irq %d\n", irq);
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clockevents_config_and_register(&crisv32_clockevent,
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CRISV32_TIMER_FREQ,
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2, 0xffffffff);
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/* Enable watchdog if we should use one. */
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