pata_it8213: fix PIO2 underclocking
[ port of Sergei's fixes for pata_efar from commit 5f33b3b
]
Fix the PIO mode 2 using mode 0 timings -- this driver should enable the
fast timing bank starting with PIO2, just like the PIIX/ICH drivers do.
Also, fix/rephrase some comments while at it.
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
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@ -92,18 +92,17 @@ static void it8213_set_piomode (struct ata_port *ap, struct ata_device *adev)
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{ 2, 1 },
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{ 2, 3 }, };
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if (pio > 2)
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control |= 1; /* TIME1 enable */
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if (pio > 1)
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control |= 1; /* TIME */
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if (ata_pio_need_iordy(adev)) /* PIO 3/4 require IORDY */
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control |= 2; /* IORDY enable */
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control |= 2; /* IE */
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/* Bit 2 is set for ATAPI on the IT8213 - reverse of ICH/PIIX */
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if (adev->class != ATA_DEV_ATA)
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control |= 4;
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control |= 4; /* PPE */
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pci_read_config_word(dev, idetm_port, &idetm_data);
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/* Enable PPE, IE and TIME as appropriate */
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/* Set PPE, IE, and TIME as appropriate */
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if (adev->devno == 0) {
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idetm_data &= 0xCCF0;
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idetm_data |= control;
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@ -122,7 +121,7 @@ static void it8213_set_piomode (struct ata_port *ap, struct ata_device *adev)
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pci_write_config_byte(dev, 0x44, slave_data);
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}
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idetm_data |= 0x4000; /* Ensure SITRE is enabled */
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idetm_data |= 0x4000; /* Ensure SITRE is set */
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pci_write_config_word(dev, idetm_port, idetm_data);
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}
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