iio: temp: max31865: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition
Fixes: e112dc4e18
("iio: temperature: Add MAX31865 RTD Support")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Navin Sankar Velliangiri <navin@linumiz.com>
Acked-by: Nuno Sá <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20220508175712.647246-92-jic23@kernel.org
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@ -55,7 +55,7 @@ struct max31865_data {
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struct mutex lock;
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bool filter_50hz;
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bool three_wire;
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u8 buf[2] ____cacheline_aligned;
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u8 buf[2] __aligned(IIO_DMA_MINALIGN);
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};
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static int max31865_read(struct max31865_data *data, u8 reg,
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