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linux-sg2042
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Fixup a few lose ends in explicit support for MIPS R1/R2. 

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ralf Baechle 2005-10-07 16:58:15 +01:00
parent f92c1759a4
commit ec917c2c1a
13 changed files with 50 additions and 51 deletions
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4
arch/mips/kernel/Makefile
View File

@ -28,8 +28,8 @@ obj-$(CONFIG_CPU_RM9000) += r4k_fpu.o r4k_switch.o
obj-$(CONFIG_CPU_NEVADA) += r4k_fpu.o r4k_switch.o
obj-$(CONFIG_CPU_R10000) += r4k_fpu.o r4k_switch.o
obj-$(CONFIG_CPU_SB1) += r4k_fpu.o r4k_switch.o
obj-$(CONFIG_CPU_MIPS32_R1) += r4k_fpu.o r4k_switch.o
obj-$(CONFIG_CPU_MIPS64_R1) += r4k_fpu.o r4k_switch.o
obj-$(CONFIG_CPU_MIPS32) += r4k_fpu.o r4k_switch.o
obj-$(CONFIG_CPU_MIPS64) += r4k_fpu.o r4k_switch.o
obj-$(CONFIG_CPU_R6000) += r6000_fpu.o r4k_switch.o
obj-$(CONFIG_SMP) += smp.o

2
arch/mips/kernel/r4k_switch.S
View File

@ -165,7 +165,7 @@ LEAF(_init_fpu)
1:
#endif
#ifdef CONFIG_CPU_MIPS32_R1
#ifdef CONFIG_CPU_MIPS32
mtc1 t1, $f0
mtc1 t1, $f1
mtc1 t1, $f2

2
arch/mips/kernel/traps.c
View File

@ -885,7 +885,7 @@ asmlinkage void cache_parity_error(void)
reg_val & (1<<22) ? "E0 " : "");
printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
#if defined(CONFIG_CPU_MIPS32_R1) || defined(CONFIG_CPU_MIPS64_R1)
#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
if (reg_val & (1<<22))
printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());

4
arch/mips/lib-32/Makefile
View File

@ -4,8 +4,8 @@
lib-y += csum_partial.o memset.o watch.o
obj-$(CONFIG_CPU_MIPS32_R1) += dump_tlb.o
obj-$(CONFIG_CPU_MIPS64_R1) += dump_tlb.o
obj-$(CONFIG_CPU_MIPS32) += dump_tlb.o
obj-$(CONFIG_CPU_MIPS64) += dump_tlb.o
obj-$(CONFIG_CPU_NEVADA) += dump_tlb.o
obj-$(CONFIG_CPU_R10000) += dump_tlb.o
obj-$(CONFIG_CPU_R3000) += r3k_dump_tlb.o

4
arch/mips/lib-64/Makefile
View File

@ -4,8 +4,8 @@
lib-y += csum_partial.o memset.o watch.o
obj-$(CONFIG_CPU_MIPS32_R1) += dump_tlb.o
obj-$(CONFIG_CPU_MIPS64_R1) += dump_tlb.o
obj-$(CONFIG_CPU_MIPS32) += dump_tlb.o
obj-$(CONFIG_CPU_MIPS64) += dump_tlb.o
obj-$(CONFIG_CPU_NEVADA) += dump_tlb.o
obj-$(CONFIG_CPU_R10000) += dump_tlb.o
obj-$(CONFIG_CPU_R3000) += r3k_dump_tlb.o

4
arch/mips/mm/Makefile
View File

@ -9,8 +9,8 @@ obj-$(CONFIG_32BIT) += ioremap.o pgtable-32.o
obj-$(CONFIG_64BIT) += pgtable-64.o
obj-$(CONFIG_HIGHMEM) += highmem.o
obj-$(CONFIG_CPU_MIPS32_R1) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o
obj-$(CONFIG_CPU_MIPS64_R1) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o
obj-$(CONFIG_CPU_MIPS32) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o
obj-$(CONFIG_CPU_MIPS64) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o
obj-$(CONFIG_CPU_NEVADA) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o
obj-$(CONFIG_CPU_R10000) += c-r4k.o cex-gen.o pg-r4k.o tlb-andes.o
obj-$(CONFIG_CPU_R3000) += c-r3k.o tlb-r3k.o pg-r4k.o

4
arch/mips/oprofile/Makefile
View File

@ -10,6 +10,6 @@ DRIVER_OBJS = $(addprefix ../../../drivers/oprofile/, \
oprofile-y := $(DRIVER_OBJS) common.o
oprofile-$(CONFIG_CPU_MIPS32_R1) += op_model_mipsxx.o
oprofile-$(CONFIG_CPU_MIPS64_R1) += op_model_mipsxx.o
oprofile-$(CONFIG_CPU_MIPS32) += op_model_mipsxx.o
oprofile-$(CONFIG_CPU_MIPS64) += op_model_mipsxx.o
oprofile-$(CONFIG_CPU_RM9000) += op_model_rm9000.o

2
include/asm-mips/addrspace.h
View File

@ -131,7 +131,7 @@
|| defined (CONFIG_CPU_R5000) \
|| defined (CONFIG_CPU_NEVADA) \
|| defined (CONFIG_CPU_TX49XX) \
|| defined (CONFIG_CPU_MIPS64_R1)
|| defined (CONFIG_CPU_MIPS64)
#define KUSIZE _LLCONST_(0x0000010000000000) /* 2^^40 */
#define KUSIZE_64 _LLCONST_(0x0000010000000000) /* 2^^40 */
#define K0SIZE _LLCONST_(0x0000001000000000) /* 2^^36 */

56
include/asm-mips/bitops.h
View File

@ -12,6 +12,7 @@
#include <linux/config.h>
#include <linux/compiler.h>
#include <linux/types.h>
#include <asm/bug.h>
#include <asm/byteorder.h> /* sigh ... */
#include <asm/cpu-features.h>
@ -546,34 +547,28 @@ static inline int test_bit(unsigned long nr, const volatile unsigned long *addr)
return 1UL & (addr[nr >> SZLONG_LOG] >> (nr & SZLONG_MASK));
}
#ifdef CONFIG_CPU_MIPS32_R1
/*
* Return the bit position (0..31) of the most significant 1 bit in a word
* Returns -1 if no 1 bit exists
*/
static __inline__ int __ilog2(unsigned long x)
{
int lz;
__asm__ (
" .set push \n"
" .set mips32 \n"
" clz %0, %1 \n"
" .set pop \n"
: "=r" (lz)
: "r" (x));
return 31 - lz;
}
#elif defined(CONFIG_CPU_MIPS64_R1)
/*
* Return the bit position (0..63) of the most significant 1 bit in a word
* Returns -1 if no 1 bit exists
*/
static __inline__ int __ilog2(unsigned long x)
static inline int __ilog2(unsigned long x)
{
int lz;
if (sizeof(x) == 4) {
__asm__ (
" .set push \n"
" .set mips32 \n"
" clz %0, %1 \n"
" .set pop \n"
: "=r" (lz)
: "r" (x));
return 31 - lz;
}
BUG_ON(sizeof(x) != 8);
__asm__ (
" .set push \n"
" .set mips64 \n"
@ -584,7 +579,6 @@ static __inline__ int __ilog2(unsigned long x)
return 63 - lz;
}
#endif
/*
* __ffs - find first bit in word.
@ -595,7 +589,7 @@ static __inline__ int __ilog2(unsigned long x)
*/
static inline unsigned long __ffs(unsigned long word)
{
#if defined(CONFIG_CPU_MIPS32_R1) || defined(CONFIG_CPU_MIPS64_R1)
#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
return __ilog2(word & -word);
#else
int b = 0, s;
@ -606,6 +600,8 @@ static inline unsigned long __ffs(unsigned long word)
s = 4; if (word << 28 != 0) s = 0; b += s; word >>= s;
s = 2; if (word << 30 != 0) s = 0; b += s; word >>= s;
s = 1; if (word << 31 != 0) s = 0; b += s;
return b;
#endif
#ifdef CONFIG_64BIT
s = 32; if (word << 32 != 0) s = 0; b += s; word >>= s;
@ -614,9 +610,10 @@ static inline unsigned long __ffs(unsigned long word)
s = 4; if (word << 60 != 0) s = 0; b += s; word >>= s;
s = 2; if (word << 62 != 0) s = 0; b += s; word >>= s;
s = 1; if (word << 63 != 0) s = 0; b += s;
#endif
return b;
#endif
#endif
}
/*
@ -655,10 +652,10 @@ static inline unsigned long ffz(unsigned long word)
*/
static inline unsigned long flz(unsigned long word)
{
#if defined(CONFIG_CPU_MIPS32_R1) || defined(CONFIG_CPU_MIPS64_R1)
#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
return __ilog2(~word);
#else
#if defined(CONFIG_32BIT)
#ifdef CONFIG_32BIT
int r = 31, s;
word = ~word;
s = 16; if ((word & 0xffff0000)) s = 0; r -= s; word <<= s;
@ -666,8 +663,10 @@ static inline unsigned long flz(unsigned long word)
s = 4; if ((word & 0xf0000000)) s = 0; r -= s; word <<= s;
s = 2; if ((word & 0xc0000000)) s = 0; r -= s; word <<= s;
s = 1; if ((word & 0x80000000)) s = 0; r -= s;
return r;
#endif
#if defined(CONFIG_64BIT)
#ifdef CONFIG_64BIT
int r = 63, s;
word = ~word;
s = 32; if ((word & 0xffffffff00000000UL)) s = 0; r -= s; word <<= s;
@ -676,9 +675,10 @@ static inline unsigned long flz(unsigned long word)
s = 4; if ((word & 0xf000000000000000UL)) s = 0; r -= s; word <<= s;
s = 2; if ((word & 0xc000000000000000UL)) s = 0; r -= s; word <<= s;
s = 1; if ((word & 0x8000000000000000UL)) s = 0; r -= s;
#endif
return r;
#endif
#endif
}
/*

2
include/asm-mips/hazards.h
View File

@ -232,7 +232,7 @@ __asm__(
#endif
#if defined(CONFIG_CPU_MIPS32_R2) || defined (CONFIG_CPU_MIPS64_R2)
#ifdef CONFIG_CPU_MIPSR2
#define instruction_hazard() \
do { \
__label__ __next; \

11
include/asm-mips/interrupt.h
View File

@ -19,7 +19,7 @@ __asm__ (
" .set push \n"
" .set reorder \n"
" .set noat \n"
#if defined(CONFIG_CPU_MIPS32_R2) || defined(CONFIG_CPU_MIPS64_R2)
#ifdef CONFIG_CPU_MIPSR2
" ei \n"
#else
" mfc0 $1,$12 \n"
@ -51,7 +51,7 @@ __asm__ (
" .macro local_irq_disable\n"
" .set push \n"
" .set noat \n"
#if defined(CONFIG_CPU_MIPS32_R2) || defined(CONFIG_CPU_MIPS64_R2)
#ifdef CONFIG_CPU_MIPSR2
" di \n"
#else
" mfc0 $1,$12 \n"
@ -91,7 +91,7 @@ __asm__ (
" .set push \n"
" .set reorder \n"
" .set noat \n"
#if defined(CONFIG_CPU_MIPS32_R2) || defined(CONFIG_CPU_MIPS64_R2)
#ifdef CONFIG_CPU_MIPSR2
" di \\result \n"
#else
" mfc0 \\result, $12 \n"
@ -115,8 +115,7 @@ __asm__ (
" .macro local_irq_restore flags \n"
" .set noreorder \n"
" .set noat \n"
#if (defined(CONFIG_CPU_MIPS32_R2) || defined(CONFIG_CPU_MIPS64_R2)) && \
defined(CONFIG_IRQ_CPU)
#if defined(CONFIG_CPU_MIPSR2) && defined(CONFIG_IRQ_CPU)
/*
* Slow, but doesn't suffer from a relativly unlikely race
* condition we're having since days 1.
@ -125,7 +124,7 @@ __asm__ (
" di \n"
" ei \n"
"1: \n"
#elif defined(CONFIG_CPU_MIPS32_R2) || defined(CONFIG_CPU_MIPS64_R2)
#elif defined(CONFIG_CPU_MIPSR2)
/*
* Fast, dangerous. Life is fun, life is good.
*/

4
include/asm-mips/mach-mips/cpu-feature-overrides.h
View File

@ -14,7 +14,7 @@
/*
* CPU feature overrides for MIPS boards
*/
#ifdef CONFIG_CPU_MIPS32_R1
#ifdef CONFIG_CPU_MIPS32
#define cpu_has_tlb 1
#define cpu_has_4kex 1
#define cpu_has_4kcache 1
@ -40,7 +40,7 @@
#define cpu_icache_snoops_remote_store 1
#endif
#ifdef CONFIG_CPU_MIPS64_R1
#ifdef CONFIG_CPU_MIPS64
#define cpu_has_tlb 1
#define cpu_has_4kex 1
#define cpu_has_4kcache 1

2
include/asm-mips/page.h
View File

@ -76,7 +76,7 @@ static inline void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
* These are used to make use of C type-checking..
*/
#ifdef CONFIG_64BIT_PHYS_ADDR
#ifdef CONFIG_CPU_MIPS32_R1
#ifdef CONFIG_CPU_MIPS32
typedef struct { unsigned long pte_low, pte_high; } pte_t;
#define pte_val(x) ((x).pte_low | ((unsigned long long)(x).pte_high << 32))
#else