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ARCv2: IDU-intc: Delete deprecated parameters in Device Trees 

No need for specifying a list of interrupts in the declaration
of IDU interrupt controller anymore since the kernel can obtain
a number of supported interrupts from the build register.

Also delete support of the second parameter for devices which
are connected to IDU because it is not used anywhere.

Signed-off-by: Yuriy Kolerov <yuriy.kolerov@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
This commit is contained in:
Yuriy Kolerov 2017-02-02 03:13:32 +03:00 committed by Vineet Gupta
parent fc73965ed0
commit ec69b269d8
7 changed files with 21 additions and 101 deletions
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24
Documentation/devicetree/bindings/interrupt-controller/snps,archs-idu-intc.txt
View File

@ -8,15 +8,11 @@ Properties:
- compatible: "snps,archs-idu-intc"
- interrupt-controller: This is an interrupt controller.
- interrupt-parent: <reference to parent core intc>
- #interrupt-cells: Must be <2>.
- interrupts: <...> specifies the upstream core irqs
- #interrupt-cells: Must be <1>.
First cell specifies the "common" IRQ from peripheral to IDU
Second cell specifies the irq distribution mode to cores
0=Round Robin; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3
The second cell in interrupts property is deprecated and may be ignored by
the kernel.
Value of the cell specifies the "common" IRQ from peripheral to IDU. Number N
of the particular interrupt line of IDU corresponds to the line N+24 of the
core interrupt controller.
intc accessed via the special ARC AUX register interface, hence "reg" property
is not specified.
@ -32,18 +28,10 @@ Example:
compatible = "snps,archs-idu-intc";
interrupt-controller;
interrupt-parent = <&core_intc>;
/*
* <hwirq distribution>
* distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3
*/
#interrupt-cells = <2>;
/* upstream core irqs: downstream these are "COMMON" irq 0,1.. */
interrupts = <24 25 26 27 28 29 30 31>;
#interrupt-cells = <1>;
};
some_device: serial@c0fc1000 {
interrupt-parent = <&idu_intc>;
interrupts = <0 0>; /* upstream idu IRQ #24, Round Robin */
interrupts = <0>; /* upstream idu IRQ #24 */
};

23
arch/arc/boot/dts/axc003_idu.dtsi
View File

@ -40,18 +40,7 @@
compatible = "snps,archs-idu-intc";
interrupt-controller;
interrupt-parent = <&core_intc>;
/*
* <hwirq distribution>
* distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3
*/
#interrupt-cells = <2>;
/*
* upstream irqs to core intc - downstream these are
* "COMMON" irq 0,1..
*/
interrupts = <24 25>;
#interrupt-cells = <1>;
};
/*
@ -73,12 +62,7 @@
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&idu_intc>;
/*
* cmn irq 1 -> cpu irq 25
* Distribute to cpu0 only
*/
interrupts = <1 1>;
interrupts = <1>;
};
};
@ -119,8 +103,7 @@
reg = < 0xe0012000 0x200 >;
interrupt-controller;
interrupt-parent = <&idu_intc>;
interrupts = <0 1>; /* cmn irq 0 -> cpu irq 24
distribute to cpu0 only */
interrupts = <0>;
};
memory {

10
arch/arc/boot/dts/haps_hs_idu.dts
View File

@ -54,11 +54,7 @@
compatible = "snps,archs-idu-intc";
interrupt-controller;
interrupt-parent = <&core_intc>;
/* <hwirq distribution>
distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3 */
#interrupt-cells = <2>;
interrupts = <24 25 26 27 28 29 30 31>;
#interrupt-cells = <1>;
};
uart0: serial@f0000000 {
@ -66,9 +62,7 @@
compatible = "ns16550a";
reg = <0xf0000000 0x2000>;
interrupt-parent = <&idu_intc>;
/* interrupts = <0 1>; DEST=1*/
/* interrupts = <0 2>; DEST=2*/
interrupts = <0 0>; /* RR*/
interrupts = <0>;
clock-frequency = <50000000>;
baud = <115200>;
reg-shift = <2>;

15
arch/arc/boot/dts/nsim_hs_idu.dts
View File

@ -46,25 +46,14 @@
compatible = "snps,archs-idu-intc";
interrupt-controller;
interrupt-parent = <&core_intc>;
/*
* <hwirq distribution>
* distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3
*/
#interrupt-cells = <2>;
/*
* upstream irqs to core intc - downstream these are
* "COMMON" irq 0,1..
*/
interrupts = <24 25 26 27 28 29 30 31>;
#interrupt-cells = <1>;
};
arcuart0: serial@c0fc1000 {
compatible = "snps,arc-uart";
reg = <0xc0fc1000 0x100>;
interrupt-parent = <&idu_intc>;
interrupts = <0 0>;
interrupts = <0>;
clock-frequency = <80000000>;
current-speed = <115200>;
status = "okay";

20
arch/arc/boot/dts/nsimosci_hs_idu.dts
View File

@ -50,26 +50,14 @@
compatible = "snps,archs-idu-intc";
interrupt-controller;
interrupt-parent = <&core_intc>;
/*
* <hwirq distribution>
* distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3
*/
#interrupt-cells = <2>;
/*
* upstream irqs to core intc - downstream these are
* "COMMON" irq 0,1..
*/
interrupts = <24 25 26 27 28 29 30 31>;
#interrupt-cells = <1>;
};
uart0: serial@f0000000 {
compatible = "ns8250";
reg = <0xf0000000 0x2000>;
interrupt-parent = <&idu_intc>;
interrupts = <0 0>; /* cmn irq 0 -> cpu irq 24
RR distribute to all cpus */
interrupts = <0>;
clock-frequency = <3686400>;
baud = <115200>;
reg-shift = <2>;
@ -93,7 +81,7 @@
ps2: ps2@f9001000 {
compatible = "snps,arc_ps2";
reg = <0xf9000400 0x14>;
interrupts = <3 0>;
interrupts = <3>;
interrupt-parent = <&idu_intc>;
interrupt-names = "arc_ps2_irq";
};
@ -102,7 +90,7 @@
compatible = "ezchip,nps-mgt-enet";
reg = <0xf0003000 0x44>;
interrupt-parent = <&idu_intc>;
interrupts = <1 2>;
interrupts = <1>;
};
arcpct0: pct {

13
arch/arc/boot/dts/vdk_axc003_idu.dtsi
View File

@ -41,14 +41,7 @@
compatible = "snps,archs-idu-intc";
interrupt-controller;
interrupt-parent = <&core_intc>;
/*
* <hwirq distribution>
* distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3
*/
#interrupt-cells = <2>;
interrupts = <24 25 26 27>;
#interrupt-cells = <1>;
};
debug_uart: dw-apb-uart@0x5000 {
@ -56,7 +49,7 @@
reg = <0x5000 0x100>;
clock-frequency = <2403200>;
interrupt-parent = <&idu_intc>;
interrupts = <2 0>;
interrupts = <2>;
baud = <115200>;
reg-shift = <2>;
reg-io-width = <4>;
@ -70,7 +63,7 @@
reg = < 0xe0012000 0x200 >;
interrupt-controller;
interrupt-parent = <&idu_intc>;
interrupts = < 0 0 >;
interrupts = <0>;
};
memory {

17
arch/arc/kernel/mcip.c
View File

@ -255,23 +255,8 @@ static int idu_irq_map(struct irq_domain *d, unsigned int virq, irq_hw_number_t
return 0;
}
static int idu_irq_xlate(struct irq_domain *d, struct device_node *n,
const u32 *intspec, unsigned int intsize,
irq_hw_number_t *out_hwirq, unsigned int *out_type)
{
/*
* Ignore value of interrupt distribution mode for common interrupts in
* IDU which resides in intspec[1] since setting an affinity using value
* from Device Tree is deprecated in ARC.
*/
*out_hwirq = intspec[0];
*out_type = IRQ_TYPE_NONE;
return 0;
}
static const struct irq_domain_ops idu_irq_ops = {
.xlate = idu_irq_xlate,
.xlate = irq_domain_xlate_onecell,
.map = idu_irq_map,
};