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net: dsa: mv88e6xxx: SERDES support 2500BaseT via external PHY 

By using an external PHY, ports 9 and 10 can support 2500BaseT.
So set this link mode in the mask when validating.

Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Andrew Lunn 2019-02-08 22:25:44 +01:00 committed by David S. Miller
parent 132c4e9e6a
commit ec26016b95
1 changed files with 3 additions and 1 deletions
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4
drivers/net/dsa/mv88e6xxx/chip.c
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@ -647,8 +647,10 @@ static void mv88e6390_phylink_validate(struct mv88e6xxx_chip *chip, int port,
unsigned long *mask,
struct phylink_link_state *state)
{
if (port >= 9)
if (port >= 9) {
phylink_set(mask, 2500baseX_Full);
phylink_set(mask, 2500baseT_Full);
}
/* No ethtool bits for 200Mbps */
phylink_set(mask, 1000baseT_Full);