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x86/oprofile: fix and cleanup CTRL_SET_* macros 

This patch fixes missing braces around macro parameters. Macro
definitions from intel_arch_perfmon.h are used where possible.

Signed-off-by: Robert Richter <robert.richter@amd.com>
This commit is contained in:
Robert Richter 2009-05-25 15:05:50 +02:00
parent 1131a47824
commit ec064c093e
2 changed files with 10 additions and 9 deletions
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1
arch/x86/oprofile/op_model_ppro.c
View File

@ -18,7 +18,6 @@
#include <asm/msr.h> #include <asm/msr.h>
#include <asm/apic.h> #include <asm/apic.h>
#include <asm/nmi.h> #include <asm/nmi.h>
#include <asm/intel_arch_perfmon.h>
#include "op_x86_model.h" #include "op_x86_model.h"
#include "op_counter.h" #include "op_counter.h"

18
arch/x86/oprofile/op_x86_model.h
View File

@ -11,14 +11,16 @@
#ifndef OP_X86_MODEL_H #ifndef OP_X86_MODEL_H
#define OP_X86_MODEL_H #define OP_X86_MODEL_H
#define CTR_IS_RESERVED(msrs, c) (msrs->counters[(c)].addr ? 1 : 0) #include <asm/intel_arch_perfmon.h>
#define CTRL_IS_RESERVED(msrs, c) (msrs->controls[(c)].addr ? 1 : 0)
#define CTRL_SET_ACTIVE(n) (n |= (1<<22)) #define CTR_IS_RESERVED(msrs, c) ((msrs)->counters[(c)].addr ? 1 : 0)
#define CTRL_SET_ENABLE(val) (val |= 1<<20) #define CTRL_IS_RESERVED(msrs, c) ((msrs)->controls[(c)].addr ? 1 : 0)
#define CTRL_SET_INACTIVE(n) (n &= ~(1<<22)) #define CTRL_SET_ACTIVE(val) ((val) |= ARCH_PERFMON_EVENTSEL0_ENABLE)
#define CTRL_SET_KERN(val, k) (val |= ((k & 1) << 17)) #define CTRL_SET_ENABLE(val) ((val) |= ARCH_PERFMON_EVENTSEL_INT)
#define CTRL_SET_UM(val, m) (val |= (m << 8)) #define CTRL_SET_INACTIVE(val) ((val) &= ~ARCH_PERFMON_EVENTSEL0_ENABLE)
#define CTRL_SET_USR(val, u) (val |= ((u & 1) << 16)) #define CTRL_SET_KERN(val, k) ((val) |= ((k) ? ARCH_PERFMON_EVENTSEL_OS : 0))
#define CTRL_SET_USR(val, u) ((val) |= ((u) ? ARCH_PERFMON_EVENTSEL_USR : 0))
#define CTRL_SET_UM(val, m) ((val) |= ((m) << 8))
struct op_saved_msr { struct op_saved_msr {
unsigned int high; unsigned int high;