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clk: qoriq: Update the clock bindings 

Main changs include:
	- Clarified the clock nodes' version number
	- Fixed a issue in example

Singed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
This commit is contained in:
Tang Yuantian 2014-05-08 11:12:10 +08:00 committed by Scott Wood
parent 83e267d797
commit eaf76b2142
1 changed files with 9 additions and 1 deletions
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10
Documentation/devicetree/bindings/clock/corenet-clock.txt → Documentation/devicetree/bindings/clock/qoriq-clock.txt
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@ -7,6 +7,14 @@ which can then be passed to a variety of internal logic, including
cores and peripheral IP blocks. cores and peripheral IP blocks.
Please refer to the Reference Manual for details. Please refer to the Reference Manual for details.
All references to "1.0" and "2.0" refer to the QorIQ chassis version to
which the chip complies.
Chassis Version Example Chips
--------------- -------------
1.0 p4080, p5020, p5040
2.0 t4240, b4860, t1040
1. Clock Block Binding 1. Clock Block Binding
Required properties: Required properties:
@ -85,7 +93,7 @@ Example for clock block and clock provider:
#clock-cells = <0>; #clock-cells = <0>;
compatible = "fsl,qoriq-sysclk-1.0"; compatible = "fsl,qoriq-sysclk-1.0";
clock-output-names = "sysclk"; clock-output-names = "sysclk";
} };
pll0: pll0@800 { pll0: pll0@800 {
#clock-cells = <1>; #clock-cells = <1>;