Amlogic 64-bit DT changes for v4.19, round 2
- new SoC: S905W - new boards: based on S905W: Amlogic P281, Oranth Tanix TX3 Mini - AXG: add DT for new audio clock controller -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEe4dGDhaSf6n1v/EMWTcYmtP7xmUFAltWB4EACgkQWTcYmtP7 xmW5Mg/8C8UrOoUcfanK/E3qpogIbyfzJzA4duuBm0HzXjQXBQWVjn2fTJa7kkYF DkMsM16P2c5XjutepySrystcGC7sbvj5BDvGuH6u6y5IvKeWGSM9jQ9Xy6zj53Yw NBifmkBn0JCoO2h0Fauu1iH6xeKdVoCPufM7kXq9evhZ94qd8L+FvWMB6ZSVNl7F WkO27xnL+PWH54flBS+cAkG/Htia635SiIxWdVzG6VdSFoDrJTqFQAAXAhi4XBdH vkanXohQ/weXmJHYWsYpCCjuJFGtceWtaGZKnK+bCbGYXWQB3BgR/qcdGYZ+Ee2K QJr94aaUBlySjDQvYzIGvy0qvyIeLJ/mz7EMQhJS3vG0/OKQgCyNrGpAw1JWjxcK 0LIyNKTW+b/CA8WGDIlEOMnbf11GzBRQzPjf1PneZAFc0xZDIziSCp7bMONA+Nb2 w8STNc82zDwPuPI05ZIKJuiRLWcU/kdnw/1uLdVy4UWq+gvNNxioG1ML7wrXukZV yUErXfmOKCmg49oUeE4wlyJotNqj+YxbWfYmGks0EK/IFomA7i5CeSOrEV9BtkdQ 62ezN8wBnf/XoGon53noyvNHk2W+N0I603G7BxJ1ypV1mH8AWRSwiCxE2mOXgW16 wkwte9qduYYi25V7pkPjnuQ2aFpvPjnRT5FrGj086fDM3PkJVV4= =bHuf -----END PGP SIGNATURE----- Merge tag 'amlogic-dt64-2-1' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into next/dt Amlogic 64-bit DT changes for v4.19, round 2 - new SoC: S905W - new boards: based on S905W: Amlogic P281, Oranth Tanix TX3 Mini - AXG: add DT for new audio clock controller * tag 'amlogic-dt64-2-1' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: ARM64: dts: meson-gxl: add support for the Oranth Tanix TX3 Mini ARM64: dts: meson-gxl: add support for the S905W SoC and the P281 board dt-bindings: arm: amlogic: Add support for the Oranth Tanix TX3 Mini dt-bindings: arm: amlogic: Add support for GXL S905W and the P281 board dt-bindings: add vendor prefix for Shenzhen Oranth Technology Co., Ltd. ARM64: dts: meson-axg: add the audio clock controller clk: meson: expose GEN_CLK clkid clk: meson-axg: add pcie and mipi clock bindings dt-bindings: clock: add meson axg audio clock controller bindings Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
commit
ea537363c7
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@ -45,6 +45,10 @@ Boards with the Amlogic Meson GXL S805X SoC shall have the following properties:
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Required root node property:
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Required root node property:
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compatible: "amlogic,s805x", "amlogic,meson-gxl";
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compatible: "amlogic,s805x", "amlogic,meson-gxl";
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Boards with the Amlogic Meson GXL S905W SoC shall have the following properties:
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Required root node property:
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compatible: "amlogic,s905w", "amlogic,meson-gxl";
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Boards with the Amlogic Meson GXM S912 SoC shall have the following properties:
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Boards with the Amlogic Meson GXM S912 SoC shall have the following properties:
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Required root node property:
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Required root node property:
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compatible: "amlogic,s912", "amlogic,meson-gxm";
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compatible: "amlogic,s912", "amlogic,meson-gxm";
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@ -85,6 +89,9 @@ Board compatible values (alphabetically, grouped by SoC):
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- "amlogic,p241" (Meson gxl s805x)
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- "amlogic,p241" (Meson gxl s805x)
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- "amlogic,p281" (Meson gxl s905w)
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- "oranth,tx3-mini" (Meson gxl s905w)
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- "amlogic,q200" (Meson gxm s912)
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- "amlogic,q200" (Meson gxm s912)
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- "amlogic,q201" (Meson gxm s912)
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- "amlogic,q201" (Meson gxm s912)
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- "khadas,vim2" (Meson gxm s912)
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- "khadas,vim2" (Meson gxm s912)
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@ -0,0 +1,56 @@
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* Amlogic AXG Audio Clock Controllers
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The Amlogic AXG audio clock controller generates and supplies clock to the
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other elements of the audio subsystem, such as fifos, i2s, spdif and pdm
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devices.
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Required Properties:
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- compatible : should be "amlogic,axg-audio-clkc" for the A113X and A113D
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- reg : physical base address of the clock controller and length of
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memory mapped region.
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- clocks : a list of phandle + clock-specifier pairs for the clocks listed
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in clock-names.
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- clock-names : must contain the following:
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* "pclk" - Main peripheral bus clock
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may contain the following:
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* "mst_in[0-7]" - 8 input plls to generate clock signals
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* "slv_sclk[0-9]" - 10 slave bit clocks provided by external
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components.
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* "slv_lrclk[0-9]" - 10 slave sample clocks provided by external
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components.
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- resets : phandle of the internal reset line
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- #clock-cells : should be 1.
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Each clock is assigned an identifier and client nodes can use this identifier
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to specify the clock which they consume. All available clocks are defined as
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preprocessor macros in the dt-bindings/clock/axg-audio-clkc.h header and can be
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used in device tree sources.
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Example:
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clkc_audio: clock-controller@0 {
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compatible = "amlogic,axg-audio-clkc";
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reg = <0x0 0x0 0x0 0xb4>;
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#clock-cells = <1>;
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clocks = <&clkc CLKID_AUDIO>,
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<&clkc CLKID_MPLL0>,
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<&clkc CLKID_MPLL1>,
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<&clkc CLKID_MPLL2>,
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<&clkc CLKID_MPLL3>,
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<&clkc CLKID_HIFI_PLL>,
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<&clkc CLKID_FCLK_DIV3>,
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<&clkc CLKID_FCLK_DIV4>,
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<&clkc CLKID_GP0_PLL>;
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clock-names = "pclk",
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"mst_in0",
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"mst_in1",
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"mst_in2",
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"mst_in3",
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"mst_in4",
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"mst_in5",
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"mst_in6",
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"mst_in7";
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resets = <&reset RESET_AUDIO>;
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};
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@ -273,6 +273,7 @@ opalkelly Opal Kelly Incorporated
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opencores OpenCores.org
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opencores OpenCores.org
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openrisc OpenRISC.io
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openrisc OpenRISC.io
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option Option NV
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option Option NV
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oranth Shenzhen Oranth Technology Co., Ltd.
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ORCL Oracle Corporation
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ORCL Oracle Corporation
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orisetech Orise Technology
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orisetech Orise Technology
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ortustech Ortus Technology Co., Ltd.
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ortustech Ortus Technology Co., Ltd.
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@ -18,6 +18,8 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-p212.dtb
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dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p230.dtb
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dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p230.dtb
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dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p231.dtb
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dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p231.dtb
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dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s805x-p241.dtb
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dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s805x-p241.dtb
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dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905w-p281.dtb
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dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905w-tx3-mini.dtb
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dtb-$(CONFIG_ARCH_MESON) += meson-gxm-khadas-vim2.dtb
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dtb-$(CONFIG_ARCH_MESON) += meson-gxm-khadas-vim2.dtb
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dtb-$(CONFIG_ARCH_MESON) += meson-gxm-nexbox-a1.dtb
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dtb-$(CONFIG_ARCH_MESON) += meson-gxm-nexbox-a1.dtb
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dtb-$(CONFIG_ARCH_MESON) += meson-gxm-q200.dtb
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dtb-$(CONFIG_ARCH_MESON) += meson-gxm-q200.dtb
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@ -6,6 +6,7 @@
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/axg-audio-clkc.h>
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#include <dt-bindings/clock/axg-clkc.h>
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#include <dt-bindings/clock/axg-clkc.h>
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#include <dt-bindings/clock/axg-aoclkc.h>
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#include <dt-bindings/clock/axg-aoclkc.h>
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#include <dt-bindings/gpio/meson-axg-gpio.h>
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#include <dt-bindings/gpio/meson-axg-gpio.h>
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@ -155,6 +156,41 @@
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};
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};
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};
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};
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audio: bus@ff642000 {
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compatible = "simple-bus";
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reg = <0x0 0xff642000 0x0 0x2000>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x0 0x0 0x0 0xff642000 0x0 0x2000>;
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clkc_audio: clock-controller@0 {
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compatible = "amlogic,axg-audio-clkc";
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reg = <0x0 0x0 0x0 0xb4>;
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#clock-cells = <1>;
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clocks = <&clkc CLKID_AUDIO>,
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<&clkc CLKID_MPLL0>,
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<&clkc CLKID_MPLL1>,
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<&clkc CLKID_MPLL2>,
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<&clkc CLKID_MPLL3>,
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<&clkc CLKID_HIFI_PLL>,
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<&clkc CLKID_FCLK_DIV3>,
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<&clkc CLKID_FCLK_DIV4>,
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<&clkc CLKID_GP0_PLL>;
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clock-names = "pclk",
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"mst_in0",
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"mst_in1",
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"mst_in2",
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"mst_in3",
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"mst_in4",
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"mst_in5",
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"mst_in6",
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"mst_in7";
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resets = <&reset RESET_AUDIO>;
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};
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};
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cbus: bus@ffd00000 {
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cbus: bus@ffd00000 {
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compatible = "simple-bus";
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compatible = "simple-bus";
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reg = <0x0 0xffd00000 0x0 0x25000>;
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reg = <0x0 0xffd00000 0x0 0x25000>;
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@ -0,0 +1,22 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2018 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
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* Based on meson-gxl-s905d-p231.dts:
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* - Copyright (c) 2016 Endless Computers, Inc.
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* Author: Carlo Caione <carlo@endlessm.com>
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*/
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/dts-v1/;
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#include "meson-gxl-s905x.dtsi"
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#include "meson-gx-p23x-q20x.dtsi"
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/ {
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compatible = "amlogic,p281", "amlogic,s905w", "amlogic,meson-gxl";
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model = "Amlogic Meson GXL (S905W) P281 Development Board";
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x40000000>;
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};
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};
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@ -0,0 +1,22 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2018 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
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* Based on meson-gxl-s905d-p231.dts:
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* - Copyright (c) 2016 Endless Computers, Inc.
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* Author: Carlo Caione <carlo@endlessm.com>
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*/
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/dts-v1/;
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#include "meson-gxl-s905x.dtsi"
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#include "meson-gx-p23x-q20x.dtsi"
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/ {
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compatible = "oranth,tx3-mini", "amlogic,s905w", "amlogic,meson-gxl";
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model = "Oranth Tanix TX3 Mini";
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x40000000>; /* 1 GiB or 2 GiB */
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};
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};
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@ -0,0 +1,94 @@
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/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
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/*
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* Copyright (c) 2018 Baylibre SAS.
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* Author: Jerome Brunet <jbrunet@baylibre.com>
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*/
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#ifndef __AXG_AUDIO_CLKC_BINDINGS_H
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#define __AXG_AUDIO_CLKC_BINDINGS_H
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#define AUD_CLKID_SLV_SCLK0 9
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#define AUD_CLKID_SLV_SCLK1 10
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#define AUD_CLKID_SLV_SCLK2 11
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#define AUD_CLKID_SLV_SCLK3 12
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#define AUD_CLKID_SLV_SCLK4 13
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#define AUD_CLKID_SLV_SCLK5 14
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#define AUD_CLKID_SLV_SCLK6 15
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#define AUD_CLKID_SLV_SCLK7 16
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#define AUD_CLKID_SLV_SCLK8 17
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#define AUD_CLKID_SLV_SCLK9 18
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#define AUD_CLKID_SLV_LRCLK0 19
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#define AUD_CLKID_SLV_LRCLK1 20
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#define AUD_CLKID_SLV_LRCLK2 21
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#define AUD_CLKID_SLV_LRCLK3 22
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#define AUD_CLKID_SLV_LRCLK4 23
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#define AUD_CLKID_SLV_LRCLK5 24
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#define AUD_CLKID_SLV_LRCLK6 25
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#define AUD_CLKID_SLV_LRCLK7 26
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#define AUD_CLKID_SLV_LRCLK8 27
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#define AUD_CLKID_SLV_LRCLK9 28
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#define AUD_CLKID_DDR_ARB 29
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#define AUD_CLKID_PDM 30
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#define AUD_CLKID_TDMIN_A 31
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#define AUD_CLKID_TDMIN_B 32
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#define AUD_CLKID_TDMIN_C 33
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#define AUD_CLKID_TDMIN_LB 34
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#define AUD_CLKID_TDMOUT_A 35
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#define AUD_CLKID_TDMOUT_B 36
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#define AUD_CLKID_TDMOUT_C 37
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#define AUD_CLKID_FRDDR_A 38
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#define AUD_CLKID_FRDDR_B 39
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#define AUD_CLKID_FRDDR_C 40
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#define AUD_CLKID_TODDR_A 41
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#define AUD_CLKID_TODDR_B 42
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||||||
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#define AUD_CLKID_TODDR_C 43
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#define AUD_CLKID_LOOPBACK 44
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#define AUD_CLKID_SPDIFIN 45
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#define AUD_CLKID_SPDIFOUT 46
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#define AUD_CLKID_RESAMPLE 47
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#define AUD_CLKID_POWER_DETECT 48
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#define AUD_CLKID_MST_A_MCLK 49
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||||||
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#define AUD_CLKID_MST_B_MCLK 50
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||||||
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#define AUD_CLKID_MST_C_MCLK 51
|
||||||
|
#define AUD_CLKID_MST_D_MCLK 52
|
||||||
|
#define AUD_CLKID_MST_E_MCLK 53
|
||||||
|
#define AUD_CLKID_MST_F_MCLK 54
|
||||||
|
#define AUD_CLKID_SPDIFOUT_CLK 55
|
||||||
|
#define AUD_CLKID_SPDIFIN_CLK 56
|
||||||
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#define AUD_CLKID_PDM_DCLK 57
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||||||
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#define AUD_CLKID_PDM_SYSCLK 58
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||||||
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#define AUD_CLKID_MST_A_SCLK 79
|
||||||
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#define AUD_CLKID_MST_B_SCLK 80
|
||||||
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#define AUD_CLKID_MST_C_SCLK 81
|
||||||
|
#define AUD_CLKID_MST_D_SCLK 82
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||||||
|
#define AUD_CLKID_MST_E_SCLK 83
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||||||
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#define AUD_CLKID_MST_F_SCLK 84
|
||||||
|
#define AUD_CLKID_MST_A_LRCLK 86
|
||||||
|
#define AUD_CLKID_MST_B_LRCLK 87
|
||||||
|
#define AUD_CLKID_MST_C_LRCLK 88
|
||||||
|
#define AUD_CLKID_MST_D_LRCLK 89
|
||||||
|
#define AUD_CLKID_MST_E_LRCLK 90
|
||||||
|
#define AUD_CLKID_MST_F_LRCLK 91
|
||||||
|
#define AUD_CLKID_TDMIN_A_SCLK_SEL 116
|
||||||
|
#define AUD_CLKID_TDMIN_B_SCLK_SEL 117
|
||||||
|
#define AUD_CLKID_TDMIN_C_SCLK_SEL 118
|
||||||
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#define AUD_CLKID_TDMIN_LB_SCLK_SEL 119
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#define AUD_CLKID_TDMOUT_A_SCLK_SEL 120
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#define AUD_CLKID_TDMOUT_B_SCLK_SEL 121
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#define AUD_CLKID_TDMOUT_C_SCLK_SEL 122
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#define AUD_CLKID_TDMIN_A_SCLK 123
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#define AUD_CLKID_TDMIN_B_SCLK 124
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#define AUD_CLKID_TDMIN_C_SCLK 125
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||||||
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#define AUD_CLKID_TDMIN_LB_SCLK 126
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#define AUD_CLKID_TDMOUT_A_SCLK 127
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||||||
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#define AUD_CLKID_TDMOUT_B_SCLK 128
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||||||
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#define AUD_CLKID_TDMOUT_C_SCLK 129
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||||||
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#define AUD_CLKID_TDMIN_A_LRCLK 130
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||||||
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#define AUD_CLKID_TDMIN_B_LRCLK 131
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||||||
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#define AUD_CLKID_TDMIN_C_LRCLK 132
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||||||
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#define AUD_CLKID_TDMIN_LB_LRCLK 133
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||||||
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#define AUD_CLKID_TDMOUT_A_LRCLK 134
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||||||
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#define AUD_CLKID_TDMOUT_B_LRCLK 135
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||||||
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#define AUD_CLKID_TDMOUT_C_LRCLK 136
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||||||
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||||||
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#endif /* __AXG_AUDIO_CLKC_BINDINGS_H */
|
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@ -68,5 +68,9 @@
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||||||
#define CLKID_SD_EMMC_B_CLK0 59
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#define CLKID_SD_EMMC_B_CLK0 59
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||||||
#define CLKID_SD_EMMC_C_CLK0 60
|
#define CLKID_SD_EMMC_C_CLK0 60
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||||||
#define CLKID_HIFI_PLL 69
|
#define CLKID_HIFI_PLL 69
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||||||
|
#define CLKID_PCIE_CML_EN0 79
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||||||
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#define CLKID_PCIE_CML_EN1 80
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||||||
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#define CLKID_MIPI_ENABLE 81
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||||||
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#define CLKID_GEN_CLK 84
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||||||
|
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||||||
#endif /* __AXG_CLKC_H */
|
#endif /* __AXG_CLKC_H */
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||||||
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|
|
@ -127,5 +127,6 @@
|
||||||
#define CLKID_VAPB 140
|
#define CLKID_VAPB 140
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||||||
#define CLKID_VDEC_1 153
|
#define CLKID_VDEC_1 153
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||||||
#define CLKID_VDEC_HEVC 156
|
#define CLKID_VDEC_HEVC 156
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||||||
|
#define CLKID_GEN_CLK 159
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||||||
|
|
||||||
#endif /* __GXBB_CLKC_H */
|
#endif /* __GXBB_CLKC_H */
|
||||||
|
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Loading…
Reference in New Issue