video: support DP controller driver
Samsung EXYNOS SoC such Exynos5 has DP controller and embedded DP panel can be used. This patch supports DP driver based on Samsung EXYNOS SoC chip. Signed-off-by: Jingoo Han <jg1.han@samsung.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
This commit is contained in:
Jingoo Han
Florian Tobias Schandinat
parent
9befe40f6e
commit
e9474be4eb
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@ -27,4 +27,11 @@ config EXYNOS_LCD_S6E8AX0
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If you have an S6E8AX0 MIPI AMOLED LCD Panel, say Y to enable its
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LCD control driver.
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config EXYNOS_DP
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bool "EXYNOS DP driver support"
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depends on ARCH_EXYNOS
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default n
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help
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This enables support for DP device.
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endif # EXYNOS_VIDEO
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@ -5,3 +5,4 @@
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obj-$(CONFIG_EXYNOS_MIPI_DSI) += exynos_mipi_dsi.o exynos_mipi_dsi_common.o \
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exynos_mipi_dsi_lowlevel.o
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obj-$(CONFIG_EXYNOS_LCD_S6E8AX0) += s6e8ax0.o
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obj-$(CONFIG_EXYNOS_DP) += exynos_dp_core.o exynos_dp_reg.o
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,206 @@
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/*
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* Header file for Samsung DP (Display Port) interface driver.
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*
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* Copyright (C) 2012 Samsung Electronics Co., Ltd.
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* Author: Jingoo Han <jg1.han@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifndef _EXYNOS_DP_CORE_H
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#define _EXYNOS_DP_CORE_H
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struct link_train {
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int eq_loop;
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int cr_loop[4];
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u8 link_rate;
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u8 lane_count;
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u8 training_lane[4];
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enum link_training_state lt_state;
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};
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struct exynos_dp_device {
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struct device *dev;
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struct resource *res;
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struct clk *clock;
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unsigned int irq;
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void __iomem *reg_base;
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struct video_info *video_info;
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struct link_train link_train;
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};
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/* exynos_dp_reg.c */
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void exynos_dp_enable_video_mute(struct exynos_dp_device *dp, bool enable);
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void exynos_dp_stop_video(struct exynos_dp_device *dp);
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void exynos_dp_lane_swap(struct exynos_dp_device *dp, bool enable);
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void exynos_dp_init_interrupt(struct exynos_dp_device *dp);
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void exynos_dp_reset(struct exynos_dp_device *dp);
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void exynos_dp_config_interrupt(struct exynos_dp_device *dp);
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u32 exynos_dp_get_pll_lock_status(struct exynos_dp_device *dp);
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void exynos_dp_set_pll_power_down(struct exynos_dp_device *dp, bool enable);
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void exynos_dp_set_analog_power_down(struct exynos_dp_device *dp,
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enum analog_power_block block,
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bool enable);
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void exynos_dp_init_analog_func(struct exynos_dp_device *dp);
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void exynos_dp_init_hpd(struct exynos_dp_device *dp);
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void exynos_dp_reset_aux(struct exynos_dp_device *dp);
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void exynos_dp_init_aux(struct exynos_dp_device *dp);
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int exynos_dp_get_plug_in_status(struct exynos_dp_device *dp);
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void exynos_dp_enable_sw_function(struct exynos_dp_device *dp);
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int exynos_dp_start_aux_transaction(struct exynos_dp_device *dp);
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int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp,
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unsigned int reg_addr,
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unsigned char data);
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int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
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unsigned int reg_addr,
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unsigned char *data);
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int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
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unsigned int reg_addr,
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unsigned int count,
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unsigned char data[]);
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int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
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unsigned int reg_addr,
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unsigned int count,
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unsigned char data[]);
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int exynos_dp_select_i2c_device(struct exynos_dp_device *dp,
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unsigned int device_addr,
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unsigned int reg_addr);
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int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
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unsigned int device_addr,
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unsigned int reg_addr,
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unsigned int *data);
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int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
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unsigned int device_addr,
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unsigned int reg_addr,
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unsigned int count,
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unsigned char edid[]);
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void exynos_dp_set_link_bandwidth(struct exynos_dp_device *dp, u32 bwtype);
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void exynos_dp_get_link_bandwidth(struct exynos_dp_device *dp, u32 *bwtype);
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void exynos_dp_set_lane_count(struct exynos_dp_device *dp, u32 count);
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void exynos_dp_get_lane_count(struct exynos_dp_device *dp, u32 *count);
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void exynos_dp_set_link_bandwidth(struct exynos_dp_device *dp, u32 bwtype);
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void exynos_dp_get_link_bandwidth(struct exynos_dp_device *dp, u32 *bwtype);
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void exynos_dp_set_lane_count(struct exynos_dp_device *dp, u32 count);
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void exynos_dp_get_lane_count(struct exynos_dp_device *dp, u32 *count);
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void exynos_dp_enable_enhanced_mode(struct exynos_dp_device *dp, bool enable);
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void exynos_dp_set_training_pattern(struct exynos_dp_device *dp,
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enum pattern_set pattern);
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void exynos_dp_set_lane0_pre_emphasis(struct exynos_dp_device *dp, u32 level);
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void exynos_dp_set_lane1_pre_emphasis(struct exynos_dp_device *dp, u32 level);
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void exynos_dp_set_lane2_pre_emphasis(struct exynos_dp_device *dp, u32 level);
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void exynos_dp_set_lane3_pre_emphasis(struct exynos_dp_device *dp, u32 level);
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void exynos_dp_set_lane0_link_training(struct exynos_dp_device *dp,
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u32 training_lane);
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void exynos_dp_set_lane1_link_training(struct exynos_dp_device *dp,
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u32 training_lane);
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void exynos_dp_set_lane2_link_training(struct exynos_dp_device *dp,
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u32 training_lane);
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void exynos_dp_set_lane3_link_training(struct exynos_dp_device *dp,
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u32 training_lane);
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u32 exynos_dp_get_lane0_link_training(struct exynos_dp_device *dp);
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u32 exynos_dp_get_lane1_link_training(struct exynos_dp_device *dp);
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u32 exynos_dp_get_lane2_link_training(struct exynos_dp_device *dp);
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u32 exynos_dp_get_lane3_link_training(struct exynos_dp_device *dp);
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void exynos_dp_reset_macro(struct exynos_dp_device *dp);
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int exynos_dp_init_video(struct exynos_dp_device *dp);
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void exynos_dp_set_video_color_format(struct exynos_dp_device *dp,
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u32 color_depth,
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u32 color_space,
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u32 dynamic_range,
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u32 ycbcr_coeff);
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int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp_device *dp);
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void exynos_dp_set_video_cr_mn(struct exynos_dp_device *dp,
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enum clock_recovery_m_value_type type,
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u32 m_value,
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u32 n_value);
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void exynos_dp_set_video_timing_mode(struct exynos_dp_device *dp, u32 type);
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void exynos_dp_enable_video_master(struct exynos_dp_device *dp, bool enable);
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void exynos_dp_start_video(struct exynos_dp_device *dp);
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int exynos_dp_is_video_stream_on(struct exynos_dp_device *dp);
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void exynos_dp_config_video_slave_mode(struct exynos_dp_device *dp,
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struct video_info *video_info);
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void exynos_dp_enable_scrambling(struct exynos_dp_device *dp);
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void exynos_dp_disable_scrambling(struct exynos_dp_device *dp);
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/* I2C EDID Chip ID, Slave Address */
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#define I2C_EDID_DEVICE_ADDR 0x50
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#define I2C_E_EDID_DEVICE_ADDR 0x30
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#define EDID_BLOCK_LENGTH 0x80
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#define EDID_HEADER_PATTERN 0x00
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#define EDID_EXTENSION_FLAG 0x7e
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#define EDID_CHECKSUM 0x7f
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/* Definition for DPCD Register */
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#define DPCD_ADDR_DPCD_REV 0x0000
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#define DPCD_ADDR_MAX_LINK_RATE 0x0001
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#define DPCD_ADDR_MAX_LANE_COUNT 0x0002
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#define DPCD_ADDR_LINK_BW_SET 0x0100
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#define DPCD_ADDR_LANE_COUNT_SET 0x0101
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#define DPCD_ADDR_TRAINING_PATTERN_SET 0x0102
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#define DPCD_ADDR_TRAINING_LANE0_SET 0x0103
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#define DPCD_ADDR_LANE0_1_STATUS 0x0202
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#define DPCD_ADDR_LANE_ALIGN__STATUS_UPDATED 0x0204
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#define DPCD_ADDR_ADJUST_REQUEST_LANE0_1 0x0206
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#define DPCD_ADDR_ADJUST_REQUEST_LANE2_3 0x0207
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#define DPCD_ADDR_TEST_REQUEST 0x0218
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#define DPCD_ADDR_TEST_RESPONSE 0x0260
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#define DPCD_ADDR_TEST_EDID_CHECKSUM 0x0261
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#define DPCD_ADDR_SINK_POWER_STATE 0x0600
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/* DPCD_ADDR_MAX_LANE_COUNT */
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#define DPCD_ENHANCED_FRAME_CAP(x) (((x) >> 7) & 0x1)
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#define DPCD_MAX_LANE_COUNT(x) ((x) & 0x1f)
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/* DPCD_ADDR_LANE_COUNT_SET */
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#define DPCD_ENHANCED_FRAME_EN (0x1 << 7)
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#define DPCD_LANE_COUNT_SET(x) ((x) & 0x1f)
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/* DPCD_ADDR_TRAINING_PATTERN_SET */
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#define DPCD_SCRAMBLING_DISABLED (0x1 << 5)
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#define DPCD_SCRAMBLING_ENABLED (0x0 << 5)
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#define DPCD_TRAINING_PATTERN_2 (0x2 << 0)
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#define DPCD_TRAINING_PATTERN_1 (0x1 << 0)
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#define DPCD_TRAINING_PATTERN_DISABLED (0x0 << 0)
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/* DPCD_ADDR_TRAINING_LANE0_SET */
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#define DPCD_MAX_PRE_EMPHASIS_REACHED (0x1 << 5)
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#define DPCD_PRE_EMPHASIS_SET(x) (((x) & 0x3) << 3)
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#define DPCD_PRE_EMPHASIS_GET(x) (((x) >> 3) & 0x3)
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#define DPCD_PRE_EMPHASIS_PATTERN2_LEVEL0 (0x0 << 3)
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#define DPCD_MAX_SWING_REACHED (0x1 << 2)
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#define DPCD_VOLTAGE_SWING_SET(x) (((x) & 0x3) << 0)
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#define DPCD_VOLTAGE_SWING_GET(x) (((x) >> 0) & 0x3)
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#define DPCD_VOLTAGE_SWING_PATTERN1_LEVEL0 (0x0 << 0)
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/* DPCD_ADDR_LANE0_1_STATUS */
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#define DPCD_LANE_SYMBOL_LOCKED (0x1 << 2)
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#define DPCD_LANE_CHANNEL_EQ_DONE (0x1 << 1)
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#define DPCD_LANE_CR_DONE (0x1 << 0)
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#define DPCD_CHANNEL_EQ_BITS (DPCD_LANE_CR_DONE| \
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DPCD_LANE_CHANNEL_EQ_DONE|\
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DPCD_LANE_SYMBOL_LOCKED)
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/* DPCD_ADDR_LANE_ALIGN__STATUS_UPDATED */
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#define DPCD_LINK_STATUS_UPDATED (0x1 << 7)
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#define DPCD_DOWNSTREAM_PORT_STATUS_CHANGED (0x1 << 6)
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#define DPCD_INTERLANE_ALIGN_DONE (0x1 << 0)
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/* DPCD_ADDR_TEST_REQUEST */
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#define DPCD_TEST_EDID_READ (0x1 << 2)
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/* DPCD_ADDR_TEST_RESPONSE */
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#define DPCD_TEST_EDID_CHECKSUM_WRITE (0x1 << 2)
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/* DPCD_ADDR_SINK_POWER_STATE */
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#define DPCD_SET_POWER_STATE_D0 (0x1 << 0)
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#define DPCD_SET_POWER_STATE_D4 (0x2 << 0)
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#endif /* _EXYNOS_DP_CORE_H */
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,335 @@
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/*
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* Register definition file for Samsung DP driver
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*
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* Copyright (C) 2012 Samsung Electronics Co., Ltd.
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* Author: Jingoo Han <jg1.han@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _EXYNOS_DP_REG_H
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#define _EXYNOS_DP_REG_H
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#define EXYNOS_DP_TX_SW_RESET 0x14
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#define EXYNOS_DP_FUNC_EN_1 0x18
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#define EXYNOS_DP_FUNC_EN_2 0x1C
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#define EXYNOS_DP_VIDEO_CTL_1 0x20
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#define EXYNOS_DP_VIDEO_CTL_2 0x24
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#define EXYNOS_DP_VIDEO_CTL_3 0x28
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#define EXYNOS_DP_VIDEO_CTL_8 0x3C
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#define EXYNOS_DP_VIDEO_CTL_10 0x44
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#define EXYNOS_DP_LANE_MAP 0x35C
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#define EXYNOS_DP_AUX_HW_RETRY_CTL 0x390
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#define EXYNOS_DP_COMMON_INT_STA_1 0x3C4
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#define EXYNOS_DP_COMMON_INT_STA_2 0x3C8
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#define EXYNOS_DP_COMMON_INT_STA_3 0x3CC
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#define EXYNOS_DP_COMMON_INT_STA_4 0x3D0
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#define EXYNOS_DP_INT_STA 0x3DC
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#define EXYNOS_DP_COMMON_INT_MASK_1 0x3E0
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#define EXYNOS_DP_COMMON_INT_MASK_2 0x3E4
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#define EXYNOS_DP_COMMON_INT_MASK_3 0x3E8
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#define EXYNOS_DP_COMMON_INT_MASK_4 0x3EC
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#define EXYNOS_DP_INT_STA_MASK 0x3F8
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#define EXYNOS_DP_INT_CTL 0x3FC
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#define EXYNOS_DP_SYS_CTL_1 0x600
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#define EXYNOS_DP_SYS_CTL_2 0x604
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#define EXYNOS_DP_SYS_CTL_3 0x608
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#define EXYNOS_DP_SYS_CTL_4 0x60C
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#define EXYNOS_DP_PKT_SEND_CTL 0x640
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#define EXYNOS_DP_HDCP_CTL 0x648
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#define EXYNOS_DP_LINK_BW_SET 0x680
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#define EXYNOS_DP_LANE_COUNT_SET 0x684
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#define EXYNOS_DP_TRAINING_PTN_SET 0x688
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#define EXYNOS_DP_LN0_LINK_TRAINING_CTL 0x68C
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#define EXYNOS_DP_LN1_LINK_TRAINING_CTL 0x690
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#define EXYNOS_DP_LN2_LINK_TRAINING_CTL 0x694
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#define EXYNOS_DP_LN3_LINK_TRAINING_CTL 0x698
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#define EXYNOS_DP_DEBUG_CTL 0x6C0
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#define EXYNOS_DP_HPD_DEGLITCH_L 0x6C4
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#define EXYNOS_DP_HPD_DEGLITCH_H 0x6C8
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#define EXYNOS_DP_LINK_DEBUG_CTL 0x6E0
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#define EXYNOS_DP_M_VID_0 0x700
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#define EXYNOS_DP_M_VID_1 0x704
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#define EXYNOS_DP_M_VID_2 0x708
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#define EXYNOS_DP_N_VID_0 0x70C
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#define EXYNOS_DP_N_VID_1 0x710
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#define EXYNOS_DP_N_VID_2 0x714
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#define EXYNOS_DP_PLL_CTL 0x71C
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#define EXYNOS_DP_PHY_PD 0x720
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#define EXYNOS_DP_PHY_TEST 0x724
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#define EXYNOS_DP_VIDEO_FIFO_THRD 0x730
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#define EXYNOS_DP_AUDIO_MARGIN 0x73C
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#define EXYNOS_DP_M_VID_GEN_FILTER_TH 0x764
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#define EXYNOS_DP_M_AUD_GEN_FILTER_TH 0x778
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#define EXYNOS_DP_AUX_CH_STA 0x780
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#define EXYNOS_DP_AUX_CH_DEFER_CTL 0x788
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#define EXYNOS_DP_AUX_RX_COMM 0x78C
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#define EXYNOS_DP_BUFFER_DATA_CTL 0x790
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#define EXYNOS_DP_AUX_CH_CTL_1 0x794
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#define EXYNOS_DP_AUX_ADDR_7_0 0x798
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#define EXYNOS_DP_AUX_ADDR_15_8 0x79C
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#define EXYNOS_DP_AUX_ADDR_19_16 0x7A0
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#define EXYNOS_DP_AUX_CH_CTL_2 0x7A4
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#define EXYNOS_DP_BUF_DATA_0 0x7C0
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#define EXYNOS_DP_SOC_GENERAL_CTL 0x800
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/* EXYNOS_DP_TX_SW_RESET */
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#define RESET_DP_TX (0x1 << 0)
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/* EXYNOS_DP_FUNC_EN_1 */
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#define MASTER_VID_FUNC_EN_N (0x1 << 7)
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#define SLAVE_VID_FUNC_EN_N (0x1 << 5)
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#define AUD_FIFO_FUNC_EN_N (0x1 << 4)
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#define AUD_FUNC_EN_N (0x1 << 3)
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#define HDCP_FUNC_EN_N (0x1 << 2)
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#define CRC_FUNC_EN_N (0x1 << 1)
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#define SW_FUNC_EN_N (0x1 << 0)
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/* EXYNOS_DP_FUNC_EN_2 */
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#define SSC_FUNC_EN_N (0x1 << 7)
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#define AUX_FUNC_EN_N (0x1 << 2)
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#define SERDES_FIFO_FUNC_EN_N (0x1 << 1)
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#define LS_CLK_DOMAIN_FUNC_EN_N (0x1 << 0)
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/* EXYNOS_DP_VIDEO_CTL_1 */
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#define VIDEO_EN (0x1 << 7)
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#define HDCP_VIDEO_MUTE (0x1 << 6)
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/* EXYNOS_DP_VIDEO_CTL_1 */
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#define IN_D_RANGE_MASK (0x1 << 7)
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#define IN_D_RANGE_SHIFT (7)
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#define IN_D_RANGE_CEA (0x1 << 7)
|
||||
#define IN_D_RANGE_VESA (0x0 << 7)
|
||||
#define IN_BPC_MASK (0x7 << 4)
|
||||
#define IN_BPC_SHIFT (4)
|
||||
#define IN_BPC_12_BITS (0x3 << 4)
|
||||
#define IN_BPC_10_BITS (0x2 << 4)
|
||||
#define IN_BPC_8_BITS (0x1 << 4)
|
||||
#define IN_BPC_6_BITS (0x0 << 4)
|
||||
#define IN_COLOR_F_MASK (0x3 << 0)
|
||||
#define IN_COLOR_F_SHIFT (0)
|
||||
#define IN_COLOR_F_YCBCR444 (0x2 << 0)
|
||||
#define IN_COLOR_F_YCBCR422 (0x1 << 0)
|
||||
#define IN_COLOR_F_RGB (0x0 << 0)
|
||||
|
||||
/* EXYNOS_DP_VIDEO_CTL_3 */
|
||||
#define IN_YC_COEFFI_MASK (0x1 << 7)
|
||||
#define IN_YC_COEFFI_SHIFT (7)
|
||||
#define IN_YC_COEFFI_ITU709 (0x1 << 7)
|
||||
#define IN_YC_COEFFI_ITU601 (0x0 << 7)
|
||||
#define VID_CHK_UPDATE_TYPE_MASK (0x1 << 4)
|
||||
#define VID_CHK_UPDATE_TYPE_SHIFT (4)
|
||||
#define VID_CHK_UPDATE_TYPE_1 (0x1 << 4)
|
||||
#define VID_CHK_UPDATE_TYPE_0 (0x0 << 4)
|
||||
|
||||
/* EXYNOS_DP_VIDEO_CTL_8 */
|
||||
#define VID_HRES_TH(x) (((x) & 0xf) << 4)
|
||||
#define VID_VRES_TH(x) (((x) & 0xf) << 0)
|
||||
|
||||
/* EXYNOS_DP_VIDEO_CTL_10 */
|
||||
#define FORMAT_SEL (0x1 << 4)
|
||||
#define INTERACE_SCAN_CFG (0x1 << 2)
|
||||
#define VSYNC_POLARITY_CFG (0x1 << 1)
|
||||
#define HSYNC_POLARITY_CFG (0x1 << 0)
|
||||
|
||||
/* EXYNOS_DP_LANE_MAP */
|
||||
#define LANE3_MAP_LOGIC_LANE_0 (0x0 << 6)
|
||||
#define LANE3_MAP_LOGIC_LANE_1 (0x1 << 6)
|
||||
#define LANE3_MAP_LOGIC_LANE_2 (0x2 << 6)
|
||||
#define LANE3_MAP_LOGIC_LANE_3 (0x3 << 6)
|
||||
#define LANE2_MAP_LOGIC_LANE_0 (0x0 << 4)
|
||||
#define LANE2_MAP_LOGIC_LANE_1 (0x1 << 4)
|
||||
#define LANE2_MAP_LOGIC_LANE_2 (0x2 << 4)
|
||||
#define LANE2_MAP_LOGIC_LANE_3 (0x3 << 4)
|
||||
#define LANE1_MAP_LOGIC_LANE_0 (0x0 << 2)
|
||||
#define LANE1_MAP_LOGIC_LANE_1 (0x1 << 2)
|
||||
#define LANE1_MAP_LOGIC_LANE_2 (0x2 << 2)
|
||||
#define LANE1_MAP_LOGIC_LANE_3 (0x3 << 2)
|
||||
#define LANE0_MAP_LOGIC_LANE_0 (0x0 << 0)
|
||||
#define LANE0_MAP_LOGIC_LANE_1 (0x1 << 0)
|
||||
#define LANE0_MAP_LOGIC_LANE_2 (0x2 << 0)
|
||||
#define LANE0_MAP_LOGIC_LANE_3 (0x3 << 0)
|
||||
|
||||
/* EXYNOS_DP_AUX_HW_RETRY_CTL */
|
||||
#define AUX_BIT_PERIOD_EXPECTED_DELAY(x) (((x) & 0x7) << 8)
|
||||
#define AUX_HW_RETRY_INTERVAL_MASK (0x3 << 3)
|
||||
#define AUX_HW_RETRY_INTERVAL_600_MICROSECONDS (0x0 << 3)
|
||||
#define AUX_HW_RETRY_INTERVAL_800_MICROSECONDS (0x1 << 3)
|
||||
#define AUX_HW_RETRY_INTERVAL_1000_MICROSECONDS (0x2 << 3)
|
||||
#define AUX_HW_RETRY_INTERVAL_1800_MICROSECONDS (0x3 << 3)
|
||||
#define AUX_HW_RETRY_COUNT_SEL(x) (((x) & 0x7) << 0)
|
||||
|
||||
/* EXYNOS_DP_COMMON_INT_STA_1 */
|
||||
#define VSYNC_DET (0x1 << 7)
|
||||
#define PLL_LOCK_CHG (0x1 << 6)
|
||||
#define SPDIF_ERR (0x1 << 5)
|
||||
#define SPDIF_UNSTBL (0x1 << 4)
|
||||
#define VID_FORMAT_CHG (0x1 << 3)
|
||||
#define AUD_CLK_CHG (0x1 << 2)
|
||||
#define VID_CLK_CHG (0x1 << 1)
|
||||
#define SW_INT (0x1 << 0)
|
||||
|
||||
/* EXYNOS_DP_COMMON_INT_STA_2 */
|
||||
#define ENC_EN_CHG (0x1 << 6)
|
||||
#define HW_BKSV_RDY (0x1 << 3)
|
||||
#define HW_SHA_DONE (0x1 << 2)
|
||||
#define HW_AUTH_STATE_CHG (0x1 << 1)
|
||||
#define HW_AUTH_DONE (0x1 << 0)
|
||||
|
||||
/* EXYNOS_DP_COMMON_INT_STA_3 */
|
||||
#define AFIFO_UNDER (0x1 << 7)
|
||||
#define AFIFO_OVER (0x1 << 6)
|
||||
#define R0_CHK_FLAG (0x1 << 5)
|
||||
|
||||
/* EXYNOS_DP_COMMON_INT_STA_4 */
|
||||
#define PSR_ACTIVE (0x1 << 7)
|
||||
#define PSR_INACTIVE (0x1 << 6)
|
||||
#define SPDIF_BI_PHASE_ERR (0x1 << 5)
|
||||
#define HOTPLUG_CHG (0x1 << 2)
|
||||
#define HPD_LOST (0x1 << 1)
|
||||
#define PLUG (0x1 << 0)
|
||||
|
||||
/* EXYNOS_DP_INT_STA */
|
||||
#define INT_HPD (0x1 << 6)
|
||||
#define HW_TRAINING_FINISH (0x1 << 5)
|
||||
#define RPLY_RECEIV (0x1 << 1)
|
||||
#define AUX_ERR (0x1 << 0)
|
||||
|
||||
/* EXYNOS_DP_INT_CTL */
|
||||
#define SOFT_INT_CTRL (0x1 << 2)
|
||||
#define INT_POL (0x1 << 0)
|
||||
|
||||
/* EXYNOS_DP_SYS_CTL_1 */
|
||||
#define DET_STA (0x1 << 2)
|
||||
#define FORCE_DET (0x1 << 1)
|
||||
#define DET_CTRL (0x1 << 0)
|
||||
|
||||
/* EXYNOS_DP_SYS_CTL_2 */
|
||||
#define CHA_CRI(x) (((x) & 0xf) << 4)
|
||||
#define CHA_STA (0x1 << 2)
|
||||
#define FORCE_CHA (0x1 << 1)
|
||||
#define CHA_CTRL (0x1 << 0)
|
||||
|
||||
/* EXYNOS_DP_SYS_CTL_3 */
|
||||
#define HPD_STATUS (0x1 << 6)
|
||||
#define F_HPD (0x1 << 5)
|
||||
#define HPD_CTRL (0x1 << 4)
|
||||
#define HDCP_RDY (0x1 << 3)
|
||||
#define STRM_VALID (0x1 << 2)
|
||||
#define F_VALID (0x1 << 1)
|
||||
#define VALID_CTRL (0x1 << 0)
|
||||
|
||||
/* EXYNOS_DP_SYS_CTL_4 */
|
||||
#define FIX_M_AUD (0x1 << 4)
|
||||
#define ENHANCED (0x1 << 3)
|
||||
#define FIX_M_VID (0x1 << 2)
|
||||
#define M_VID_UPDATE_CTRL (0x3 << 0)
|
||||
|
||||
/* EXYNOS_DP_TRAINING_PTN_SET */
|
||||
#define SCRAMBLER_TYPE (0x1 << 9)
|
||||
#define HW_LINK_TRAINING_PATTERN (0x1 << 8)
|
||||
#define SCRAMBLING_DISABLE (0x1 << 5)
|
||||
#define SCRAMBLING_ENABLE (0x0 << 5)
|
||||
#define LINK_QUAL_PATTERN_SET_MASK (0x3 << 2)
|
||||
#define LINK_QUAL_PATTERN_SET_PRBS7 (0x3 << 2)
|
||||
#define LINK_QUAL_PATTERN_SET_D10_2 (0x1 << 2)
|
||||
#define LINK_QUAL_PATTERN_SET_DISABLE (0x0 << 2)
|
||||
#define SW_TRAINING_PATTERN_SET_MASK (0x3 << 0)
|
||||
#define SW_TRAINING_PATTERN_SET_PTN2 (0x2 << 0)
|
||||
#define SW_TRAINING_PATTERN_SET_PTN1 (0x1 << 0)
|
||||
#define SW_TRAINING_PATTERN_SET_NORMAL (0x0 << 0)
|
||||
|
||||
/* EXYNOS_DP_LN0_LINK_TRAINING_CTL */
|
||||
#define PRE_EMPHASIS_SET_SHIFT (3)
|
||||
|
||||
/* EXYNOS_DP_DEBUG_CTL */
|
||||
#define PLL_LOCK (0x1 << 4)
|
||||
#define F_PLL_LOCK (0x1 << 3)
|
||||
#define PLL_LOCK_CTRL (0x1 << 2)
|
||||
#define PN_INV (0x1 << 0)
|
||||
|
||||
/* EXYNOS_DP_PLL_CTL */
|
||||
#define DP_PLL_PD (0x1 << 7)
|
||||
#define DP_PLL_RESET (0x1 << 6)
|
||||
#define DP_PLL_LOOP_BIT_DEFAULT (0x1 << 4)
|
||||
#define DP_PLL_REF_BIT_1_1250V (0x5 << 0)
|
||||
#define DP_PLL_REF_BIT_1_2500V (0x7 << 0)
|
||||
|
||||
/* EXYNOS_DP_PHY_PD */
|
||||
#define DP_PHY_PD (0x1 << 5)
|
||||
#define AUX_PD (0x1 << 4)
|
||||
#define CH3_PD (0x1 << 3)
|
||||
#define CH2_PD (0x1 << 2)
|
||||
#define CH1_PD (0x1 << 1)
|
||||
#define CH0_PD (0x1 << 0)
|
||||
|
||||
/* EXYNOS_DP_PHY_TEST */
|
||||
#define MACRO_RST (0x1 << 5)
|
||||
#define CH1_TEST (0x1 << 1)
|
||||
#define CH0_TEST (0x1 << 0)
|
||||
|
||||
/* EXYNOS_DP_AUX_CH_STA */
|
||||
#define AUX_BUSY (0x1 << 4)
|
||||
#define AUX_STATUS_MASK (0xf << 0)
|
||||
|
||||
/* EXYNOS_DP_AUX_CH_DEFER_CTL */
|
||||
#define DEFER_CTRL_EN (0x1 << 7)
|
||||
#define DEFER_COUNT(x) (((x) & 0x7f) << 0)
|
||||
|
||||
/* EXYNOS_DP_AUX_RX_COMM */
|
||||
#define AUX_RX_COMM_I2C_DEFER (0x2 << 2)
|
||||
#define AUX_RX_COMM_AUX_DEFER (0x2 << 0)
|
||||
|
||||
/* EXYNOS_DP_BUFFER_DATA_CTL */
|
||||
#define BUF_CLR (0x1 << 7)
|
||||
#define BUF_DATA_COUNT(x) (((x) & 0x1f) << 0)
|
||||
|
||||
/* EXYNOS_DP_AUX_CH_CTL_1 */
|
||||
#define AUX_LENGTH(x) (((x - 1) & 0xf) << 4)
|
||||
#define AUX_TX_COMM_MASK (0xf << 0)
|
||||
#define AUX_TX_COMM_DP_TRANSACTION (0x1 << 3)
|
||||
#define AUX_TX_COMM_I2C_TRANSACTION (0x0 << 3)
|
||||
#define AUX_TX_COMM_MOT (0x1 << 2)
|
||||
#define AUX_TX_COMM_WRITE (0x0 << 0)
|
||||
#define AUX_TX_COMM_READ (0x1 << 0)
|
||||
|
||||
/* EXYNOS_DP_AUX_ADDR_7_0 */
|
||||
#define AUX_ADDR_7_0(x) (((x) >> 0) & 0xff)
|
||||
|
||||
/* EXYNOS_DP_AUX_ADDR_15_8 */
|
||||
#define AUX_ADDR_15_8(x) (((x) >> 8) & 0xff)
|
||||
|
||||
/* EXYNOS_DP_AUX_ADDR_19_16 */
|
||||
#define AUX_ADDR_19_16(x) (((x) >> 16) & 0x0f)
|
||||
|
||||
/* EXYNOS_DP_AUX_CH_CTL_2 */
|
||||
#define ADDR_ONLY (0x1 << 1)
|
||||
#define AUX_EN (0x1 << 0)
|
||||
|
||||
/* EXYNOS_DP_SOC_GENERAL_CTL */
|
||||
#define AUDIO_MODE_SPDIF_MODE (0x1 << 8)
|
||||
#define AUDIO_MODE_MASTER_MODE (0x0 << 8)
|
||||
#define MASTER_VIDEO_INTERLACE_EN (0x1 << 4)
|
||||
#define VIDEO_MASTER_CLK_SEL (0x1 << 2)
|
||||
#define VIDEO_MASTER_MODE_EN (0x1 << 1)
|
||||
#define VIDEO_MODE_MASK (0x1 << 0)
|
||||
#define VIDEO_MODE_SLAVE_MODE (0x1 << 0)
|
||||
#define VIDEO_MODE_MASTER_MODE (0x0 << 0)
|
||||
|
||||
#endif /* _EXYNOS_DP_REG_H */
|
||||
|
|
@ -0,0 +1,131 @@
|
|||
/*
|
||||
* Samsung SoC DP device support
|
||||
*
|
||||
* Copyright (C) 2012 Samsung Electronics Co., Ltd.
|
||||
* Author: Jingoo Han <jg1.han@samsung.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef _EXYNOS_DP_H
|
||||
#define _EXYNOS_DP_H
|
||||
|
||||
#define DP_TIMEOUT_LOOP_COUNT 100
|
||||
#define MAX_CR_LOOP 5
|
||||
#define MAX_EQ_LOOP 4
|
||||
|
||||
enum link_rate_type {
|
||||
LINK_RATE_1_62GBPS = 0x06,
|
||||
LINK_RATE_2_70GBPS = 0x0a
|
||||
};
|
||||
|
||||
enum link_lane_count_type {
|
||||
LANE_COUNT1 = 1,
|
||||
LANE_COUNT2 = 2,
|
||||
LANE_COUNT4 = 4
|
||||
};
|
||||
|
||||
enum link_training_state {
|
||||
START,
|
||||
CLOCK_RECOVERY,
|
||||
EQUALIZER_TRAINING,
|
||||
FINISHED,
|
||||
FAILED
|
||||
};
|
||||
|
||||
enum voltage_swing_level {
|
||||
VOLTAGE_LEVEL_0,
|
||||
VOLTAGE_LEVEL_1,
|
||||
VOLTAGE_LEVEL_2,
|
||||
VOLTAGE_LEVEL_3,
|
||||
};
|
||||
|
||||
enum pre_emphasis_level {
|
||||
PRE_EMPHASIS_LEVEL_0,
|
||||
PRE_EMPHASIS_LEVEL_1,
|
||||
PRE_EMPHASIS_LEVEL_2,
|
||||
PRE_EMPHASIS_LEVEL_3,
|
||||
};
|
||||
|
||||
enum pattern_set {
|
||||
PRBS7,
|
||||
D10_2,
|
||||
TRAINING_PTN1,
|
||||
TRAINING_PTN2,
|
||||
DP_NONE
|
||||
};
|
||||
|
||||
enum color_space {
|
||||
COLOR_RGB,
|
||||
COLOR_YCBCR422,
|
||||
COLOR_YCBCR444
|
||||
};
|
||||
|
||||
enum color_depth {
|
||||
COLOR_6,
|
||||
COLOR_8,
|
||||
COLOR_10,
|
||||
COLOR_12
|
||||
};
|
||||
|
||||
enum color_coefficient {
|
||||
COLOR_YCBCR601,
|
||||
COLOR_YCBCR709
|
||||
};
|
||||
|
||||
enum dynamic_range {
|
||||
VESA,
|
||||
CEA
|
||||
};
|
||||
|
||||
enum pll_status {
|
||||
PLL_UNLOCKED,
|
||||
PLL_LOCKED
|
||||
};
|
||||
|
||||
enum clock_recovery_m_value_type {
|
||||
CALCULATED_M,
|
||||
REGISTER_M
|
||||
};
|
||||
|
||||
enum video_timing_recognition_type {
|
||||
VIDEO_TIMING_FROM_CAPTURE,
|
||||
VIDEO_TIMING_FROM_REGISTER
|
||||
};
|
||||
|
||||
enum analog_power_block {
|
||||
AUX_BLOCK,
|
||||
CH0_BLOCK,
|
||||
CH1_BLOCK,
|
||||
CH2_BLOCK,
|
||||
CH3_BLOCK,
|
||||
ANALOG_TOTAL,
|
||||
POWER_ALL
|
||||
};
|
||||
|
||||
struct video_info {
|
||||
char *name;
|
||||
|
||||
bool h_sync_polarity;
|
||||
bool v_sync_polarity;
|
||||
bool interlaced;
|
||||
|
||||
enum color_space color_space;
|
||||
enum dynamic_range dynamic_range;
|
||||
enum color_coefficient ycbcr_coeff;
|
||||
enum color_depth color_depth;
|
||||
|
||||
enum link_rate_type link_rate;
|
||||
enum link_lane_count_type lane_count;
|
||||
};
|
||||
|
||||
struct exynos_dp_platdata {
|
||||
struct video_info *video_info;
|
||||
|
||||
void (*phy_init)(void);
|
||||
void (*phy_exit)(void);
|
||||
};
|
||||
|
||||
#endif /* _EXYNOS_DP_H */
|
||||
Loading…
Reference in New Issue