irqchip/gic-v3: Add INTID range and convertion primitives
In the beginning, life was simple. The GIC driver mostly cared about PPIs, SPIs and LPIs, all with nicely layed out ranges. We're about to change all that, with new ranges such as EPPI and ESPI interleaved in the middle of the no-irq-land between the "special IDs" and the LPI range. Boo. In order to make our life less hellish, let's introduce a set of primitives that will allow ranges to be identified easily and offsets to be remapped. So far, there is no functionnal change. Signed-off-by: Marc Zyngier <maz@kernel.org>
This commit is contained in:
Marc Zyngier
parent
13d22e2e1f
commit
e91b036e1c
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@ -97,6 +97,32 @@ static DEFINE_PER_CPU(bool, has_rss);
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/* Our default, arbitrary priority value. Linux only uses one anyway. */
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#define DEFAULT_PMR_VALUE 0xf0
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enum gic_intid_range {
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PPI_RANGE,
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SPI_RANGE,
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LPI_RANGE,
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__INVALID_RANGE__
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};
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static enum gic_intid_range __get_intid_range(irq_hw_number_t hwirq)
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{
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switch (hwirq) {
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case 16 ... 31:
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return PPI_RANGE;
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case 32 ... 1019:
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return SPI_RANGE;
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case 8192 ... GENMASK(23, 0):
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return LPI_RANGE;
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default:
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return __INVALID_RANGE__;
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}
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}
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static enum gic_intid_range get_intid_range(struct irq_data *d)
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{
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return __get_intid_range(d->hwirq);
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}
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static inline unsigned int gic_irq(struct irq_data *d)
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{
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return d->hwirq;
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@ -104,18 +130,23 @@ static inline unsigned int gic_irq(struct irq_data *d)
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static inline int gic_irq_in_rdist(struct irq_data *d)
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{
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return gic_irq(d) < 32;
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return get_intid_range(d) == PPI_RANGE;
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}
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static inline void __iomem *gic_dist_base(struct irq_data *d)
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{
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if (gic_irq_in_rdist(d)) /* SGI+PPI -> SGI_base for this CPU */
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switch (get_intid_range(d)) {
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case PPI_RANGE:
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/* SGI+PPI -> SGI_base for this CPU */
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return gic_data_rdist_sgi_base();
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if (d->hwirq <= 1023) /* SPI -> dist_base */
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case SPI_RANGE:
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/* SPI -> dist_base */
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return gic_data.dist_base;
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return NULL;
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default:
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return NULL;
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}
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}
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static void gic_do_wait_for_rwp(void __iomem *base)
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@ -196,24 +227,46 @@ static void gic_enable_redist(bool enable)
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/*
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* Routines to disable, enable, EOI and route interrupts
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*/
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static u32 convert_offset_index(struct irq_data *d, u32 offset, u32 *index)
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{
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switch (get_intid_range(d)) {
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case PPI_RANGE:
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case SPI_RANGE:
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*index = d->hwirq;
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return offset;
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default:
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break;
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}
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WARN_ON(1);
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*index = d->hwirq;
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return offset;
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}
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static int gic_peek_irq(struct irq_data *d, u32 offset)
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{
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u32 mask = 1 << (gic_irq(d) % 32);
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void __iomem *base;
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u32 index, mask;
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offset = convert_offset_index(d, offset, &index);
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mask = 1 << (index % 32);
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if (gic_irq_in_rdist(d))
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base = gic_data_rdist_sgi_base();
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else
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base = gic_data.dist_base;
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return !!(readl_relaxed(base + offset + (gic_irq(d) / 32) * 4) & mask);
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return !!(readl_relaxed(base + offset + (index / 32) * 4) & mask);
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}
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static void gic_poke_irq(struct irq_data *d, u32 offset)
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{
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u32 mask = 1 << (gic_irq(d) % 32);
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void (*rwp_wait)(void);
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void __iomem *base;
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u32 index, mask;
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offset = convert_offset_index(d, offset, &index);
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mask = 1 << (index % 32);
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if (gic_irq_in_rdist(d)) {
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base = gic_data_rdist_sgi_base();
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@ -223,7 +276,7 @@ static void gic_poke_irq(struct irq_data *d, u32 offset)
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rwp_wait = gic_dist_wait_for_rwp;
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}
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writel_relaxed(mask, base + offset + (gic_irq(d) / 32) * 4);
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writel_relaxed(mask, base + offset + (index / 32) * 4);
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rwp_wait();
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}
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@ -316,8 +369,11 @@ static int gic_irq_get_irqchip_state(struct irq_data *d,
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static void gic_irq_set_prio(struct irq_data *d, u8 prio)
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{
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void __iomem *base = gic_dist_base(d);
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u32 offset, index;
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writeb_relaxed(prio, base + GICD_IPRIORITYR + gic_irq(d));
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offset = convert_offset_index(d, GICD_IPRIORITYR, &index);
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writeb_relaxed(prio, base + offset + index);
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}
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static int gic_irq_nmi_setup(struct irq_data *d)
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@ -407,6 +463,7 @@ static int gic_set_type(struct irq_data *d, unsigned int type)
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unsigned int irq = gic_irq(d);
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void (*rwp_wait)(void);
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void __iomem *base;
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u32 offset, index;
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int ret;
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/* Interrupt configuration for SGIs can't be changed */
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@ -426,8 +483,9 @@ static int gic_set_type(struct irq_data *d, unsigned int type)
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rwp_wait = gic_dist_wait_for_rwp;
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}
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offset = convert_offset_index(d, GICD_ICFGR, &index);
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ret = gic_configure_irq(irq, type, base + GICD_ICFGR, rwp_wait);
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ret = gic_configure_irq(index, type, base + offset, rwp_wait);
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if (ret && irq < 32) {
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/* Misconfigured PPIs are usually not fatal */
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pr_warn("GIC: PPI%d is secure or misconfigured\n", irq - 16);
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@ -970,6 +1028,7 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
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bool force)
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{
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unsigned int cpu;
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u32 offset, index;
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void __iomem *reg;
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int enabled;
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u64 val;
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@ -990,7 +1049,8 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
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if (enabled)
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gic_mask_irq(d);
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reg = gic_dist_base(d) + GICD_IROUTER + (gic_irq(d) * 8);
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offset = convert_offset_index(d, GICD_IROUTER, &index);
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reg = gic_dist_base(d) + offset + (index * 8);
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val = gic_mpidr_to_affinity(cpu_logical_map(cpu));
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gic_write_irouter(val, reg);
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@ -1084,36 +1144,30 @@ static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
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if (static_branch_likely(&supports_deactivate_key))
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chip = &gic_eoimode1_chip;
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/* SGIs are private to the core kernel */
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if (hw < 16)
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return -EPERM;
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/* Nothing here */
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if (hw >= gic_data.irq_nr && hw < 8192)
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return -EPERM;
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/* Off limits */
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if (hw >= GIC_ID_NR)
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return -EPERM;
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/* PPIs */
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if (hw < 32) {
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switch (__get_intid_range(hw)) {
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case PPI_RANGE:
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irq_set_percpu_devid(irq);
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irq_domain_set_info(d, irq, hw, chip, d->host_data,
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handle_percpu_devid_irq, NULL, NULL);
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irq_set_status_flags(irq, IRQ_NOAUTOEN);
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}
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/* SPIs */
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if (hw >= 32 && hw < gic_data.irq_nr) {
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break;
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case SPI_RANGE:
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irq_domain_set_info(d, irq, hw, chip, d->host_data,
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handle_fasteoi_irq, NULL, NULL);
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irq_set_probe(irq);
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irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(irq)));
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}
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/* LPIs */
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if (hw >= 8192 && hw < GIC_ID_NR) {
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break;
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case LPI_RANGE:
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if (!gic_dist_supports_lpis())
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return -EPERM;
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irq_domain_set_info(d, irq, hw, chip, d->host_data,
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handle_fasteoi_irq, NULL, NULL);
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break;
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default:
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return -EPERM;
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}
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return 0;
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