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ARM: kill off set_irq_flags usage 

set_irq_flags is ARM specific with custom flags which have genirq
equivalents. Convert drivers to use the genirq interfaces directly, so we
can kill off set_irq_flags. The translation of flags is as follows:

IRQF_VALID -> !IRQ_NOREQUEST
IRQF_PROBE -> !IRQ_NOPROBE
IRQF_NOAUTOEN -> IRQ_NOAUTOEN

For IRQs managed by an irqdomain, the irqdomain core code handles clearing
and setting IRQ_NOREQUEST already, so there is no need to do this in
.map() functions and we can simply remove the set_irq_flags calls. Some
users also modify IRQ_NOPROBE and this has been maintained although it
is not clear that is really needed. There appears to be a great deal of
blind copy and paste of this code.

Signed-off-by: Rob Herring <robh@kernel.org>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Sekhar Nori <nsekhar@ti.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
Acked-by: Hans Ulli Kroll <ulli.kroll@googlemail.com>
Acked-by: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Imre Kaloz <kaloz@openwrt.org>
Acked-by: Krzysztof Halasa <khalasa@piap.pl>
Cc: Greg Ungerer <gerg@uclinux.org>
Cc: Roland Stigge <stigge@antcom.de>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Daniel Mack <daniel@zonque.org>
Cc: Haojian Zhuang <haojian.zhuang@gmail.com>
Cc: Robert Jarzmik <robert.jarzmik@free.fr>
Cc: Simtec Linux Team <linux@simtec.co.uk>
Cc: Kukjin Kim <kgene@kernel.org>
Cc: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Acked-by: Wan ZongShun <mcuos.com@gmail.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-omap@vger.kernel.org
Cc: linux-samsung-soc@vger.kernel.org
Tested-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Rob Herring 2015-07-27 15:55:13 -05:00 committed by Olof Johansson
parent 19c233b79d
commit e8d36d5dbb
35 changed files with 45 additions and 47 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/common/it8152.c
View File

@ -91,7 +91,7 @@ void it8152_init_irq(void)
for (irq = IT8152_IRQ(0); irq <= IT8152_LAST_IRQ; irq++) { for (irq = IT8152_IRQ(0); irq <= IT8152_LAST_IRQ; irq++) {
irq_set_chip_and_handler(irq, &it8152_irq_chip, irq_set_chip_and_handler(irq, &it8152_irq_chip,
handle_level_irq); handle_level_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
} }
} }

2
arch/arm/common/locomo.c
View File

@ -205,7 +205,7 @@ static void locomo_setup_irq(struct locomo *lchip)
for ( ; irq <= lchip->irq_base + 3; irq++) { for ( ; irq <= lchip->irq_base + 3; irq++) {
irq_set_chip_and_handler(irq, &locomo_chip, handle_level_irq); irq_set_chip_and_handler(irq, &locomo_chip, handle_level_irq);
irq_set_chip_data(irq, lchip); irq_set_chip_data(irq, lchip);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
} }
} }

4
arch/arm/common/sa1111.c
View File

@ -486,7 +486,7 @@ static int sa1111_setup_irq(struct sa1111 *sachip, unsigned irq_base)
irq_set_chip_and_handler(irq, &sa1111_low_chip, irq_set_chip_and_handler(irq, &sa1111_low_chip,
handle_edge_irq); handle_edge_irq);
irq_set_chip_data(irq, sachip); irq_set_chip_data(irq, sachip);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
} }
for (i = AUDXMTDMADONEA; i <= IRQ_S1_BVD1_STSCHG; i++) { for (i = AUDXMTDMADONEA; i <= IRQ_S1_BVD1_STSCHG; i++) {
@ -494,7 +494,7 @@ static int sa1111_setup_irq(struct sa1111 *sachip, unsigned irq_base)
irq_set_chip_and_handler(irq, &sa1111_high_chip, irq_set_chip_and_handler(irq, &sa1111_high_chip,
handle_edge_irq); handle_edge_irq);
irq_set_chip_data(irq, sachip); irq_set_chip_data(irq, sachip);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
} }
/* /*

2
arch/arm/mach-davinci/cp_intc.c
View File

@ -112,7 +112,7 @@ static int cp_intc_host_map(struct irq_domain *h, unsigned int virq,
pr_debug("cp_intc_host_map(%d, 0x%lx)\n", virq, hw); pr_debug("cp_intc_host_map(%d, 0x%lx)\n", virq, hw);
irq_set_chip(virq, &cp_intc_irq_chip); irq_set_chip(virq, &cp_intc_irq_chip);
set_irq_flags(virq, IRQF_VALID | IRQF_PROBE); irq_set_probe(virq);
irq_set_handler(virq, handle_edge_irq); irq_set_handler(virq, handle_edge_irq);
return 0; return 0;
} }

2
arch/arm/mach-dove/irq.c
View File

@ -172,7 +172,7 @@ void __init dove_init_irq(void)
for (i = IRQ_DOVE_PMU_START; i < NR_IRQS; i++) { for (i = IRQ_DOVE_PMU_START; i < NR_IRQS; i++) {
irq_set_chip_and_handler(i, &pmu_irq_chip, handle_level_irq); irq_set_chip_and_handler(i, &pmu_irq_chip, handle_level_irq);
irq_set_status_flags(i, IRQ_LEVEL); irq_set_status_flags(i, IRQ_LEVEL);
set_irq_flags(i, IRQF_VALID); irq_clear_status_flags(i, IRQ_NOREQUEST);
} }
irq_set_chained_handler(IRQ_DOVE_PMU, pmu_irq_handler); irq_set_chained_handler(IRQ_DOVE_PMU, pmu_irq_handler);
} }

2
arch/arm/mach-ebsa110/core.c
View File

@ -65,7 +65,7 @@ static void __init ebsa110_init_irq(void)
for (irq = 0; irq < NR_IRQS; irq++) { for (irq = 0; irq < NR_IRQS; irq++) {
irq_set_chip_and_handler(irq, &ebsa110_irq_chip, irq_set_chip_and_handler(irq, &ebsa110_irq_chip,
handle_level_irq); handle_level_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
} }
} }

2
arch/arm/mach-footbridge/common.c
View File

@ -106,7 +106,7 @@ static void __init __fb_init_irq(void)
for (irq = _DC21285_IRQ(0); irq < _DC21285_IRQ(20); irq++) { for (irq = _DC21285_IRQ(0); irq < _DC21285_IRQ(20); irq++) {
irq_set_chip_and_handler(irq, &fb_chip, handle_level_irq); irq_set_chip_and_handler(irq, &fb_chip, handle_level_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
} }
} }

8
arch/arm/mach-footbridge/isa-irq.c
View File

@ -153,13 +153,13 @@ void __init isa_init_irq(unsigned int host_irq)
for (irq = _ISA_IRQ(0); irq < _ISA_IRQ(8); irq++) { for (irq = _ISA_IRQ(0); irq < _ISA_IRQ(8); irq++) {
irq_set_chip_and_handler(irq, &isa_lo_chip, irq_set_chip_and_handler(irq, &isa_lo_chip,
handle_level_irq); handle_level_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
} }
for (irq = _ISA_IRQ(8); irq < _ISA_IRQ(16); irq++) { for (irq = _ISA_IRQ(8); irq < _ISA_IRQ(16); irq++) {
irq_set_chip_and_handler(irq, &isa_hi_chip, irq_set_chip_and_handler(irq, &isa_hi_chip,
handle_level_irq); handle_level_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
} }
request_resource(&ioport_resource, &pic1_resource); request_resource(&ioport_resource, &pic1_resource);
@ -175,8 +175,8 @@ void __init isa_init_irq(unsigned int host_irq)
* resistor on this line. * resistor on this line.
*/ */
if (machine_is_netwinder()) if (machine_is_netwinder())
set_irq_flags(_ISA_IRQ(11), IRQF_VALID | irq_modify_status(_ISA_IRQ(11),
IRQF_PROBE | IRQF_NOAUTOEN); IRQ_NOREQUEST | IRQ_NOPROBE, IRQ_NOAUTOEN);
} }
} }

2
arch/arm/mach-gemini/gpio.c
View File

@ -220,7 +220,7 @@ void __init gemini_gpio_init(void)
j < GPIO_IRQ_BASE + (i + 1) * 32; j++) { j < GPIO_IRQ_BASE + (i + 1) * 32; j++) {
irq_set_chip_and_handler(j, &gpio_irq_chip, irq_set_chip_and_handler(j, &gpio_irq_chip,
handle_edge_irq); handle_edge_irq);
set_irq_flags(j, IRQF_VALID); irq_clear_status_flags(j, IRQ_NOREQUEST);
} }
irq_set_chained_handler_and_data(IRQ_GPIO(i), gpio_irq_handler, irq_set_chained_handler_and_data(IRQ_GPIO(i), gpio_irq_handler,

2
arch/arm/mach-gemini/irq.c
View File

@ -92,7 +92,7 @@ void __init gemini_init_irq(void)
} else { } else {
irq_set_handler(i, handle_level_irq); irq_set_handler(i, handle_level_irq);
} }
set_irq_flags(i, IRQF_VALID | IRQF_PROBE); irq_clear_status_flags(i, IRQ_NOREQUEST | IRQ_NOPROBE);
} }
/* Disable all interrupts */ /* Disable all interrupts */

2
arch/arm/mach-imx/3ds_debugboard.c
View File

@ -195,7 +195,7 @@ int __init mxc_expio_init(u32 base, u32 intr_gpio)
for (i = irq_base; i < irq_base + MXC_MAX_EXP_IO_LINES; i++) { for (i = irq_base; i < irq_base + MXC_MAX_EXP_IO_LINES; i++) {
irq_set_chip_and_handler(i, &expio_irq_chip, handle_level_irq); irq_set_chip_and_handler(i, &expio_irq_chip, handle_level_irq);
set_irq_flags(i, IRQF_VALID); irq_clear_status_flags(i, IRQ_NOREQUEST);
} }
irq_set_irq_type(p_irq, IRQF_TRIGGER_LOW); irq_set_irq_type(p_irq, IRQF_TRIGGER_LOW);
irq_set_chained_handler(p_irq, mxc_expio_irq_handler); irq_set_chained_handler(p_irq, mxc_expio_irq_handler);

2
arch/arm/mach-imx/mach-mx31ads.c
View File

@ -238,7 +238,7 @@ static void __init mx31ads_init_expio(void)
for (i = irq_base; i < irq_base + MXC_MAX_EXP_IO_LINES; i++) { for (i = irq_base; i < irq_base + MXC_MAX_EXP_IO_LINES; i++) {
irq_set_chip_and_handler(i, &expio_irq_chip, handle_level_irq); irq_set_chip_and_handler(i, &expio_irq_chip, handle_level_irq);
set_irq_flags(i, IRQF_VALID); irq_clear_status_flags(i, IRQ_NOREQUEST);
} }
irq = gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_4)); irq = gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_4));
irq_set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH); irq_set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);

2
arch/arm/mach-iop13xx/irq.c
View File

@ -233,7 +233,7 @@ void __init iop13xx_init_irq(void)
irq_set_chip(i, &iop13xx_irqchip4); irq_set_chip(i, &iop13xx_irqchip4);
irq_set_handler(i, handle_level_irq); irq_set_handler(i, handle_level_irq);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE); irq_clear_status_flags(i, IRQ_NOREQUEST | IRQ_NOPROBE);
} }
iop13xx_msi_init(); iop13xx_msi_init();

2
arch/arm/mach-iop32x/irq.c
View File

@ -69,6 +69,6 @@ void __init iop32x_init_irq(void)
for (i = 0; i < NR_IRQS; i++) { for (i = 0; i < NR_IRQS; i++) {
irq_set_chip_and_handler(i, &ext_chip, handle_level_irq); irq_set_chip_and_handler(i, &ext_chip, handle_level_irq);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE); irq_clear_status_flags(i, IRQ_NOREQUEST | IRQ_NOPROBE);
} }
} }

2
arch/arm/mach-iop33x/irq.c
View File

@ -113,6 +113,6 @@ void __init iop33x_init_irq(void)
irq_set_chip_and_handler(i, irq_set_chip_and_handler(i,
(i < 32) ? &iop33x_irqchip1 : &iop33x_irqchip2, (i < 32) ? &iop33x_irqchip1 : &iop33x_irqchip2,
handle_level_irq); handle_level_irq);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE); irq_clear_status_flags(i, IRQ_NOREQUEST | IRQ_NOPROBE);
} }
} }

2
arch/arm/mach-ixp4xx/common.c
View File

@ -296,7 +296,7 @@ void __init ixp4xx_init_irq(void)
for(i = 0; i < NR_IRQS; i++) { for(i = 0; i < NR_IRQS; i++) {
irq_set_chip_and_handler(i, &ixp4xx_irq_chip, irq_set_chip_and_handler(i, &ixp4xx_irq_chip,
handle_level_irq); handle_level_irq);
set_irq_flags(i, IRQF_VALID); irq_clear_status_flags(i, IRQ_NOREQUEST);
} }
} }

2
arch/arm/mach-ks8695/irq.c
View File

@ -172,6 +172,6 @@ void __init ks8695_init_irq(void)
handle_edge_irq); handle_edge_irq);
} }
set_irq_flags(irq, IRQF_VALID); irq_clear_status_flags(irq, IRQ_NOREQUEST);
} }
} }

2
arch/arm/mach-lpc32xx/irq.c
View File

@ -434,7 +434,7 @@ void __init lpc32xx_init_irq(void)
for (i = 0; i < NR_IRQS; i++) { for (i = 0; i < NR_IRQS; i++) {
irq_set_chip_and_handler(i, &lpc32xx_irq_chip, irq_set_chip_and_handler(i, &lpc32xx_irq_chip,
handle_level_irq); handle_level_irq);
set_irq_flags(i, IRQF_VALID); irq_clear_status_flags(i, IRQ_NOREQUEST);
} }
/* Set default mappings */ /* Set default mappings */

2
arch/arm/mach-netx/generic.c
View File

@ -174,7 +174,7 @@ void __init netx_init_irq(void)
for (irq = NETX_IRQ_HIF_CHAINED(0); irq <= NETX_IRQ_HIF_LAST; irq++) { for (irq = NETX_IRQ_HIF_CHAINED(0); irq <= NETX_IRQ_HIF_LAST; irq++) {
irq_set_chip_and_handler(irq, &netx_hif_chip, irq_set_chip_and_handler(irq, &netx_hif_chip,
handle_level_irq); handle_level_irq);
set_irq_flags(irq, IRQF_VALID); irq_clear_status_flags(irq, IRQ_NOREQUEST);
} }
writel(NETX_DPMAS_INT_EN_GLB_EN, NETX_DPMAS_INT_EN); writel(NETX_DPMAS_INT_EN_GLB_EN, NETX_DPMAS_INT_EN);

2
arch/arm/mach-omap1/fpga.c
View File

@ -169,7 +169,7 @@ void omap1510_fpga_init_irq(void)
} }
irq_set_handler(i, handle_edge_irq); irq_set_handler(i, handle_edge_irq);
set_irq_flags(i, IRQF_VALID); irq_clear_status_flags(i, IRQ_NOREQUEST);
} }
/* /*

2
arch/arm/mach-omap1/irq.c
View File

@ -262,7 +262,7 @@ void __init omap1_init_irq(void)
irq_trigger = irq_banks[i].trigger_map >> IRQ_BIT(j); irq_trigger = irq_banks[i].trigger_map >> IRQ_BIT(j);
omap_irq_set_cfg(j, 0, 0, irq_trigger); omap_irq_set_cfg(j, 0, 0, irq_trigger);
set_irq_flags(j, IRQF_VALID); irq_clear_status_flags(j, IRQ_NOREQUEST);
} }
omap_alloc_gc(irq_banks[i].va, irq_base + i * 32, 32); omap_alloc_gc(irq_banks[i].va, irq_base + i * 32, 32);
} }

2
arch/arm/mach-pxa/balloon3.c
View File

@ -528,7 +528,7 @@ static void __init balloon3_init_irq(void)
for (irq = BALLOON3_IRQ(0); irq <= BALLOON3_IRQ(7); irq++) { for (irq = BALLOON3_IRQ(0); irq <= BALLOON3_IRQ(7); irq++) {
irq_set_chip_and_handler(irq, &balloon3_irq_chip, irq_set_chip_and_handler(irq, &balloon3_irq_chip,
handle_level_irq); handle_level_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
} }
irq_set_chained_handler(BALLOON3_AUX_NIRQ, balloon3_irq_handler); irq_set_chained_handler(BALLOON3_AUX_NIRQ, balloon3_irq_handler);

1
arch/arm/mach-pxa/irq.c
View File

@ -133,7 +133,6 @@ static int pxa_irq_map(struct irq_domain *h, unsigned int virq,
irq_set_chip_and_handler(virq, &pxa_internal_irq_chip, irq_set_chip_and_handler(virq, &pxa_internal_irq_chip,
handle_level_irq); handle_level_irq);
irq_set_chip_data(virq, base); irq_set_chip_data(virq, base);
set_irq_flags(virq, IRQF_VALID);
return 0; return 0;
} }

2
arch/arm/mach-pxa/lpd270.c
View File

@ -151,7 +151,7 @@ static void __init lpd270_init_irq(void)
for (irq = LPD270_IRQ(2); irq <= LPD270_IRQ(4); irq++) { for (irq = LPD270_IRQ(2); irq <= LPD270_IRQ(4); irq++) {
irq_set_chip_and_handler(irq, &lpd270_irq_chip, irq_set_chip_and_handler(irq, &lpd270_irq_chip,
handle_level_irq); handle_level_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
} }
irq_set_chained_handler(PXA_GPIO_TO_IRQ(0), lpd270_irq_handler); irq_set_chained_handler(PXA_GPIO_TO_IRQ(0), lpd270_irq_handler);
irq_set_irq_type(PXA_GPIO_TO_IRQ(0), IRQ_TYPE_EDGE_FALLING); irq_set_irq_type(PXA_GPIO_TO_IRQ(0), IRQ_TYPE_EDGE_FALLING);

2
arch/arm/mach-pxa/pcm990-baseboard.c
View File

@ -311,7 +311,7 @@ static void __init pcm990_init_irq(void)
for (irq = PCM027_IRQ(0); irq <= PCM027_IRQ(3); irq++) { for (irq = PCM027_IRQ(0); irq <= PCM027_IRQ(3); irq++) {
irq_set_chip_and_handler(irq, &pcm990_irq_chip, irq_set_chip_and_handler(irq, &pcm990_irq_chip,
handle_level_irq); handle_level_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
} }
/* disable all Interrupts */ /* disable all Interrupts */

2
arch/arm/mach-pxa/pxa3xx.c
View File

@ -325,7 +325,7 @@ static void __init pxa_init_ext_wakeup_irq(int (*fn)(struct irq_data *,
for (irq = IRQ_WAKEUP0; irq <= IRQ_WAKEUP1; irq++) { for (irq = IRQ_WAKEUP0; irq <= IRQ_WAKEUP1; irq++) {
irq_set_chip_and_handler(irq, &pxa_ext_wakeup_chip, irq_set_chip_and_handler(irq, &pxa_ext_wakeup_chip,
handle_edge_irq); handle_edge_irq);
set_irq_flags(irq, IRQF_VALID); irq_clear_status_flags(irq, IRQ_NOREQUEST);
} }
pxa_ext_wakeup_chip.irq_set_wake = fn; pxa_ext_wakeup_chip.irq_set_wake = fn;

2
arch/arm/mach-pxa/viper.c
View File

@ -313,7 +313,7 @@ static void __init viper_init_irq(void)
isa_irq = viper_bit_to_irq(level); isa_irq = viper_bit_to_irq(level);
irq_set_chip_and_handler(isa_irq, &viper_irq_chip, irq_set_chip_and_handler(isa_irq, &viper_irq_chip,
handle_edge_irq); handle_edge_irq);
set_irq_flags(isa_irq, IRQF_VALID | IRQF_PROBE); irq_clear_status_flags(isa_irq, IRQ_NOREQUEST | IRQ_NOPROBE);
} }
irq_set_chained_handler(gpio_to_irq(VIPER_CPLD_GPIO), irq_set_chained_handler(gpio_to_irq(VIPER_CPLD_GPIO),

2
arch/arm/mach-pxa/zeus.c
View File

@ -151,7 +151,7 @@ static void __init zeus_init_irq(void)
isa_irq = zeus_bit_to_irq(level); isa_irq = zeus_bit_to_irq(level);
irq_set_chip_and_handler(isa_irq, &zeus_irq_chip, irq_set_chip_and_handler(isa_irq, &zeus_irq_chip,
handle_edge_irq); handle_edge_irq);
set_irq_flags(isa_irq, IRQF_VALID | IRQF_PROBE); irq_clear_status_flags(isa_irq, IRQ_NOREQUEST | IRQ_NOPROBE);
} }
irq_set_irq_type(gpio_to_irq(ZEUS_ISA_GPIO), IRQ_TYPE_EDGE_RISING); irq_set_irq_type(gpio_to_irq(ZEUS_ISA_GPIO), IRQ_TYPE_EDGE_RISING);

2
arch/arm/mach-rpc/ecard.c
View File

@ -946,7 +946,7 @@ static int __init ecard_probe(int slot, unsigned irq, card_type_t type)
irq_set_chip_and_handler(ec->irq, &ecard_chip, irq_set_chip_and_handler(ec->irq, &ecard_chip,
handle_level_irq); handle_level_irq);
irq_set_chip_data(ec->irq, ec); irq_set_chip_data(ec->irq, ec);
set_irq_flags(ec->irq, IRQF_VALID); irq_clear_status_flags(ec->irq, IRQ_NOREQUEST);
} }
#ifdef CONFIG_ARCH_RPC #ifdef CONFIG_ARCH_RPC

16
arch/arm/mach-rpc/irq.c
View File

@ -117,7 +117,7 @@ extern unsigned char rpc_default_fiq_start, rpc_default_fiq_end;
void __init rpc_init_irq(void) void __init rpc_init_irq(void)
{ {
unsigned int irq, flags; unsigned int irq, clr, set = 0;
iomd_writeb(0, IOMD_IRQMASKA); iomd_writeb(0, IOMD_IRQMASKA);
iomd_writeb(0, IOMD_IRQMASKB); iomd_writeb(0, IOMD_IRQMASKB);
@ -128,37 +128,37 @@ void __init rpc_init_irq(void)
&rpc_default_fiq_end - &rpc_default_fiq_start); &rpc_default_fiq_end - &rpc_default_fiq_start);
for (irq = 0; irq < NR_IRQS; irq++) { for (irq = 0; irq < NR_IRQS; irq++) {
flags = IRQF_VALID; clr = IRQ_NOREQUEST;
if (irq <= 6 || (irq >= 9 && irq <= 15)) if (irq <= 6 || (irq >= 9 && irq <= 15))
flags |= IRQF_PROBE; clr |= IRQ_NOPROBE;
if (irq == 21 || (irq >= 16 && irq <= 19) || if (irq == 21 || (irq >= 16 && irq <= 19) ||
irq == IRQ_KEYBOARDTX) irq == IRQ_KEYBOARDTX)
flags |= IRQF_NOAUTOEN; set |= IRQ_NOAUTOEN;
switch (irq) { switch (irq) {
case 0 ... 7: case 0 ... 7:
irq_set_chip_and_handler(irq, &iomd_a_chip, irq_set_chip_and_handler(irq, &iomd_a_chip,
handle_level_irq); handle_level_irq);
set_irq_flags(irq, flags); irq_modify_status(irq, clr, set);
break; break;
case 8 ... 15: case 8 ... 15:
irq_set_chip_and_handler(irq, &iomd_b_chip, irq_set_chip_and_handler(irq, &iomd_b_chip,
handle_level_irq); handle_level_irq);
set_irq_flags(irq, flags); irq_modify_status(irq, clr, set);
break; break;
case 16 ... 21: case 16 ... 21:
irq_set_chip_and_handler(irq, &iomd_dma_chip, irq_set_chip_and_handler(irq, &iomd_dma_chip,
handle_level_irq); handle_level_irq);
set_irq_flags(irq, flags); irq_modify_status(irq, clr, set);
break; break;
case 64 ... 71: case 64 ... 71:
irq_set_chip(irq, &iomd_fiq_chip); irq_set_chip(irq, &iomd_fiq_chip);
set_irq_flags(irq, IRQF_VALID); irq_modify_status(irq, clr, set);
break; break;
} }
} }

2
arch/arm/mach-s3c24xx/bast-irq.c
View File

@ -147,7 +147,7 @@ static __init int bast_irq_init(void)
irq_set_chip_and_handler(irqno, &bast_pc104_chip, irq_set_chip_and_handler(irqno, &bast_pc104_chip,
handle_level_irq); handle_level_irq);
set_irq_flags(irqno, IRQF_VALID); irq_clear_status_flags(irqno, IRQ_NOREQUEST);
} }
} }

2
arch/arm/mach-s3c64xx/common.c
View File

@ -420,7 +420,7 @@ static int __init s3c64xx_init_irq_eint(void)
for (irq = IRQ_EINT(0); irq <= IRQ_EINT(27); irq++) { for (irq = IRQ_EINT(0); irq <= IRQ_EINT(27); irq++) {
irq_set_chip_and_handler(irq, &s3c_irq_eint, handle_level_irq); irq_set_chip_and_handler(irq, &s3c_irq_eint, handle_level_irq);
irq_set_chip_data(irq, (void *)eint_irq_to_bit(irq)); irq_set_chip_data(irq, (void *)eint_irq_to_bit(irq));
set_irq_flags(irq, IRQF_VALID); irq_clear_status_flags(irq, IRQ_NOREQUEST);
} }
irq_set_chained_handler(IRQ_EINT0_3, s3c_irq_demux_eint0_3); irq_set_chained_handler(IRQ_EINT0_3, s3c_irq_demux_eint0_3);

4
arch/arm/mach-sa1100/neponset.c
View File

@ -320,10 +320,10 @@ static int neponset_probe(struct platform_device *dev)
irq_set_chip_and_handler(d->irq_base + NEP_IRQ_SMC91X, &nochip, irq_set_chip_and_handler(d->irq_base + NEP_IRQ_SMC91X, &nochip,
handle_simple_irq); handle_simple_irq);
set_irq_flags(d->irq_base + NEP_IRQ_SMC91X, IRQF_VALID | IRQF_PROBE); irq_clear_status_flags(d->irq_base + NEP_IRQ_SMC91X, IRQ_NOREQUEST | IRQ_NOPROBE);
irq_set_chip_and_handler(d->irq_base + NEP_IRQ_USAR, &nochip, irq_set_chip_and_handler(d->irq_base + NEP_IRQ_USAR, &nochip,
handle_simple_irq); handle_simple_irq);
set_irq_flags(d->irq_base + NEP_IRQ_USAR, IRQF_VALID | IRQF_PROBE); irq_clear_status_flags(d->irq_base + NEP_IRQ_USAR, IRQ_NOREQUEST | IRQ_NOPROBE);
irq_set_chip(d->irq_base + NEP_IRQ_SA1111, &nochip); irq_set_chip(d->irq_base + NEP_IRQ_SA1111, &nochip);
irq_set_irq_type(irq, IRQ_TYPE_EDGE_RISING); irq_set_irq_type(irq, IRQ_TYPE_EDGE_RISING);

2
arch/arm/mach-w90x900/irq.c
View File

@ -211,6 +211,6 @@ void __init nuc900_init_irq(void)
for (irqno = IRQ_WDT; irqno <= IRQ_ADC; irqno++) { for (irqno = IRQ_WDT; irqno <= IRQ_ADC; irqno++) {
irq_set_chip_and_handler(irqno, &nuc900_irq_chip, irq_set_chip_and_handler(irqno, &nuc900_irq_chip,
handle_level_irq); handle_level_irq);
set_irq_flags(irqno, IRQF_VALID); irq_clear_status_flags(irqno, IRQ_NOREQUEST);
} }
} }

1
drivers/irqchip/irq-sa11x0.c
View File

@ -70,7 +70,6 @@ static int sa1100_normal_irqdomain_map(struct irq_domain *d,
{ {
irq_set_chip_and_handler(irq, &sa1100_normal_chip, irq_set_chip_and_handler(irq, &sa1100_normal_chip,
handle_level_irq); handle_level_irq);
set_irq_flags(irq, IRQF_VALID);
return 0; return 0;
} }