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MIPS: make PCI_DMA_BUS_IS_PHYS=1 constant 

No one of supported MIPS machines has an IOMMU unit, so we can safely define
PCI_DMA_BUS_IS_PHYS = 1. Also remove iommu flag from the pci controller
structure, since it is useless.

Signed-off-by: Sergey Ryazanov <ryazanov.s.a@gmail.com>
Cc: Linux MIPS <linux-mips@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/7604/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Sergey Ryazanov 2014-08-30 06:06:28 +04:00 committed by Ralf Baechle
parent 1e321fa917
commit e8b5325ca3
5 changed files with 4 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
arch/mips/include/asm/pci.h
View File

@ -43,8 +43,6 @@ struct pci_controller {
and XFree86. Eventually will be removed. */
unsigned int need_domain_info;
int iommu;
/* Optional access methods for reading/writing the bus number
of the PCI controller */
int (*get_busno)(void);
@ -106,11 +104,11 @@ static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
struct pci_dev;
/*
* The PCI address space does equal the physical memory address space. The
* networking and block device layers use this boolean for bounce buffer
* decisions. This is set if any hose does not have an IOMMU.
* The PCI address space does equal the physical memory address space.
* The networking and block device layers use this boolean for bounce
* buffer decisions.
*/
extern unsigned int PCI_DMA_BUS_IS_PHYS;
#define PCI_DMA_BUS_IS_PHYS (1)
#ifdef CONFIG_PCI_DOMAINS
#define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index

7
arch/mips/kernel/setup.c
View File

@ -51,13 +51,6 @@ EXPORT_SYMBOL(cpu_data);
struct screen_info screen_info;
#endif
/*
* Despite it's name this variable is even if we don't have PCI
*/
unsigned int PCI_DMA_BUS_IS_PHYS;
EXPORT_SYMBOL(PCI_DMA_BUS_IS_PHYS);
/*
* Setup information
*

1
arch/mips/pci/pci-ip32.c
View File

@ -116,7 +116,6 @@ static struct pci_controller mace_pci_controller = {
.pci_ops = &mace_pci_ops,
.mem_resource = &mace_pci_mem_resource,
.io_resource = &mace_pci_io_resource,
.iommu = 0,
.mem_offset = MACE_PCI_MEM_OFFSET,
.io_offset = 0,
.io_map_base = CKSEG1ADDR(MACEPCI_LOW_IO),

3
arch/mips/pci/pci.c
View File

@ -83,9 +83,6 @@ static void pcibios_scanbus(struct pci_controller *hose)
LIST_HEAD(resources);
struct pci_bus *bus;
if (!hose->iommu)
PCI_DMA_BUS_IS_PHYS = 1;
if (hose->get_busno && pci_has_flag(PCI_PROBE_ONLY))
next_busno = (*hose->get_busno)();

3
arch/mips/pnx833x/common/setup.c
View File

@ -38,9 +38,6 @@ extern void pnx833x_machine_power_off(void);
int __init plat_mem_setup(void)
{
/* fake pci bus to avoid bounce buffers */
PCI_DMA_BUS_IS_PHYS = 1;
/* set mips clock to 320MHz */
#if defined(CONFIG_SOC_PNX8335)
PNX8335_WRITEFIELD(0x17, CLOCK_PLL_CPU_CTL, FREQ);