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ARM: 8443/1: Adding support for atomic half word exchange 

Since support for half-word atomic exchange was not there and Qspinlock
on ARM requires it, modified __xchg() to add support for that as well.
ARMv6 and lower does not support ldrex{b,h} so, added a guard code to
prevent build breaks.

Signed-off-by: Sarbojit Ganguly <ganguly.s@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Sarbojit Ganguly 2015-10-09 12:10:02 +01:00 committed by Russell King
parent e1b8c05dcc
commit e8973a889e
1 changed files with 12 additions and 0 deletions
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12
arch/arm/include/asm/cmpxchg.h
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@ -39,6 +39,7 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size
switch (size) { switch (size) {
#if __LINUX_ARM_ARCH__ >= 6 #if __LINUX_ARM_ARCH__ >= 6
#ifndef CONFIG_CPU_V6 /* MIN ARCH >= V6K */
case 1: case 1:
asm volatile("@ __xchg1\n" asm volatile("@ __xchg1\n"
"1: ldrexb %0, [%3]\n" "1: ldrexb %0, [%3]\n"
@ -49,6 +50,17 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size
: "r" (x), "r" (ptr) : "r" (x), "r" (ptr)
: "memory", "cc"); : "memory", "cc");
break; break;
case 2:
asm volatile("@ __xchg2\n"
"1: ldrexh %0, [%3]\n"
" strexh %1, %2, [%3]\n"
" teq %1, #0\n"
" bne 1b"
: "=&r" (ret), "=&r" (tmp)
: "r" (x), "r" (ptr)
: "memory", "cc");
break;
#endif
case 4: case 4:
asm volatile("@ __xchg4\n" asm volatile("@ __xchg4\n"
"1: ldrex %0, [%3]\n" "1: ldrex %0, [%3]\n"