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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc 

* 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc: (408 commits)
  [POWERPC] Add memchr() to the bootwrapper
  [POWERPC] Implement logging of unhandled signals
  [POWERPC] Add legacy serial support for OPB with flattened device tree
  [POWERPC] Use 1TB segments
  [POWERPC] XilinxFB: Allow fixed framebuffer base address
  [POWERPC] XilinxFB: Add support for custom screen resolution
  [POWERPC] XilinxFB: Use pdata to pass around framebuffer parameters
  [POWERPC] PCI: Add 64-bit physical address support to setup_indirect_pci
  [POWERPC] 4xx: Kilauea defconfig file
  [POWERPC] 4xx: Kilauea DTS
  [POWERPC] 4xx: Add AMCC Kilauea eval board support to platforms/40x
  [POWERPC] 4xx: Add AMCC 405EX support to cputable.c
  [POWERPC] Adjust TASK_SIZE on ppc32 systems to 3GB that are capable
  [POWERPC] Use PAGE_OFFSET to tell if an address is user/kernel in SW TLB handlers
  [POWERPC] 85xx: Enable FP emulation in MPC8560 ADS defconfig
  [POWERPC] 85xx: Killed <asm/mpc85xx.h>
  [POWERPC] 85xx: Add cpm nodes for 8541/8555 CDS
  [POWERPC] 85xx: Convert mpc8560ads to the new CPM binding.
  [POWERPC] mpc8272ads: Remove muram from the CPM reg property.
  [POWERPC] Make clockevents work on PPC601 processors
  ...

Fixed up conflict in Documentation/powerpc/booting-without-of.txt manually.
This commit is contained in:
Linus Torvalds 2007-10-11 21:55:47 -07:00
parent 5473074209 9b4b8feb96
commit e86908614f
529 changed files with 31146 additions and 13497 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

330
Documentation/powerpc/booting-without-of.txt
View File

@ -50,7 +50,7 @@ Table of Contents
g) Freescale SOC SEC Security Engines
h) Board Control and Status (BCSR)
i) Freescale QUICC Engine module (QE)
j) Flash chip nodes
j) CFI or JEDEC memory-mapped NOR flash
k) Global Utilities Block
VII - Specifying interrupt information for devices
@ -1510,7 +1510,10 @@ platforms are moved over to use the flattened-device-tree model.
i) Freescale QUICC Engine module (QE)
This represents qe module that is installed on PowerQUICC II Pro.
Hopefully it will merge backward compatibility with CPM/CPM2.
NOTE: This is an interim binding; it should be updated to fit
in with the CPM binding later in this document.
Basically, it is a bus of devices, that could act more or less
as a complete entity (UCC, USB etc ). All of them should be siblings on
the "root" qe node, using the common properties from there.
@ -1548,7 +1551,7 @@ platforms are moved over to use the flattened-device-tree model.
Required properties:
- device_type : should be "spi".
- compatible : should be "fsl_spi".
- mode : the SPI operation mode, it can be "cpu" or "qe".
- mode : the SPI operation mode, it can be "cpu" or "cpu-qe".
- reg : Offset and length of the register set for the device
- interrupts : <a b> where a is the interrupt number and b is a
field that represents an encoding of the sense and level
@ -1757,45 +1760,69 @@ platforms are moved over to use the flattened-device-tree model.
};
};
j) Flash chip nodes
j) CFI or JEDEC memory-mapped NOR flash
Flash chips (Memory Technology Devices) are often used for solid state
file systems on embedded devices.
Required properties:
- compatible : should contain the specific model of flash chip(s)
used, if known, followed by either "cfi-flash" or "jedec-flash"
- reg : Address range of the flash chip
- bank-width : Width (in bytes) of the flash bank. Equal to the
device width times the number of interleaved chips.
- device-width : (optional) Width of a single flash chip. If
omitted, assumed to be equal to 'bank-width'.
- #address-cells, #size-cells : Must be present if the flash has
sub-nodes representing partitions (see below). In this case
both #address-cells and #size-cells must be equal to 1.
- device_type : has to be "rom"
- compatible : Should specify what this flash device is compatible with.
Currently, this is most likely to be "direct-mapped" (which
corresponds to the MTD physmap mapping driver).
- reg : Offset and length of the register set (or memory mapping) for
the device.
- bank-width : Width of the flash data bus in bytes. Required
for the NOR flashes (compatible == "direct-mapped" and others) ONLY.
For JEDEC compatible devices, the following additional properties
are defined:
Recommended properties :
- vendor-id : Contains the flash chip's vendor id (1 byte).
- device-id : Contains the flash chip's device id (1 byte).
- partitions : Several pairs of 32-bit values where the first value is
partition's offset from the start of the device and the second one is
partition size in bytes with LSB used to signify a read only
partition (so, the partition size should always be an even number).
- partition-names : The list of concatenated zero terminated strings
representing the partition names.
- probe-type : The type of probe which should be done for the chip
(JEDEC vs CFI actually). Valid ONLY for NOR flashes.
In addition to the information on the flash bank itself, the
device tree may optionally contain additional information
describing partitions of the flash address space. This can be
used on platforms which have strong conventions about which
portions of the flash are used for what purposes, but which don't
use an on-flash partition table such as RedBoot.
Example:
Each partition is represented as a sub-node of the flash device.
Each node's name represents the name of the corresponding
partition of the flash device.
flash@ff000000 {
device_type = "rom";
compatible = "direct-mapped";
probe-type = "CFI";
reg = <ff000000 01000000>;
bank-width = <4>;
partitions = <00000000 00f80000
00f80000 00080001>;
partition-names = "fs\0firmware";
};
Flash partitions
- reg : The partition's offset and size within the flash bank.
- label : (optional) The label / name for this flash partition.
If omitted, the label is taken from the node name (excluding
the unit address).
- read-only : (optional) This parameter, if present, is a hint to
Linux that this flash partition should only be mounted
read-only. This is usually used for flash partitions
containing early-boot firmware images or data which should not
be clobbered.
Example:
flash@ff000000 {
compatible = "amd,am29lv128ml", "cfi-flash";
reg = <ff000000 01000000>;
bank-width = <4>;
device-width = <1>;
#address-cells = <1>;
#size-cells = <1>;
fs@0 {
label = "fs";
reg = <0 f80000>;
};
firmware@f80000 {
label ="firmware";
reg = <f80000 80000>;
read-only;
};
};
k) Global Utilities Block
@ -1824,8 +1851,243 @@ platforms are moved over to use the flattened-device-tree model.
fsl,has-rstcr;
};
l) Freescale Communications Processor Module
h) 4xx/Axon EMAC ethernet nodes
NOTE: This is an interim binding, and will likely change slightly,
as more devices are supported. The QE bindings especially are
incomplete.
i) Root CPM node
Properties:
- compatible : "fsl,cpm1", "fsl,cpm2", or "fsl,qe".
- reg : A 48-byte region beginning with CPCR.
Example:
cpm@119c0 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
compatible = "fsl,mpc8272-cpm", "fsl,cpm2";
reg = <119c0 30>;
}
ii) Properties common to mulitple CPM/QE devices
- fsl,cpm-command : This value is ORed with the opcode and command flag
to specify the device on which a CPM command operates.
- fsl,cpm-brg : Indicates which baud rate generator the device
is associated with. If absent, an unused BRG
should be dynamically allocated. If zero, the
device uses an external clock rather than a BRG.
- reg : Unless otherwise specified, the first resource represents the
scc/fcc/ucc registers, and the second represents the device's
parameter RAM region (if it has one).
iii) Serial
Currently defined compatibles:
- fsl,cpm1-smc-uart
- fsl,cpm2-smc-uart
- fsl,cpm1-scc-uart
- fsl,cpm2-scc-uart
- fsl,qe-uart
Example:
serial@11a00 {
device_type = "serial";
compatible = "fsl,mpc8272-scc-uart",
"fsl,cpm2-scc-uart";
reg = <11a00 20 8000 100>;
interrupts = <28 8>;
interrupt-parent = <&PIC>;
fsl,cpm-brg = <1>;
fsl,cpm-command = <00800000>;
};
iii) Network
Currently defined compatibles:
- fsl,cpm1-scc-enet
- fsl,cpm2-scc-enet
- fsl,cpm1-fec-enet
- fsl,cpm2-fcc-enet (third resource is GFEMR)
- fsl,qe-enet
Example:
ethernet@11300 {
device_type = "network";
compatible = "fsl,mpc8272-fcc-enet",
"fsl,cpm2-fcc-enet";
reg = <11300 20 8400 100 11390 1>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <20 8>;
interrupt-parent = <&PIC>;
phy-handle = <&PHY0>;
linux,network-index = <0>;
fsl,cpm-command = <12000300>;
};
iv) MDIO
Currently defined compatibles:
fsl,pq1-fec-mdio (reg is same as first resource of FEC device)
fsl,cpm2-mdio-bitbang (reg is port C registers)
Properties for fsl,cpm2-mdio-bitbang:
fsl,mdio-pin : pin of port C controlling mdio data
fsl,mdc-pin : pin of port C controlling mdio clock
Example:
mdio@10d40 {
device_type = "mdio";
compatible = "fsl,mpc8272ads-mdio-bitbang",
"fsl,mpc8272-mdio-bitbang",
"fsl,cpm2-mdio-bitbang";
reg = <10d40 14>;
#address-cells = <1>;
#size-cells = <0>;
fsl,mdio-pin = <12>;
fsl,mdc-pin = <13>;
};
v) Baud Rate Generators
Currently defined compatibles:
fsl,cpm-brg
fsl,cpm1-brg
fsl,cpm2-brg
Properties:
- reg : There may be an arbitrary number of reg resources; BRG
numbers are assigned to these in order.
- clock-frequency : Specifies the base frequency driving
the BRG.
Example:
brg@119f0 {
compatible = "fsl,mpc8272-brg",
"fsl,cpm2-brg",
"fsl,cpm-brg";
reg = <119f0 10 115f0 10>;
clock-frequency = <d#25000000>;
};
vi) Interrupt Controllers
Currently defined compatibles:
- fsl,cpm1-pic
- only one interrupt cell
- fsl,pq1-pic
- fsl,cpm2-pic
- second interrupt cell is level/sense:
- 2 is falling edge
- 8 is active low
Example:
interrupt-controller@10c00 {
#interrupt-cells = <2>;
interrupt-controller;
reg = <10c00 80>;
compatible = "mpc8272-pic", "fsl,cpm2-pic";
};
vii) USB (Universal Serial Bus Controller)
Properties:
- compatible : "fsl,cpm1-usb", "fsl,cpm2-usb", "fsl,qe-usb"
Example:
usb@11bc0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,cpm2-usb";
reg = <11b60 18 8b00 100>;
interrupts = <b 8>;
interrupt-parent = <&PIC>;
fsl,cpm-command = <2e600000>;
};
viii) Multi-User RAM (MURAM)
The multi-user/dual-ported RAM is expressed as a bus under the CPM node.
Ranges must be set up subject to the following restrictions:
- Children's reg nodes must be offsets from the start of all muram, even
if the user-data area does not begin at zero.
- If multiple range entries are used, the difference between the parent
address and the child address must be the same in all, so that a single
mapping can cover them all while maintaining the ability to determine
CPM-side offsets with pointer subtraction. It is recommended that
multiple range entries not be used.
- A child address of zero must be translatable, even if no reg resources
contain it.
A child "data" node must exist, compatible with "fsl,cpm-muram-data", to
indicate the portion of muram that is usable by the OS for arbitrary
purposes. The data node may have an arbitrary number of reg resources,
all of which contribute to the allocatable muram pool.
Example, based on mpc8272:
muram@0 {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 10000>;
data@0 {
compatible = "fsl,cpm-muram-data";
reg = <0 2000 9800 800>;
};
};
m) Chipselect/Local Bus
Properties:
- name : Should be localbus
- #address-cells : Should be either two or three. The first cell is the
chipselect number, and the remaining cells are the
offset into the chipselect.
- #size-cells : Either one or two, depending on how large each chipselect
can be.
- ranges : Each range corresponds to a single chipselect, and cover
the entire access window as configured.
Example:
localbus@f0010100 {
compatible = "fsl,mpc8272ads-localbus",
"fsl,mpc8272-localbus",
"fsl,pq2-localbus";
#address-cells = <2>;
#size-cells = <1>;
reg = <f0010100 40>;
ranges = <0 0 fe000000 02000000
1 0 f4500000 00008000>;
flash@0,0 {
compatible = "jedec-flash";
reg = <0 0 2000000>;
bank-width = <4>;
device-width = <1>;
};
board-control@1,0 {
reg = <1 0 20>;
compatible = "fsl,mpc8272ads-bcsr";
};
};
n) 4xx/Axon EMAC ethernet nodes
The EMAC ethernet controller in IBM and AMCC 4xx chips, and also
the Axon bridge. To operate this needs to interact with a ths

29
MAINTAINERS
View File

@ -1535,7 +1535,7 @@ P: Pantelis Antoniou
M: pantelis.antoniou@gmail.com
P: Vitaly Bordug
M: vbordug@ru.mvista.com
L: linuxppc-embedded@ozlabs.org
L: linuxppc-dev@ozlabs.org
L: netdev@vger.kernel.org
S: Maintained
@ -1543,14 +1543,14 @@ FREESCALE HIGHSPEED USB DEVICE DRIVER
P: Li Yang
M: leoli@freescale.com
L: linux-usb-devel@lists.sourceforge.net
L: linuxppc-embedded@ozlabs.org
L: linuxppc-dev@ozlabs.org
S: Maintained
FREESCALE QUICC ENGINE UCC ETHERNET DRIVER
P: Li Yang
M: leoli@freescale.com
L: netdev@vger.kernel.org
L: linuxppc-embedded@ozlabs.org
L: linuxppc-dev@ozlabs.org
S: Maintained
FILE LOCKING (flock() and fcntl()/lockf())
@ -2297,38 +2297,49 @@ S: Maintained
LINUX FOR POWERPC EMBEDDED MPC52XX
P: Sylvain Munaut
M: tnt@246tNt.com
P: Grant Likely
M: grant.likely@secretlab.ca
W: http://www.246tNt.com/mpc52xx/
W: http://www.penguinppc.org/
L: linuxppc-dev@ozlabs.org
L: linuxppc-embedded@ozlabs.org
S: Maintained
LINUX FOR POWERPC EMBEDDED PPC4XX
P: Josh Boyer
M: jwboyer@linux.vnet.ibm.com
P: Matt Porter
M: mporter@kernel.crashing.org
W: http://www.penguinppc.org/
L: linuxppc-embedded@ozlabs.org
L: linuxppc-dev@ozlabs.org
T: git kernel.org:/pub/scm/linux/kernel/git/jwboyer/powerpc.git
S: Maintained
LINUX FOR POWERPC EMBEDDED XILINX VIRTEX
P: Grant Likely
M: grant.likely@secretlab.ca
W: http://wiki.secretlab.ca/index.php/Linux_on_Xilinx_Virtex
L: linuxppc-dev@ozlabs.org
S: Maintained
LINUX FOR POWERPC BOOT CODE
P: Tom Rini
M: trini@kernel.crashing.org
W: http://www.penguinppc.org/
L: linuxppc-embedded@ozlabs.org
L: linuxppc-dev@ozlabs.org
S: Maintained
LINUX FOR POWERPC EMBEDDED PPC8XX
P: Marcelo Tosatti
M: marcelo@kvack.org
W: http://www.penguinppc.org/
L: linuxppc-embedded@ozlabs.org
L: linuxppc-dev@ozlabs.org
S: Maintained
LINUX FOR POWERPC EMBEDDED PPC83XX AND PPC85XX
P: Kumar Gala
M: galak@kernel.crashing.org
W: http://www.penguinppc.org/
L: linuxppc-embedded@ozlabs.org
L: linuxppc-dev@ozlabs.org
S: Maintained
LINUX FOR POWERPC PA SEMI PWRFICIENT
@ -2990,7 +3001,7 @@ POWERPC 4xx EMAC DRIVER
P: Eugene Surovegin
M: ebs@ebshome.net
W: http://kernel.ebshome.net/emac/
L: linuxppc-embedded@ozlabs.org
L: linuxppc-dev@ozlabs.org
L: netdev@vger.kernel.org
S: Maintained

50
arch/powerpc/Kconfig
View File

@ -14,6 +14,11 @@ config 64BIT
bool
default y if PPC64
config WORD_SIZE
int
default 64 if PPC64
default 32 if !PPC64
config PPC_MERGE
def_bool y
@ -21,6 +26,18 @@ config MMU
bool
default y
config GENERIC_CMOS_UPDATE
def_bool y
config GENERIC_TIME
def_bool y
config GENERIC_TIME_VSYSCALL
def_bool y
config GENERIC_CLOCKEVENTS
def_bool y
config GENERIC_HARDIRQS
bool
default y
@ -156,6 +173,7 @@ config HIGHMEM
bool "High memory support"
depends on PPC32
source kernel/time/Kconfig
source kernel/Kconfig.hz
source kernel/Kconfig.preempt
source "fs/Kconfig.binfmt"
@ -180,17 +198,29 @@ config MATH_EMULATION
unit, which will allow programs that use floating-point
instructions to run.
config 8XX_MINIMAL_FPEMU
bool "Minimal math emulation for 8xx"
depends on 8xx && !MATH_EMULATION
help
Older arch/ppc kernels still emulated a few floating point
instructions such as load and store, even when full math
emulation is disabled. Say "Y" here if you want to preserve
this behavior.
It is recommended that you build a soft-float userspace instead.
config IOMMU_VMERGE
bool "Enable IOMMU virtual merging (EXPERIMENTAL)"
depends on EXPERIMENTAL && PPC64
default n
bool "Enable IOMMU virtual merging"
depends on PPC64
default y
help
Cause IO segments sent to a device for DMA to be merged virtually
by the IOMMU when they happen to have been allocated contiguously.
This doesn't add pressure to the IOMMU allocator. However, some
drivers don't support getting large merged segments coming back
from *_map_sg(). Say Y if you know the drivers you are using are
properly handling this case.
from *_map_sg().
Most drivers don't have this problem; it is safe to say Y here.
config HOTPLUG_CPU
bool "Support for enabling/disabling CPUs"
@ -465,7 +495,7 @@ config PCI_8260
config 8260_PCI9
bool "Enable workaround for MPC826x erratum PCI 9"
depends on PCI_8260 && !ADS8272
depends on PCI_8260 && !8272
default y
choice
@ -569,7 +599,8 @@ config TASK_SIZE_BOOL
config TASK_SIZE
hex "Size of user task space" if TASK_SIZE_BOOL
default "0x80000000"
default "0x80000000" if PPC_PREP || PPC_8xx
default "0xc0000000"
config CONSISTENT_START_BOOL
bool "Set custom consistent memory pool address"
@ -581,6 +612,7 @@ config CONSISTENT_START_BOOL
config CONSISTENT_START
hex "Base virtual address of consistent memory pool" if CONSISTENT_START_BOOL
default "0xfd000000" if (NOT_COHERENT_CACHE && 8xx)
default "0xff100000" if NOT_COHERENT_CACHE
config CONSISTENT_SIZE_BOOL
@ -662,3 +694,7 @@ config KEYS_COMPAT
default y
source "crypto/Kconfig"
config PPC_CLOCK
bool
default n

31
arch/powerpc/Kconfig.debug
View File

@ -124,6 +124,16 @@ config IRQSTACKS
for handling hard and soft interrupts. This can help avoid
overflowing the process kernel stacks.
config VIRQ_DEBUG
bool "Expose hardware/virtual IRQ mapping via debugfs"
depends on DEBUG_FS && PPC_MERGE
help
This option will show the mapping relationship between hardware irq
numbers and virtual irq numbers. The mapping is exposed via debugfs
in the file powerpc/virq_mapping.
If you don't know what this means you don't need it.
config BDI_SWITCH
bool "Include BDI-2000 user context switcher"
depends on DEBUG_KERNEL && PPC32
@ -211,6 +221,15 @@ config PPC_EARLY_DEBUG_44x
Select this to enable early debugging for IBM 44x chips via the
inbuilt serial port.
config PPC_EARLY_DEBUG_CPM
bool "Early serial debugging for Freescale CPM-based serial ports"
depends on SERIAL_CPM
select PIN_TLB if PPC_8xx
help
Select this to enable early debugging for Freescale chips
using a CPM-based serial port. This assumes that the bootwrapper
has run, and set up the CPM in a particular way.
endchoice
config PPC_EARLY_DEBUG_44x_PHYSLOW
@ -223,4 +242,16 @@ config PPC_EARLY_DEBUG_44x_PHYSHIGH
depends PPC_EARLY_DEBUG_44x
default "0x1"
config PPC_EARLY_DEBUG_CPM_ADDR
hex "CPM UART early debug transmit descriptor address"
depends on PPC_EARLY_DEBUG_CPM
default "0xfa202008" if PPC_EP88XC
default "0xf0000008" if CPM2
default "0xff002008" if CPM1
help
This specifies the address of the transmit descriptor
used for early debug output. Because it is needed before
platform probing is done, all platforms selected must
share the same address.
endmenu

56
arch/powerpc/Makefile
View File

@ -35,11 +35,14 @@ endif
export CROSS32CC CROSS32AS CROSS32LD CROSS32AR CROSS32OBJCOPY
ifeq ($(CROSS_COMPILE),)
KBUILD_DEFCONFIG := $(shell uname -m)_defconfig
else
KBUILD_DEFCONFIG := ppc64_defconfig
endif
ifeq ($(CONFIG_PPC64),y)
OLDARCH := ppc64
SZ := 64
new_nm := $(shell if $(NM) --help 2>&1 | grep -- '--synthetic' > /dev/null; then echo y; else echo n; fi)
@ -49,22 +52,26 @@ endif
else
OLDARCH := ppc
SZ := 32
endif
# It seems there are times we use this Makefile without
# including the config file, but this replicates the old behaviour
ifeq ($(CONFIG_WORD_SIZE),)
CONFIG_WORD_SIZE := 32
endif
UTS_MACHINE := $(OLDARCH)
ifeq ($(HAS_BIARCH),y)
override AS += -a$(SZ)
override LD += -m elf$(SZ)ppc
override CC += -m$(SZ)
override AR := GNUTARGET=elf$(SZ)-powerpc $(AR)
override AS += -a$(CONFIG_WORD_SIZE)
override LD += -m elf$(CONFIG_WORD_SIZE)ppc
override CC += -m$(CONFIG_WORD_SIZE)
override AR := GNUTARGET=elf$(CONFIG_WORD_SIZE)-powerpc $(AR)
endif
LDFLAGS_vmlinux := -Bstatic
# The -Iarch/$(ARCH)/include is temporary while we are merging
CPPFLAGS-$(CONFIG_PPC32) := -Iarch/$(ARCH) -Iarch/$(ARCH)/include
CPPFLAGS-$(CONFIG_PPC32) := -Iarch/$(ARCH)
AFLAGS-$(CONFIG_PPC32) := -Iarch/$(ARCH)
CFLAGS-$(CONFIG_PPC64) := -mminimal-toc -mtraceback=none -mcall-aixdesc
CFLAGS-$(CONFIG_PPC32) := -Iarch/$(ARCH) -ffixed-r2 -mmultiple
@ -72,11 +79,8 @@ CPPFLAGS += $(CPPFLAGS-y)
AFLAGS += $(AFLAGS-y)
CFLAGS += -msoft-float -pipe $(CFLAGS-y)
CPP = $(CC) -E $(CFLAGS)
# Temporary hack until we have migrated to asm-powerpc
LINUXINCLUDE-$(CONFIG_PPC32) := -Iarch/$(ARCH)/include
LINUXINCLUDE += $(LINUXINCLUDE-y)
CHECKFLAGS += -m$(SZ) -D__powerpc__ -D__powerpc$(SZ)__
CHECKFLAGS += -m$(CONFIG_WORD_SIZE) -D__powerpc__ -D__powerpc$(CONFIG_WORD_SIZE)__
ifeq ($(CONFIG_PPC64),y)
GCC_BROKEN_VEC := $(shell if [ $(call cc-version) -lt 0400 ] ; then echo "y"; fi)
@ -96,6 +100,10 @@ else
endif
endif
ifeq ($(CONFIG_TUNE_CELL),y)
CFLAGS += $(call cc-option,-mtune=cell)
endif
# No AltiVec instruction when building kernel
CFLAGS += $(call cc-option,-mno-altivec)
@ -120,10 +128,9 @@ cpu-as-$(CONFIG_E200) += -Wa,-me200
AFLAGS += $(cpu-as-y)
CFLAGS += $(cpu-as-y)
head-y := arch/powerpc/kernel/head_32.o
head-$(CONFIG_PPC64) := arch/powerpc/kernel/head_64.o
head-y := arch/powerpc/kernel/head_$(CONFIG_WORD_SIZE).o
head-$(CONFIG_8xx) := arch/powerpc/kernel/head_8xx.o
head-$(CONFIG_4xx) := arch/powerpc/kernel/head_4xx.o
head-$(CONFIG_40x) := arch/powerpc/kernel/head_40x.o
head-$(CONFIG_44x) := arch/powerpc/kernel/head_44x.o
head-$(CONFIG_FSL_BOOKE) := arch/powerpc/kernel/head_fsl_booke.o
@ -166,25 +173,20 @@ define archhelp
@echo ' *_defconfig - Select default config from arch/$(ARCH)/configs'
endef
install:
install: vdso_install
$(Q)$(MAKE) $(build)=$(boot) BOOTIMAGE=$(KBUILD_IMAGE) install
vdso_install:
ifeq ($(CONFIG_PPC64),y)
$(Q)$(MAKE) $(build)=arch/$(ARCH)/kernel/vdso64 $@
endif
$(Q)$(MAKE) $(build)=arch/$(ARCH)/kernel/vdso32 $@
archclean:
$(Q)$(MAKE) $(clean)=$(boot)
archmrproper:
$(Q)rm -rf arch/$(ARCH)/include
archprepare: checkbin
ifeq ($(CONFIG_PPC32),y)
# Temporary hack until we have migrated to asm-powerpc
include/asm: arch/$(ARCH)/include/asm
arch/$(ARCH)/include/asm: FORCE
$(Q)if [ ! -d arch/$(ARCH)/include ]; then mkdir -p arch/$(ARCH)/include; fi
$(Q)ln -fsn $(srctree)/include/asm-$(OLDARCH) arch/$(ARCH)/include/asm
endif
# Use the file '.tmp_gas_check' for binutils tests, as gas won't output
# to stdout and these checks are run even on install targets.
TOUT := .tmp_gas_check

9
arch/powerpc/boot/.gitignore vendored
View File

@ -18,14 +18,15 @@ kernel-vmlinux.strip.c
kernel-vmlinux.strip.gz
mktree
uImage
cuImage
cuImage.bin.gz
cuImage.elf
cuImage.*
treeImage.*
zImage
zImage.bin.*
zImage.chrp
zImage.coff
zImage.coff.lds
zImage.lds
zImage.ep*
zImage.*lds
zImage.miboot
zImage.pmac
zImage.pseries

85
arch/powerpc/boot/44x.c
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@ -1,85 +0,0 @@
/*
* Copyright 2007 David Gibson, IBM Corporation.
*
* Based on earlier code:
* Matt Porter <mporter@kernel.crashing.org>
* Copyright 2002-2005 MontaVista Software Inc.
*
* Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
* Copyright (c) 2003, 2004 Zultys Technologies
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#include <stddef.h>
#include "types.h"
#include "string.h"
#include "stdio.h"
#include "ops.h"
#include "reg.h"
#include "dcr.h"
/* Read the 44x memory controller to get size of system memory. */
void ibm44x_fixup_memsize(void)
{
int i;
unsigned long memsize, bank_config;
memsize = 0;
for (i = 0; i < ARRAY_SIZE(sdram_bxcr); i++) {
mtdcr(DCRN_SDRAM0_CFGADDR, sdram_bxcr[i]);
bank_config = mfdcr(DCRN_SDRAM0_CFGDATA);
if (bank_config & SDRAM_CONFIG_BANK_ENABLE)
memsize += SDRAM_CONFIG_BANK_SIZE(bank_config);
}
dt_fixup_memory(0, memsize);
}
#define SPRN_DBCR0 0x134
#define DBCR0_RST_SYSTEM 0x30000000
void ibm44x_dbcr_reset(void)
{
unsigned long tmp;
asm volatile (
"mfspr %0,%1\n"
"oris %0,%0,%2@h\n"
"mtspr %1,%0"
: "=&r"(tmp) : "i"(SPRN_DBCR0), "i"(DBCR0_RST_SYSTEM)
);
}
/* Read 4xx EBC bus bridge registers to get mappings of the peripheral
* banks into the OPB address space */
void ibm4xx_fixup_ebc_ranges(const char *ebc)
{
void *devp;
u32 bxcr;
u32 ranges[EBC_NUM_BANKS*4];
u32 *p = ranges;
int i;
for (i = 0; i < EBC_NUM_BANKS; i++) {
mtdcr(DCRN_EBC0_CFGADDR, EBC_BXCR(i));
bxcr = mfdcr(DCRN_EBC0_CFGDATA);
if ((bxcr & EBC_BXCR_BU) != EBC_BXCR_BU_OFF) {
*p++ = i;
*p++ = 0;
*p++ = bxcr & EBC_BXCR_BAS;
*p++ = EBC_BXCR_BANK_SIZE(bxcr);
}
}
devp = finddevice(ebc);
if (! devp)
fatal("Couldn't locate EBC node %s\n\r", ebc);
setprop(devp, "ranges", ranges, (p - ranges) * sizeof(u32));
}

5
arch/powerpc/boot/44x.h
View File

@ -10,10 +10,7 @@
#ifndef _PPC_BOOT_44X_H_
#define _PPC_BOOT_44X_H_
void ibm44x_fixup_memsize(void);
void ibm4xx_fixup_ebc_ranges(const char *ebc);
void ibm44x_dbcr_reset(void);
void ebony_init(void *mac0, void *mac1);
void bamboo_init(void *mac0, void *mac1);
#endif /* _PPC_BOOT_44X_H_ */

300
arch/powerpc/boot/4xx.c Normal file
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@ -0,0 +1,300 @@
/*
* Copyright 2007 David Gibson, IBM Corporation.
*
* Based on earlier code:
* Matt Porter <mporter@kernel.crashing.org>
* Copyright 2002-2005 MontaVista Software Inc.
*
* Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
* Copyright (c) 2003, 2004 Zultys Technologies
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#include <stddef.h>
#include "types.h"
#include "string.h"
#include "stdio.h"
#include "ops.h"
#include "reg.h"
#include "dcr.h"
/* Read the 4xx SDRAM controller to get size of system memory. */
void ibm4xx_fixup_memsize(void)
{
int i;
unsigned long memsize, bank_config;
memsize = 0;
for (i = 0; i < ARRAY_SIZE(sdram_bxcr); i++) {
mtdcr(DCRN_SDRAM0_CFGADDR, sdram_bxcr[i]);
bank_config = mfdcr(DCRN_SDRAM0_CFGDATA);
if (bank_config & SDRAM_CONFIG_BANK_ENABLE)
memsize += SDRAM_CONFIG_BANK_SIZE(bank_config);
}
dt_fixup_memory(0, memsize);
}
/* 4xx DDR1/2 Denali memory controller support */
/* DDR0 registers */
#define DDR0_02 2
#define DDR0_08 8
#define DDR0_10 10
#define DDR0_14 14
#define DDR0_42 42
#define DDR0_43 43
/* DDR0_02 */
#define DDR_START 0x1
#define DDR_START_SHIFT 0
#define DDR_MAX_CS_REG 0x3
#define DDR_MAX_CS_REG_SHIFT 24
#define DDR_MAX_COL_REG 0xf
#define DDR_MAX_COL_REG_SHIFT 16
#define DDR_MAX_ROW_REG 0xf
#define DDR_MAX_ROW_REG_SHIFT 8
/* DDR0_08 */
#define DDR_DDR2_MODE 0x1
#define DDR_DDR2_MODE_SHIFT 0
/* DDR0_10 */
#define DDR_CS_MAP 0x3
#define DDR_CS_MAP_SHIFT 8
/* DDR0_14 */
#define DDR_REDUC 0x1
#define DDR_REDUC_SHIFT 16
/* DDR0_42 */
#define DDR_APIN 0x7
#define DDR_APIN_SHIFT 24
/* DDR0_43 */
#define DDR_COL_SZ 0x7
#define DDR_COL_SZ_SHIFT 8
#define DDR_BANK8 0x1
#define DDR_BANK8_SHIFT 0
#define DDR_GET_VAL(val, mask, shift) (((val) >> (shift)) & (mask))
static inline u32 mfdcr_sdram0(u32 reg)
{
mtdcr(DCRN_SDRAM0_CFGADDR, reg);
return mfdcr(DCRN_SDRAM0_CFGDATA);
}
void ibm4xx_denali_fixup_memsize(void)
{
u32 val, max_cs, max_col, max_row;
u32 cs, col, row, bank, dpath;
unsigned long memsize;
val = mfdcr_sdram0(DDR0_02);
if (!DDR_GET_VAL(val, DDR_START, DDR_START_SHIFT))
fatal("DDR controller is not initialized\n");
/* get maximum cs col and row values */
max_cs = DDR_GET_VAL(val, DDR_MAX_CS_REG, DDR_MAX_CS_REG_SHIFT);
max_col = DDR_GET_VAL(val, DDR_MAX_COL_REG, DDR_MAX_COL_REG_SHIFT);
max_row = DDR_GET_VAL(val, DDR_MAX_ROW_REG, DDR_MAX_ROW_REG_SHIFT);
/* get CS value */
val = mfdcr_sdram0(DDR0_10);
val = DDR_GET_VAL(val, DDR_CS_MAP, DDR_CS_MAP_SHIFT);
cs = 0;
while (val) {
if (val && 0x1)
cs++;
val = val >> 1;
}
if (!cs)
fatal("No memory installed\n");
if (cs > max_cs)
fatal("DDR wrong CS configuration\n");
/* get data path bytes */
val = mfdcr_sdram0(DDR0_14);
if (DDR_GET_VAL(val, DDR_REDUC, DDR_REDUC_SHIFT))
dpath = 8; /* 64 bits */
else
dpath = 4; /* 32 bits */
/* get adress pins (rows) */
val = mfdcr_sdram0(DDR0_42);
row = DDR_GET_VAL(val, DDR_APIN, DDR_APIN_SHIFT);
if (row > max_row)
fatal("DDR wrong APIN configuration\n");
row = max_row - row;
/* get collomn size and banks */
val = mfdcr_sdram0(DDR0_43);
col = DDR_GET_VAL(val, DDR_COL_SZ, DDR_COL_SZ_SHIFT);
if (col > max_col)
fatal("DDR wrong COL configuration\n");
col = max_col - col;
if (DDR_GET_VAL(val, DDR_BANK8, DDR_BANK8_SHIFT))
bank = 8; /* 8 banks */
else
bank = 4; /* 4 banks */
memsize = cs * (1 << (col+row)) * bank * dpath;
dt_fixup_memory(0, memsize);
}
#define SPRN_DBCR0_40X 0x3F2
#define SPRN_DBCR0_44X 0x134
#define DBCR0_RST_SYSTEM 0x30000000
void ibm44x_dbcr_reset(void)
{
unsigned long tmp;
asm volatile (
"mfspr %0,%1\n"
"oris %0,%0,%2@h\n"
"mtspr %1,%0"
: "=&r"(tmp) : "i"(SPRN_DBCR0_44X), "i"(DBCR0_RST_SYSTEM)
);
}
void ibm40x_dbcr_reset(void)
{
unsigned long tmp;
asm volatile (
"mfspr %0,%1\n"
"oris %0,%0,%2@h\n"
"mtspr %1,%0"
: "=&r"(tmp) : "i"(SPRN_DBCR0_40X), "i"(DBCR0_RST_SYSTEM)
);
}
#define EMAC_RESET 0x20000000
void ibm4xx_quiesce_eth(u32 *emac0, u32 *emac1)
{
/* Quiesce the MAL and EMAC(s) since PIBS/OpenBIOS don't do this for us */
if (emac0)
*emac0 = EMAC_RESET;
if (emac1)
*emac1 = EMAC_RESET;
mtdcr(DCRN_MAL0_CFG, MAL_RESET);
}
/* Read 4xx EBC bus bridge registers to get mappings of the peripheral
* banks into the OPB address space */
void ibm4xx_fixup_ebc_ranges(const char *ebc)
{
void *devp;
u32 bxcr;
u32 ranges[EBC_NUM_BANKS*4];
u32 *p = ranges;
int i;
for (i = 0; i < EBC_NUM_BANKS; i++) {
mtdcr(DCRN_EBC0_CFGADDR, EBC_BXCR(i));
bxcr = mfdcr(DCRN_EBC0_CFGDATA);
if ((bxcr & EBC_BXCR_BU) != EBC_BXCR_BU_OFF) {
*p++ = i;
*p++ = 0;
*p++ = bxcr & EBC_BXCR_BAS;
*p++ = EBC_BXCR_BANK_SIZE(bxcr);
}
}
devp = finddevice(ebc);
if (! devp)
fatal("Couldn't locate EBC node %s\n\r", ebc);
setprop(devp, "ranges", ranges, (p - ranges) * sizeof(u32));
}
#define SPRN_CCR1 0x378
void ibm440ep_fixup_clocks(unsigned int sysclk, unsigned int ser_clk)
{
u32 cpu, plb, opb, ebc, tb, uart0, m, vco;
u32 reg;
u32 fwdva, fwdvb, fbdv, lfbdv, opbdv0, perdv0, spcid0, prbdv0, tmp;
mtdcr(DCRN_CPR0_ADDR, CPR0_PLLD0);
reg = mfdcr(DCRN_CPR0_DATA);
tmp = (reg & 0x000F0000) >> 16;
fwdva = tmp ? tmp : 16;
tmp = (reg & 0x00000700) >> 8;
fwdvb = tmp ? tmp : 8;
tmp = (reg & 0x1F000000) >> 24;
fbdv = tmp ? tmp : 32;
lfbdv = (reg & 0x0000007F);
mtdcr(DCRN_CPR0_ADDR, CPR0_OPBD0);
reg = mfdcr(DCRN_CPR0_DATA);
tmp = (reg & 0x03000000) >> 24;
opbdv0 = tmp ? tmp : 4;
mtdcr(DCRN_CPR0_ADDR, CPR0_PERD0);
reg = mfdcr(DCRN_CPR0_DATA);
tmp = (reg & 0x07000000) >> 24;
perdv0 = tmp ? tmp : 8;
mtdcr(DCRN_CPR0_ADDR, CPR0_PRIMBD0);
reg = mfdcr(DCRN_CPR0_DATA);
tmp = (reg & 0x07000000) >> 24;
prbdv0 = tmp ? tmp : 8;
mtdcr(DCRN_CPR0_ADDR, CPR0_SCPID);
reg = mfdcr(DCRN_CPR0_DATA);
tmp = (reg & 0x03000000) >> 24;
spcid0 = tmp ? tmp : 4;
/* Calculate M */
mtdcr(DCRN_CPR0_ADDR, CPR0_PLLC0);
reg = mfdcr(DCRN_CPR0_DATA);
tmp = (reg & 0x03000000) >> 24;
if (tmp == 0) { /* PLL output */
tmp = (reg & 0x20000000) >> 29;
if (!tmp) /* PLLOUTA */
m = fbdv * lfbdv * fwdva;
else
m = fbdv * lfbdv * fwdvb;
}
else if (tmp == 1) /* CPU output */
m = fbdv * fwdva;
else
m = perdv0 * opbdv0 * fwdvb;
vco = (m * sysclk) + (m >> 1);
cpu = vco / fwdva;
plb = vco / fwdvb / prbdv0;
opb = plb / opbdv0;
ebc = plb / perdv0;
/* FIXME */
uart0 = ser_clk;
/* Figure out timebase. Either CPU or default TmrClk */
asm volatile (
"mfspr %0,%1\n"
:
"=&r"(reg) : "i"(SPRN_CCR1));
if (reg & 0x0080)
tb = 25000000; /* TmrClk is 25MHz */
else
tb = cpu;
dt_fixup_cpu_clocks(cpu, tb, 0);
dt_fixup_clock("/plb", plb);
dt_fixup_clock("/plb/opb", opb);
dt_fixup_clock("/plb/opb/ebc", ebc);
dt_fixup_clock("/plb/opb/serial@ef600300", uart0);
dt_fixup_clock("/plb/opb/serial@ef600400", uart0);
dt_fixup_clock("/plb/opb/serial@ef600500", uart0);
dt_fixup_clock("/plb/opb/serial@ef600600", uart0);
}

22
arch/powerpc/boot/4xx.h Normal file
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@ -0,0 +1,22 @@
/*
* PowerPC 4xx related functions
*
* Copyright 2007 IBM Corporation.
* Josh Boyer <jwboyer@linux.vnet.ibm.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef _POWERPC_BOOT_4XX_H_
#define _POWERPC_BOOT_4XX_H_
void ibm4xx_fixup_memsize(void);
void ibm4xx_denali_fixup_memsize(void);
void ibm44x_dbcr_reset(void);
void ibm40x_dbcr_reset(void);
void ibm4xx_quiesce_eth(u32 *emac0, u32 *emac1);
void ibm4xx_fixup_ebc_ranges(const char *ebc);
void ibm440ep_fixup_clocks(unsigned int sysclk, unsigned int ser_clk);
#endif /* _POWERPC_BOOT_4XX_H_ */

25
arch/powerpc/boot/Makefile
View File

@ -25,14 +25,19 @@ BOOTCFLAGS := -Wall -Wundef -Wstrict-prototypes -Wno-trigraphs \
-isystem $(shell $(CROSS32CC) -print-file-name=include)
BOOTAFLAGS := -D__ASSEMBLY__ $(BOOTCFLAGS) -traditional -nostdinc
ifdef CONFIG_DEBUG_INFO
BOOTCFLAGS += -g
endif
ifeq ($(call cc-option-yn, -fstack-protector),y)
BOOTCFLAGS += -fno-stack-protector
endif
BOOTCFLAGS += -I$(obj) -I$(srctree)/$(obj)
$(obj)/44x.o: BOOTCFLAGS += -mcpu=440
$(obj)/4xx.o: BOOTCFLAGS += -mcpu=440
$(obj)/ebony.o: BOOTCFLAGS += -mcpu=440
$(obj)/treeboot-walnut.o: BOOTCFLAGS += -mcpu=405
zlib := inffast.c inflate.c inftrees.c
zlibheader := inffast.h inffixed.h inflate.h inftrees.h infutil.h
@ -44,10 +49,14 @@ $(addprefix $(obj)/,$(zlib) gunzip_util.o main.o): \
src-wlib := string.S crt0.S stdio.c main.c flatdevtree.c flatdevtree_misc.c \
ns16550.c serial.c simple_alloc.c div64.S util.S \
gunzip_util.c elf_util.c $(zlib) devtree.c oflib.c ofconsole.c \
44x.c ebony.c mv64x60.c mpsc.c mv64x60_i2c.c cuboot.c
src-plat := of.c cuboot-83xx.c cuboot-85xx.c holly.c \
4xx.c ebony.c mv64x60.c mpsc.c mv64x60_i2c.c cuboot.c bamboo.c \
cpm-serial.c stdlib.c mpc52xx-psc.c planetcore.c uartlite.c \
fsl-soc.c mpc8xx.c pq2.c
src-plat := of.c cuboot-52xx.c cuboot-83xx.c cuboot-85xx.c holly.c \
cuboot-ebony.c treeboot-ebony.c prpmc2800.c \
ps3-head.S ps3-hvcall.S ps3.c
ps3-head.S ps3-hvcall.S ps3.c treeboot-bamboo.c cuboot-8xx.c \
cuboot-pq2.c cuboot-sequoia.c treeboot-walnut.c cuboot-bamboo.c \
fixed-head.S ep88xc.c cuboot-hpc2.c
src-boot := $(src-wlib) $(src-plat) empty.c
src-boot := $(addprefix $(obj)/, $(src-boot))
@ -139,9 +148,17 @@ image-$(CONFIG_PPC_ISERIES) += zImage.iseries
image-$(CONFIG_DEFAULT_UIMAGE) += uImage
ifneq ($(CONFIG_DEVICE_TREE),"")
image-$(CONFIG_PPC_8xx) += cuImage.8xx
image-$(CONFIG_PPC_EP88XC) += zImage.ep88xc
image-$(CONFIG_8260) += cuImage.pq2
image-$(CONFIG_PPC_MPC52xx) += cuImage.52xx
image-$(CONFIG_PPC_83xx) += cuImage.83xx
image-$(CONFIG_PPC_85xx) += cuImage.85xx
image-$(CONFIG_MPC7448HPC2) += cuImage.hpc2
image-$(CONFIG_EBONY) += treeImage.ebony cuImage.ebony
image-$(CONFIG_BAMBOO) += treeImage.bamboo cuImage.bamboo
image-$(CONFIG_SEQUOIA) += cuImage.sequoia
image-$(CONFIG_WALNUT) += treeImage.walnut
endif
# For 32-bit powermacs, build the COFF and miboot images

47
arch/powerpc/boot/bamboo.c Normal file
View File

@ -0,0 +1,47 @@
/*
* Copyright IBM Corporation, 2007
* Josh Boyer <jwboyer@linux.vnet.ibm.com>
*
* Based on ebony wrapper:
* Copyright 2007 David Gibson, IBM Corporation.
*
* Clocking code based on code by:
* Stefan Roese <sr@denx.de>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; version 2 of the License
*/
#include <stdarg.h>
#include <stddef.h>
#include "types.h"
#include "elf.h"
#include "string.h"
#include "stdio.h"
#include "page.h"
#include "ops.h"
#include "dcr.h"
#include "4xx.h"
#include "44x.h"
static u8 *bamboo_mac0, *bamboo_mac1;
static void bamboo_fixups(void)
{
unsigned long sysclk = 33333333;
ibm440ep_fixup_clocks(sysclk, 11059200);
ibm4xx_fixup_memsize();
ibm4xx_quiesce_eth((u32 *)0xef600e00, (u32 *)0xef600f00);
dt_fixup_mac_addresses(bamboo_mac0, bamboo_mac1);
}
void bamboo_init(void *mac0, void *mac1)
{
platform_ops.fixups = bamboo_fixups;
platform_ops.exit = ibm44x_dbcr_reset;
bamboo_mac0 = mac0;
bamboo_mac1 = mac1;
ft_init(_dtb_start, 0, 32);
serial_console_init();
}

269
arch/powerpc/boot/cpm-serial.c Normal file
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@ -0,0 +1,269 @@
/*
* CPM serial console support.
*
* Copyright 2007 Freescale Semiconductor, Inc.
* Author: Scott Wood <scottwood@freescale.com>
*
* It is assumed that the firmware (or the platform file) has already set
* up the port.
*/
#include "types.h"
#include "io.h"
#include "ops.h"
struct cpm_scc {
u32 gsmrl;
u32 gsmrh;
u16 psmr;
u8 res1[2];
u16 todr;
u16 dsr;
u16 scce;
u8 res2[2];
u16 sccm;
u8 res3;
u8 sccs;
u8 res4[8];
};
struct cpm_smc {
u8 res1[2];
u16 smcmr;
u8 res2[2];
u8 smce;
u8 res3[3];
u8 smcm;
u8 res4[5];
};
struct cpm_param {
u16 rbase;
u16 tbase;
u8 rfcr;
u8 tfcr;
};
struct cpm_bd {
u16 sc; /* Status and Control */
u16 len; /* Data length in buffer */
u8 *addr; /* Buffer address in host memory */
};
static void *cpcr;
static struct cpm_param *param;
static struct cpm_smc *smc;
static struct cpm_scc *scc;
struct cpm_bd *tbdf, *rbdf;
static u32 cpm_cmd;
static u8 *muram_start;
static u32 muram_offset;
static void (*do_cmd)(int op);
static void (*enable_port)(void);
static void (*disable_port)(void);
#define CPM_CMD_STOP_TX 4
#define CPM_CMD_RESTART_TX 6
#define CPM_CMD_INIT_RX_TX 0
static void cpm1_cmd(int op)
{
while (in_be16(cpcr) & 1)
;
out_be16(cpcr, (op << 8) | cpm_cmd | 1);
while (in_be16(cpcr) & 1)
;
}
static void cpm2_cmd(int op)
{
while (in_be32(cpcr) & 0x10000)
;
out_be32(cpcr, op | cpm_cmd | 0x10000);
while (in_be32(cpcr) & 0x10000)
;
}
static void smc_disable_port(void)
{
do_cmd(CPM_CMD_STOP_TX);
out_be16(&smc->smcmr, in_be16(&smc->smcmr) & ~3);
}
static void scc_disable_port(void)
{
do_cmd(CPM_CMD_STOP_TX);
out_be32(&scc->gsmrl, in_be32(&scc->gsmrl) & ~0x30);
}
static void smc_enable_port(void)
{
out_be16(&smc->smcmr, in_be16(&smc->smcmr) | 3);
do_cmd(CPM_CMD_RESTART_TX);
}
static void scc_enable_port(void)
{
out_be32(&scc->gsmrl, in_be32(&scc->gsmrl) | 0x30);
do_cmd(CPM_CMD_RESTART_TX);
}
static int cpm_serial_open(void)
{
disable_port();
out_8(&param->rfcr, 0x10);
out_8(&param->tfcr, 0x10);
rbdf = (struct cpm_bd *)muram_start;
rbdf->addr = (u8 *)(rbdf + 2);
rbdf->sc = 0xa000;
rbdf->len = 1;
tbdf = rbdf + 1;
tbdf->addr = (u8 *)(rbdf + 2) + 1;
tbdf->sc = 0x2000;
tbdf->len = 1;
sync();
out_be16(&param->rbase, muram_offset);
out_be16(&param->tbase, muram_offset + sizeof(struct cpm_bd));
do_cmd(CPM_CMD_INIT_RX_TX);
enable_port();
return 0;
}
static void cpm_serial_putc(unsigned char c)
{
while (tbdf->sc & 0x8000)
barrier();
sync();
tbdf->addr[0] = c;
eieio();
tbdf->sc |= 0x8000;
}
static unsigned char cpm_serial_tstc(void)
{
barrier();
return !(rbdf->sc & 0x8000);
}
static unsigned char cpm_serial_getc(void)
{
unsigned char c;
while (!cpm_serial_tstc())
;
sync();
c = rbdf->addr[0];
eieio();
rbdf->sc |= 0x8000;
return c;
}
int cpm_console_init(void *devp, struct serial_console_data *scdp)
{
void *reg_virt[2];
int is_smc = 0, is_cpm2 = 0, n;
unsigned long reg_phys;
void *parent, *muram;
if (dt_is_compatible(devp, "fsl,cpm1-smc-uart")) {
is_smc = 1;
} else if (dt_is_compatible(devp, "fsl,cpm2-scc-uart")) {
is_cpm2 = 1;
} else if (dt_is_compatible(devp, "fsl,cpm2-smc-uart")) {
is_cpm2 = 1;
is_smc = 1;
}
if (is_smc) {
enable_port = smc_enable_port;
disable_port = smc_disable_port;
} else {
enable_port = scc_enable_port;
disable_port = scc_disable_port;
}
if (is_cpm2)
do_cmd = cpm2_cmd;
else
do_cmd = cpm1_cmd;
n = getprop(devp, "fsl,cpm-command", &cpm_cmd, 4);
if (n < 4)
return -1;
n = getprop(devp, "virtual-reg", reg_virt, sizeof(reg_virt));
if (n < (int)sizeof(reg_virt)) {
for (n = 0; n < 2; n++) {
if (!dt_xlate_reg(devp, n, &reg_phys, NULL))
return -1;
reg_virt[n] = (void *)reg_phys;
}
}
if (is_smc)
smc = reg_virt[0];
else
scc = reg_virt[0];
param = reg_virt[1];
parent = get_parent(devp);
if (!parent)
return -1;
n = getprop(parent, "virtual-reg", reg_virt, sizeof(reg_virt));
if (n < (int)sizeof(reg_virt)) {
if (!dt_xlate_reg(parent, 0, &reg_phys, NULL))
return -1;
reg_virt[0] = (void *)reg_phys;
}
cpcr = reg_virt[0];
muram = finddevice("/soc/cpm/muram/data");
if (!muram)
return -1;
/* For bootwrapper-compatible device trees, we assume that the first
* entry has at least 18 bytes, and that #address-cells/#data-cells
* is one for both parent and child.
*/
n = getprop(muram, "virtual-reg", reg_virt, sizeof(reg_virt));
if (n < (int)sizeof(reg_virt)) {
if (!dt_xlate_reg(muram, 0, &reg_phys, NULL))
return -1;
reg_virt[0] = (void *)reg_phys;
}
muram_start = reg_virt[0];
n = getprop(muram, "reg", &muram_offset, 4);
if (n < 4)
return -1;
scdp->open = cpm_serial_open;
scdp->putc = cpm_serial_putc;
scdp->getc = cpm_serial_getc;
scdp->tstc = cpm_serial_tstc;
return 0;
}

59
arch/powerpc/boot/cuboot-52xx.c Normal file
View File

@ -0,0 +1,59 @@
/*
* Old U-boot compatibility for MPC5200
*
* Author: Grant Likely <grant.likely@secretlab.ca>
*
* Copyright (c) 2007 Secret Lab Technologies Ltd.
* Copyright (c) 2007 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#include "ops.h"
#include "stdio.h"
#include "io.h"
#include "cuboot.h"
#define TARGET_PPC_MPC52xx
#include "ppcboot.h"
static bd_t bd;
static void platform_fixups(void)
{
void *soc, *reg;
int div;
u32 sysfreq;
dt_fixup_memory(bd.bi_memstart, bd.bi_memsize);
dt_fixup_mac_addresses(bd.bi_enetaddr);
dt_fixup_cpu_clocks(bd.bi_intfreq, bd.bi_busfreq / 4, bd.bi_busfreq);
/* Unfortunately, the specific model number is encoded in the
* soc node name in existing dts files -- once that is fixed,
* this can do a simple path lookup.
*/
soc = find_node_by_devtype(NULL, "soc");
if (soc) {
setprop(soc, "bus-frequency", &bd.bi_ipbfreq,
sizeof(bd.bi_ipbfreq));
if (!dt_xlate_reg(soc, 0, (void*)&reg, NULL))
return;
div = in_8(reg + 0x204) & 0x0020 ? 8 : 4;
sysfreq = bd.bi_busfreq * div;
setprop(soc, "system-frequency", &sysfreq, sizeof(sysfreq));
}
}
void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
unsigned long r6, unsigned long r7)
{
CUBOOT_INIT();
ft_init(_dtb_start, _dtb_end - _dtb_start, 32);
serial_console_init();
platform_ops.fixups = platform_fixups;
}

1
arch/powerpc/boot/cuboot-83xx.c
View File

@ -18,7 +18,6 @@
#include "ppcboot.h"
static bd_t bd;
extern char _dtb_start[], _dtb_end[];
static void platform_fixups(void)
{

1
arch/powerpc/boot/cuboot-85xx.c
View File

@ -18,7 +18,6 @@
#include "ppcboot.h"
static bd_t bd;
extern char _dtb_start[], _dtb_end[];
static void platform_fixups(void)
{

47
arch/powerpc/boot/cuboot-8xx.c Normal file
View File

@ -0,0 +1,47 @@
/*
* Old U-boot compatibility for 8xx
*
* Author: Scott Wood <scottwood@freescale.com>
*
* Copyright (c) 2007 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#include "ops.h"
#include "stdio.h"
#include "cuboot.h"
#define TARGET_8xx
#define TARGET_HAS_ETH1
#include "ppcboot.h"
static bd_t bd;
static void platform_fixups(void)
{
void *node;
dt_fixup_memory(bd.bi_memstart, bd.bi_memsize);
dt_fixup_mac_addresses(bd.bi_enetaddr, bd.bi_enet1addr);
dt_fixup_cpu_clocks(bd.bi_intfreq, bd.bi_busfreq / 16, bd.bi_busfreq);
node = finddevice("/soc/cpm");
if (node)
setprop(node, "clock-frequency", &bd.bi_busfreq, 4);
node = finddevice("/soc/cpm/brg");
if (node)
setprop(node, "clock-frequency", &bd.bi_busfreq, 4);
}
void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
unsigned long r6, unsigned long r7)
{
CUBOOT_INIT();
ft_init(_dtb_start, _dtb_end - _dtb_start, 32);
serial_console_init();
platform_ops.fixups = platform_fixups;
}

30
arch/powerpc/boot/cuboot-bamboo.c Normal file
View File

@ -0,0 +1,30 @@
/*
* Old U-boot compatibility for Bamboo
*
* Author: Josh Boyer <jwboyer@linux.vnet.ibm.com>
*
* Copyright 2007 IBM Corporation
*
* Based on cuboot-ebony.c
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#include "ops.h"
#include "stdio.h"
#include "44x.h"
#include "cuboot.h"
#define TARGET_44x
#include "ppcboot.h"
static bd_t bd;
void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
unsigned long r6, unsigned long r7)
{
CUBOOT_INIT();
bamboo_init(&bd.bi_enetaddr, &bd.bi_enet1addr);
}

48
arch/powerpc/boot/cuboot-hpc2.c Normal file
View File

@ -0,0 +1,48 @@
/*
* Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
*
* Author: Roy Zang <tie-fei.zang@freescale.com>
*
* Description:
* Old U-boot compatibility for mpc7448hpc2 board
* Based on the code of Scott Wood <scottwood@freescale.com>
* for 83xx and 85xx.
*
* This is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
*/
#include "ops.h"
#include "stdio.h"
#include "cuboot.h"
#define TARGET_HAS_ETH1
#include "ppcboot.h"
static bd_t bd;
extern char _dtb_start[], _dtb_end[];
static void platform_fixups(void)
{
void *tsi;
dt_fixup_memory(bd.bi_memstart, bd.bi_memsize);
dt_fixup_mac_addresses(bd.bi_enetaddr, bd.bi_enet1addr);
dt_fixup_cpu_clocks(bd.bi_intfreq, bd.bi_busfreq / 4, bd.bi_busfreq);
tsi = find_node_by_devtype(NULL, "tsi-bridge");
if (tsi)
setprop(tsi, "bus-frequency", &bd.bi_busfreq,
sizeof(bd.bi_busfreq));
}
void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
unsigned long r6, unsigned long r7)
{
CUBOOT_INIT();
ft_init(_dtb_start, _dtb_end - _dtb_start, 32);
serial_console_init();
platform_ops.fixups = platform_fixups;
}

261
arch/powerpc/boot/cuboot-pq2.c Normal file
View File

@ -0,0 +1,261 @@
/*
* Old U-boot compatibility for PowerQUICC II
* (a.k.a. 82xx with CPM, not the 8240 family of chips)
*
* Author: Scott Wood <scottwood@freescale.com>
*
* Copyright (c) 2007 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#include "ops.h"
#include "stdio.h"
#include "cuboot.h"
#include "io.h"
#include "fsl-soc.h"
#define TARGET_CPM2
#define TARGET_HAS_ETH1
#include "ppcboot.h"
static bd_t bd;
struct cs_range {
u32 csnum;
u32 base; /* must be zero */
u32 addr;
u32 size;
};
struct pci_range {
u32 flags;
u32 pci_addr[2];
u32 phys_addr;
u32 size[2];
};
struct cs_range cs_ranges_buf[MAX_PROP_LEN / sizeof(struct cs_range)];
struct pci_range pci_ranges_buf[MAX_PROP_LEN / sizeof(struct pci_range)];
/* Different versions of u-boot put the BCSR in different places, and
* some don't set up the PCI PIC at all, so we assume the device tree is
* sane and update the BRx registers appropriately.
*
* For any node defined as compatible with fsl,pq2-localbus,
* #address/#size must be 2/1 for the localbus, and 1/1 for the parent bus.
* Ranges must be for whole chip selects.
*/
static void update_cs_ranges(void)
{
void *bus_node, *parent_node;
u32 *ctrl_addr;
unsigned long ctrl_size;
u32 naddr, nsize;
int len;
int i;
bus_node = finddevice("/localbus");
if (!bus_node || !dt_is_compatible(bus_node, "fsl,pq2-localbus"))
return;
dt_get_reg_format(bus_node, &naddr, &nsize);
if (naddr != 2 || nsize != 1)
goto err;
parent_node = get_parent(bus_node);
if (!parent_node)
goto err;
dt_get_reg_format(parent_node, &naddr, &nsize);
if (naddr != 1 || nsize != 1)
goto err;
if (!dt_xlate_reg(bus_node, 0, (unsigned long *)&ctrl_addr,
&ctrl_size))
goto err;
len = getprop(bus_node, "ranges", cs_ranges_buf, sizeof(cs_ranges_buf));
for (i = 0; i < len / sizeof(struct cs_range); i++) {
u32 base, option;
int cs = cs_ranges_buf[i].csnum;
if (cs >= ctrl_size / 8)
goto err;
if (cs_ranges_buf[i].base != 0)
goto err;
base = in_be32(&ctrl_addr[cs * 2]);
/* If CS is already valid, use the existing flags.
* Otherwise, guess a sane default.
*/
if (base & 1) {
base &= 0x7fff;
option = in_be32(&ctrl_addr[cs * 2 + 1]) & 0x7fff;
} else {
base = 0x1801;
option = 0x10;
}
out_be32(&ctrl_addr[cs * 2], 0);
out_be32(&ctrl_addr[cs * 2 + 1],
option | ~(cs_ranges_buf[i].size - 1));
out_be32(&ctrl_addr[cs * 2], base | cs_ranges_buf[i].addr);
}
return;
err:
printf("Bad /localbus node\r\n");
}
/* Older u-boots don't set PCI up properly. Update the hardware to match
* the device tree. The prefetch mem region and non-prefetch mem region
* must be contiguous in the host bus. As required by the PCI binding,
* PCI #addr/#size must be 3/2. The parent bus must be 1/1. Only
* 32-bit PCI is supported. All three region types (prefetchable mem,
* non-prefetchable mem, and I/O) must be present.
*/
static void fixup_pci(void)
{
struct pci_range *mem = NULL, *mmio = NULL,
*io = NULL, *mem_base = NULL;
u32 *pci_regs[3];
u8 *soc_regs;
int i, len;
void *node, *parent_node;
u32 naddr, nsize, mem_log2;
node = finddevice("/pci");
if (!node || !dt_is_compatible(node, "fsl,pq2-pci"))
return;
for (i = 0; i < 3; i++)
if (!dt_xlate_reg(node, i,
(unsigned long *)&pci_regs[i], NULL))
goto err;
soc_regs = (u8 *)fsl_get_immr();
if (!soc_regs)
goto err;
dt_get_reg_format(node, &naddr, &nsize);
if (naddr != 3 || nsize != 2)
goto err;
parent_node = get_parent(node);
if (!parent_node)
goto err;
dt_get_reg_format(parent_node, &naddr, &nsize);
if (naddr != 1 || nsize != 1)
goto err;
len = getprop(node, "ranges", pci_ranges_buf,
sizeof(pci_ranges_buf));
for (i = 0; i < len / sizeof(struct pci_range); i++) {
u32 flags = pci_ranges_buf[i].flags & 0x43000000;
if (flags == 0x42000000)
mem = &pci_ranges_buf[i];
else if (flags == 0x02000000)
mmio = &pci_ranges_buf[i];
else if (flags == 0x01000000)
io = &pci_ranges_buf[i];
}
if (!mem || !mmio || !io)
goto err;
if (mem->phys_addr + mem->size[1] == mmio->phys_addr)
mem_base = mem;
else if (mmio->phys_addr + mmio->size[1] == mem->phys_addr)
mem_base = mmio;
else
goto err;
out_be32(&pci_regs[1][0], mem_base->phys_addr | 1);
out_be32(&pci_regs[2][0], ~(mem->size[1] + mmio->size[1] - 1));
out_be32(&pci_regs[1][1], io->phys_addr | 1);
out_be32(&pci_regs[2][1], ~(io->size[1] - 1));
out_le32(&pci_regs[0][0], mem->pci_addr[1] >> 12);
out_le32(&pci_regs[0][2], mem->phys_addr >> 12);
out_le32(&pci_regs[0][4], (~(mem->size[1] - 1) >> 12) | 0xa0000000);
out_le32(&pci_regs[0][6], mmio->pci_addr[1] >> 12);
out_le32(&pci_regs[0][8], mmio->phys_addr >> 12);
out_le32(&pci_regs[0][10], (~(mmio->size[1] - 1) >> 12) | 0x80000000);
out_le32(&pci_regs[0][12], io->pci_addr[1] >> 12);
out_le32(&pci_regs[0][14], io->phys_addr >> 12);
out_le32(&pci_regs[0][16], (~(io->size[1] - 1) >> 12) | 0xc0000000);
/* Inbound translation */
out_le32(&pci_regs[0][58], 0);
out_le32(&pci_regs[0][60], 0);
mem_log2 = 1 << (__ilog2_u32(bd.bi_memsize - 1) + 1);
out_le32(&pci_regs[0][62], 0xa0000000 | ~((1 << (mem_log2 - 12)) - 1));
/* If PCI is disabled, drive RST high to enable. */
if (!(in_le32(&pci_regs[0][32]) & 1)) {
/* Tpvrh (Power valid to RST# high) 100 ms */
udelay(100000);
out_le32(&pci_regs[0][32], 1);
/* Trhfa (RST# high to first cfg access) 2^25 clocks */
udelay(1020000);
}
/* Enable bus master and memory access */
out_le32(&pci_regs[0][64], 0x80000004);
out_le32(&pci_regs[0][65], in_le32(&pci_regs[0][65]) | 6);
/* Park the bus on PCI, and elevate PCI's arbitration priority,
* as required by section 9.6 of the user's manual.
*/
out_8(&soc_regs[0x10028], 3);
out_be32((u32 *)&soc_regs[0x1002c], 0x01236745);
return;
err:
printf("Bad PCI node\r\n");
}
static void pq2_platform_fixups(void)
{
void *node;
dt_fixup_memory(bd.bi_memstart, bd.bi_memsize);
dt_fixup_mac_addresses(bd.bi_enetaddr, bd.bi_enet1addr);
dt_fixup_cpu_clocks(bd.bi_intfreq, bd.bi_busfreq / 4, bd.bi_busfreq);
node = finddevice("/soc/cpm");
if (node)
setprop(node, "clock-frequency", &bd.bi_cpmfreq, 4);
node = finddevice("/soc/cpm/brg");
if (node)
setprop(node, "clock-frequency", &bd.bi_brgfreq, 4);
update_cs_ranges();
fixup_pci();
}
void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
unsigned long r6, unsigned long r7)
{
CUBOOT_INIT();
ft_init(_dtb_start, _dtb_end - _dtb_start, 32);
serial_console_init();
platform_ops.fixups = pq2_platform_fixups;
}

56
arch/powerpc/boot/cuboot-sequoia.c Normal file
View File

@ -0,0 +1,56 @@
/*
* Old U-boot compatibility for Sequoia
*
* Valentine Barshak <vbarshak@ru.mvista.com>
* Copyright 2007 MontaVista Software, Inc
*
* Based on Ebony code by David Gibson <david@gibson.dropbear.id.au>
* Copyright IBM Corporation, 2007
*
* Based on Bamboo code by Josh Boyer <jwboyer@linux.vnet.ibm.com>
* Copyright IBM Corporation, 2007
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; version 2 of the License
*/
#include <stdarg.h>
#include <stddef.h>
#include "types.h"
#include "elf.h"
#include "string.h"
#include "stdio.h"
#include "page.h"
#include "ops.h"
#include "dcr.h"
#include "4xx.h"
#include "44x.h"
#include "cuboot.h"
#define TARGET_4xx
#define TARGET_44x
#include "ppcboot.h"
static bd_t bd;
static void sequoia_fixups(void)
{
unsigned long sysclk = 33333333;
ibm440ep_fixup_clocks(sysclk, 11059200);
ibm4xx_fixup_ebc_ranges("/plb/opb/ebc");
ibm4xx_denali_fixup_memsize();
dt_fixup_mac_addresses(&bd.bi_enetaddr, &bd.bi_enet1addr);
}
void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
unsigned long r6, unsigned long r7)
{
CUBOOT_INIT();
platform_ops.fixups = sequoia_fixups;
platform_ops.exit = ibm44x_dbcr_reset;
ft_init(_dtb_start, 0, 32);
serial_console_init();
}

3
arch/powerpc/boot/cuboot.c
View File

@ -17,9 +17,6 @@
#include "ppcboot.h"
extern char _end[];
extern char _dtb_start[], _dtb_end[];
void cuboot_init(unsigned long r4, unsigned long r5,
unsigned long r6, unsigned long r7,
unsigned long end_of_ram)

18
arch/powerpc/boot/dcr.h
View File

@ -121,4 +121,22 @@ static const unsigned long sdram_bxcr[] = { SDRAM0_B0CR, SDRAM0_B1CR, SDRAM0_B2C
#define DCRN_CPC0_MIRQ1 0x0ed
#define DCRN_CPC0_JTAGID 0x0ef
#define DCRN_MAL0_CFG 0x180
#define MAL_RESET 0x80000000
/* 440EP Clock/Power-on Reset regs */
#define DCRN_CPR0_ADDR 0xc
#define DCRN_CPR0_DATA 0xd
#define CPR0_PLLD0 0x60
#define CPR0_OPBD0 0xc0
#define CPR0_PERD0 0xe0
#define CPR0_PRIMBD0 0xa0
#define CPR0_SCPID 0x120
#define CPR0_PLLC0 0x40
/* 405GP Clocking/Power Management/Chip Control regs */
#define DCRN_CPC0_PLLMR 0xb0
#define DCRN_405_CPC0_CR0 0xb1
#define DCRN_405_CPC0_CR1 0xb2
#endif /* _PPC_BOOT_DCR_H_ */

99
arch/powerpc/boot/devtree.c
View File

@ -74,6 +74,8 @@ void dt_fixup_cpu_clocks(u32 cpu, u32 tb, u32 bus)
if (bus > 0)
setprop_val(devp, "bus-frequency", bus);
}
timebase_period_ns = 1000000000 / tb;
}
void dt_fixup_clock(const char *path, u32 freq)
@ -86,34 +88,38 @@ void dt_fixup_clock(const char *path, u32 freq)
}
}
void dt_fixup_mac_address(u32 index, const u8 *addr)
{
void *devp = find_node_by_prop_value(NULL, "linux,network-index",
(void*)&index, sizeof(index));
if (devp) {
printf("ENET%d: local-mac-address <-"
" %02x:%02x:%02x:%02x:%02x:%02x\n\r", index,
addr[0], addr[1], addr[2],
addr[3], addr[4], addr[5]);
setprop(devp, "local-mac-address", addr, 6);
}
}
void __dt_fixup_mac_addresses(u32 startindex, ...)
{
va_list ap;
u32 index = startindex;
void *devp;
const u8 *addr;
va_start(ap, startindex);
while ((addr = va_arg(ap, const u8 *))) {
devp = find_node_by_prop_value(NULL, "linux,network-index",
(void*)&index, sizeof(index));
printf("ENET%d: local-mac-address <-"
" %02x:%02x:%02x:%02x:%02x:%02x\n\r", index,
addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
while ((addr = va_arg(ap, const u8 *)))
dt_fixup_mac_address(index++, addr);
if (devp)
setprop(devp, "local-mac-address", addr, 6);
index++;
}
va_end(ap);
}
#define MAX_ADDR_CELLS 4
#define MAX_RANGES 8
static void get_reg_format(void *node, u32 *naddr, u32 *nsize)
void dt_get_reg_format(void *node, u32 *naddr, u32 *nsize)
{
if (getprop(node, "#address-cells", naddr, 4) != 4)
*naddr = 2;
@ -207,7 +213,7 @@ static int find_range(u32 *reg, u32 *ranges, int nregaddr,
* In particular, PCI is not supported. Also, only the beginning of the
* reg block is tracked; size is ignored except in ranges.
*/
static u32 dt_xlate_buf[MAX_ADDR_CELLS * MAX_RANGES * 3];
static u32 prop_buf[MAX_PROP_LEN / 4];
static int dt_xlate(void *node, int res, int reglen, unsigned long *addr,
unsigned long *size)
@ -216,14 +222,14 @@ static int dt_xlate(void *node, int res, int reglen, unsigned long *addr,
u32 this_addr[MAX_ADDR_CELLS];
void *parent;
u64 ret_addr, ret_size;
u32 naddr, nsize, prev_naddr;
u32 naddr, nsize, prev_naddr, prev_nsize;
int buflen, offset;
parent = get_parent(node);
if (!parent)
return 0;
get_reg_format(parent, &naddr, &nsize);
dt_get_reg_format(parent, &naddr, &nsize);
if (nsize > 2)
return 0;
@ -231,41 +237,47 @@ static int dt_xlate(void *node, int res, int reglen, unsigned long *addr,
offset = (naddr + nsize) * res;
if (reglen < offset + naddr + nsize ||
sizeof(dt_xlate_buf) < offset + naddr + nsize)
MAX_PROP_LEN < (offset + naddr + nsize) * 4)
return 0;
copy_val(last_addr, dt_xlate_buf + offset, naddr);
copy_val(last_addr, prop_buf + offset, naddr);
ret_size = dt_xlate_buf[offset + naddr];
ret_size = prop_buf[offset + naddr];
if (nsize == 2) {
ret_size <<= 32;
ret_size |= dt_xlate_buf[offset + naddr + 1];
ret_size |= prop_buf[offset + naddr + 1];
}
while ((node = get_parent(node))) {
for (;;) {
prev_naddr = naddr;
prev_nsize = nsize;
node = parent;
get_reg_format(node, &naddr, &nsize);
parent = get_parent(node);
if (!parent)
break;
buflen = getprop(node, "ranges", dt_xlate_buf,
sizeof(dt_xlate_buf));
if (buflen < 0)
dt_get_reg_format(parent, &naddr, &nsize);
buflen = getprop(node, "ranges", prop_buf,
sizeof(prop_buf));
if (buflen == 0)
continue;
if (buflen > sizeof(dt_xlate_buf))
if (buflen < 0 || buflen > sizeof(prop_buf))
return 0;
offset = find_range(last_addr, dt_xlate_buf, prev_naddr,
naddr, nsize, buflen / 4);
offset = find_range(last_addr, prop_buf, prev_naddr,
naddr, prev_nsize, buflen / 4);
if (offset < 0)
return 0;
copy_val(this_addr, dt_xlate_buf + offset, prev_naddr);
copy_val(this_addr, prop_buf + offset, prev_naddr);
if (!sub_reg(last_addr, this_addr))
return 0;
copy_val(this_addr, dt_xlate_buf + offset + prev_naddr, naddr);
copy_val(this_addr, prop_buf + offset + prev_naddr, naddr);
if (!add_reg(last_addr, this_addr, naddr))
return 0;
@ -292,16 +304,35 @@ int dt_xlate_reg(void *node, int res, unsigned long *addr, unsigned long *size)
{
int reglen;
reglen = getprop(node, "reg", dt_xlate_buf, sizeof(dt_xlate_buf)) / 4;
reglen = getprop(node, "reg", prop_buf, sizeof(prop_buf)) / 4;
return dt_xlate(node, res, reglen, addr, size);
}
int dt_xlate_addr(void *node, u32 *buf, int buflen, unsigned long *xlated_addr)
{
if (buflen > sizeof(dt_xlate_buf))
if (buflen > sizeof(prop_buf))
return 0;
memcpy(dt_xlate_buf, buf, buflen);
memcpy(prop_buf, buf, buflen);
return dt_xlate(node, 0, buflen / 4, xlated_addr, NULL);
}
int dt_is_compatible(void *node, const char *compat)
{
char *buf = (char *)prop_buf;
int len, pos;
len = getprop(node, "compatible", buf, MAX_PROP_LEN);
if (len < 0)
return 0;
for (pos = 0; pos < len; pos++) {
if (!strcmp(buf + pos, compat))
return 1;
pos += strnlen(&buf[pos], len - pos);
}
return 0;
}

244
arch/powerpc/boot/dts/bamboo.dts Normal file
View File

@ -0,0 +1,244 @@
/*
* Device Tree Source for AMCC Bamboo
*
* Copyright (c) 2006, 2007 IBM Corp.
* Josh Boyer <jwboyer@linux.vnet.ibm.com>
*
* FIXME: Draft only!
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without
* any warranty of any kind, whether express or implied.
*/
/ {
#address-cells = <2>;
#size-cells = <1>;
model = "amcc,bamboo";
compatible = "amcc,bamboo";
dcr-parent = <&/cpus/PowerPC,440EP@0>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,440EP@0 {
device_type = "cpu";
reg = <0>;
clock-frequency = <0>; /* Filled in by zImage */
timebase-frequency = <0>; /* Filled in by zImage */
i-cache-line-size = <20>;
d-cache-line-size = <20>;
i-cache-size = <8000>;
d-cache-size = <8000>;
dcr-controller;
dcr-access-method = "native";
};
};
memory {
device_type = "memory";
reg = <0 0 0>; /* Filled in by zImage */
};
UIC0: interrupt-controller0 {
compatible = "ibm,uic-440ep","ibm,uic";
interrupt-controller;
cell-index = <0>;
dcr-reg = <0c0 009>;
#address-cells = <0>;
#size-cells = <0>;
#interrupt-cells = <2>;
};
UIC1: interrupt-controller1 {
compatible = "ibm,uic-440ep","ibm,uic";
interrupt-controller;
cell-index = <1>;
dcr-reg = <0d0 009>;
#address-cells = <0>;
#size-cells = <0>;
#interrupt-cells = <2>;
interrupts = <1e 4 1f 4>; /* cascade */
interrupt-parent = <&UIC0>;
};
SDR0: sdr {
compatible = "ibm,sdr-440ep";
dcr-reg = <00e 002>;
};
CPR0: cpr {
compatible = "ibm,cpr-440ep";
dcr-reg = <00c 002>;
};
plb {
compatible = "ibm,plb-440ep", "ibm,plb-440gp", "ibm,plb4";
#address-cells = <2>;
#size-cells = <1>;
ranges;
clock-frequency = <0>; /* Filled in by zImage */
SDRAM0: sdram {
compatible = "ibm,sdram-440ep", "ibm,sdram-405gp";
dcr-reg = <010 2>;
};
DMA0: dma {
compatible = "ibm,dma-440ep", "ibm,dma-440gp";
dcr-reg = <100 027>;
};
MAL0: mcmal {
compatible = "ibm,mcmal-440ep", "ibm,mcmal-440gp", "ibm,mcmal";
dcr-reg = <180 62>;
num-tx-chans = <4>;
num-rx-chans = <2>;
interrupt-parent = <&MAL0>;
interrupts = <0 1 2 3 4>;
#interrupt-cells = <1>;
interrupt-map = </*TXEOB*/ 0 &UIC0 a 4
/*RXEOB*/ 1 &UIC0 b 4
/*SERR*/ 2 &UIC1 0 4
/*TXDE*/ 3 &UIC1 1 4
/*RXDE*/ 4 &UIC1 3 4>;
};
POB0: opb {
compatible = "ibm,opb-440ep", "ibm,opb-440gp", "ibm,opb";
#address-cells = <1>;
#size-cells = <1>;
/* Bamboo is oddball in the 44x world and doesn't use the ERPN
* bits.
*/
ranges = <00000000 0 00000000 80000000
80000000 0 80000000 80000000>;
interrupt-parent = <&UIC1>;
interrupts = <7 4>;
clock-frequency = <0>; /* Filled in by zImage */
EBC0: ebc {
compatible = "ibm,ebc-440ep", "ibm,ebc-440gp", "ibm,ebc";
dcr-reg = <012 2>;
#address-cells = <2>;
#size-cells = <1>;
clock-frequency = <0>; /* Filled in by zImage */
ranges;
interrupts = <5 1>;
interrupt-parent = <&UIC1>;
};
UART0: serial@ef600300 {
device_type = "serial";
compatible = "ns16550";
reg = <ef600300 8>;
virtual-reg = <ef600300>;
clock-frequency = <0>; /* Filled in by zImage */
current-speed = <1c200>;
interrupt-parent = <&UIC0>;
interrupts = <0 4>;
};
UART1: serial@ef600400 {
device_type = "serial";
compatible = "ns16550";
reg = <ef600400 8>;
virtual-reg = <ef600400>;
clock-frequency = <0>;
current-speed = <0>;
interrupt-parent = <&UIC0>;
interrupts = <1 4>;
};
UART2: serial@ef600500 {
device_type = "serial";
compatible = "ns16550";
reg = <ef600500 8>;
virtual-reg = <ef600500>;
clock-frequency = <0>;
current-speed = <0>;
interrupt-parent = <&UIC0>;
interrupts = <3 4>;
};
UART3: serial@ef600600 {
device_type = "serial";
compatible = "ns16550";
reg = <ef600600 8>;
virtual-reg = <ef600600>;
clock-frequency = <0>;
current-speed = <0>;
interrupt-parent = <&UIC0>;
interrupts = <4 4>;
};
IIC0: i2c@ef600700 {
device_type = "i2c";
compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic";
reg = <ef600700 14>;
interrupt-parent = <&UIC0>;
interrupts = <2 4>;
};
IIC1: i2c@ef600800 {
device_type = "i2c";
compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic";
reg = <ef600800 14>;
interrupt-parent = <&UIC0>;
interrupts = <7 4>;
};
ZMII0: emac-zmii@ef600d00 {
device_type = "zmii-interface";
compatible = "ibm,zmii-440ep", "ibm,zmii-440gp", "ibm,zmii";
reg = <ef600d00 c>;
};
EMAC0: ethernet@ef600e00 {
device_type = "network";
compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac";
interrupt-parent = <&UIC1>;
interrupts = <1c 4 1d 4>;
reg = <ef600e00 70>;
local-mac-address = [000000000000];
mal-device = <&MAL0>;
mal-tx-channel = <0 1>;
mal-rx-channel = <0>;
cell-index = <0>;
max-frame-size = <5dc>;
rx-fifo-size = <1000>;
tx-fifo-size = <800>;
phy-mode = "rmii";
phy-map = <00000001>;
zmii-device = <&ZMII0>;
zmii-channel = <0>;
};
EMAC1: ethernet@ef600f00 {
device_type = "network";
compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac";
interrupt-parent = <&UIC1>;
interrupts = <1e 4 1f 4>;
reg = <ef600f00 70>;
local-mac-address = [000000000000];
mal-device = <&MAL0>;
mal-tx-channel = <2 3>;
mal-rx-channel = <1>;
cell-index = <1>;
max-frame-size = <5dc>;
rx-fifo-size = <1000>;
tx-fifo-size = <800>;
phy-mode = "rmii";
phy-map = <00000001>;
zmii-device = <&ZMII0>;
zmii-channel = <1>;
};
};
};
chosen {
linux,stdout-path = "/plb/opb/serial@ef600300";
bootargs = "console=ttyS0,115200";
};
};

35
arch/powerpc/boot/dts/ebony.dts
View File

@ -9,10 +9,6 @@
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without
* any warranty of any kind, whether express or implied.
*
* To build:
* dtc -I dts -O asm -o ebony.S -b 0 ebony.dts
* dtc -I dts -O dtb -o ebony.dtb -b 0 ebony.dts
*/
/ {
@ -142,13 +138,16 @@
interrupt-parent = <&UIC1>;
small-flash@0,80000 {
device_type = "rom";
compatible = "direct-mapped";
probe-type = "JEDEC";
compatible = "jedec-flash";
bank-width = <1>;
partitions = <0 80000>;
partition-names = "OpenBIOS";
reg = <0 80000 80000>;
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "OpenBIOS";
reg = <0 80000>;
read-only;
};
};
ds1743@1,0 {
@ -158,14 +157,19 @@
};
large-flash@2,0 {
device_type = "rom";
compatible = "direct-mapped";
probe-type = "JEDEC";
compatible = "jedec-flash";
bank-width = <1>;
partitions = <0 380000
380000 80000>;
partition-names = "fs", "firmware";
reg = <2 0 400000>;
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "fs";
reg = <0 380000>;
};
partition@380000 {
label = "firmware";
reg = <380000 80000>;
};
};
ir@3,0 {
@ -175,6 +179,7 @@
fpga@7,0 {
compatible = "Ebony-FPGA";
reg = <7 0 10>;
virtual-reg = <e8300000>;
};
};

214
arch/powerpc/boot/dts/ep88xc.dts Normal file
View File

@ -0,0 +1,214 @@
/*
* EP88xC Device Tree Source
*
* Copyright 2006 MontaVista Software, Inc.
* Copyright 2007 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
/ {
model = "EP88xC";
compatible = "fsl,ep88xc";
#address-cells = <1>;
#size-cells = <1>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,885@0 {
device_type = "cpu";
reg = <0>;
d-cache-line-size = <d#16>;
i-cache-line-size = <d#16>;
d-cache-size = <d#8192>;
i-cache-size = <d#8192>;
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
interrupts = <f 2>; // decrementer interrupt
interrupt-parent = <&PIC>;
};
};
memory {
device_type = "memory";
reg = <0 0>;
};
localbus@fa200100 {
compatible = "fsl,mpc885-localbus", "fsl,pq1-localbus";
#address-cells = <2>;
#size-cells = <1>;
reg = <fa200100 40>;
ranges = <
0 0 fc000000 04000000
3 0 fa000000 01000000
>;
flash@0,2000000 {
compatible = "cfi-flash";
reg = <0 2000000 2000000>;
bank-width = <4>;
device-width = <2>;
};
board-control@3,400000 {
reg = <3 400000 10>;
compatible = "fsl,ep88xc-bcsr";
};
};
soc@fa200000 {
compatible = "fsl,mpc885", "fsl,pq1-soc";
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
ranges = <0 fa200000 00004000>;
bus-frequency = <0>;
// Temporary -- will go away once kernel uses ranges for get_immrbase().
reg = <fa200000 4000>;
mdio@e00 {
compatible = "fsl,mpc885-fec-mdio", "fsl,pq1-fec-mdio";
reg = <e00 188>;
#address-cells = <1>;
#size-cells = <0>;
PHY0: ethernet-phy@0 {
reg = <0>;
device_type = "ethernet-phy";
};
PHY1: ethernet-phy@1 {
reg = <1>;
device_type = "ethernet-phy";
};
};
ethernet@e00 {
device_type = "network";
compatible = "fsl,mpc885-fec-enet",
"fsl,pq1-fec-enet";
reg = <e00 188>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <3 1>;
interrupt-parent = <&PIC>;
phy-handle = <&PHY0>;
linux,network-index = <0>;
};
ethernet@1e00 {
device_type = "network";
compatible = "fsl,mpc885-fec-enet",
"fsl,pq1-fec-enet";
reg = <1e00 188>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <7 1>;
interrupt-parent = <&PIC>;
phy-handle = <&PHY1>;
linux,network-index = <1>;
};
PIC: interrupt-controller@0 {
interrupt-controller;
#interrupt-cells = <2>;
reg = <0 24>;
compatible = "fsl,mpc885-pic", "fsl,pq1-pic";
};
pcmcia@80 {
#address-cells = <3>;
#interrupt-cells = <1>;
#size-cells = <2>;
compatible = "fsl,pq-pcmcia";
device_type = "pcmcia";
reg = <80 80>;
interrupt-parent = <&PIC>;
interrupts = <d 1>;
};
cpm@9c0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc885-cpm", "fsl,cpm1";
command-proc = <9c0>;
interrupts = <0>; // cpm error interrupt
interrupt-parent = <&CPM_PIC>;
reg = <9c0 40>;
ranges;
muram@2000 {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 2000 2000>;
data@0 {
compatible = "fsl,cpm-muram-data";
reg = <0 1c00>;
};
};
brg@9f0 {
compatible = "fsl,mpc885-brg",
"fsl,cpm1-brg",
"fsl,cpm-brg";
reg = <9f0 10>;
};
CPM_PIC: interrupt-controller@930 {
interrupt-controller;
#interrupt-cells = <1>;
interrupts = <5 2 0 2>;
interrupt-parent = <&PIC>;
reg = <930 20>;
compatible = "fsl,mpc885-cpm-pic",
"fsl,cpm1-pic";
};
// MON-1
serial@a80 {
device_type = "serial";
compatible = "fsl,mpc885-smc-uart",
"fsl,cpm1-smc-uart";
reg = <a80 10 3e80 40>;
interrupts = <4>;
interrupt-parent = <&CPM_PIC>;
fsl,cpm-brg = <1>;
fsl,cpm-command = <0090>;
linux,planetcore-label = "SMC1";
};
// SER-1
serial@a20 {
device_type = "serial";
compatible = "fsl,mpc885-scc-uart",
"fsl,cpm1-scc-uart";
reg = <a20 20 3d00 80>;
interrupts = <1d>;
interrupt-parent = <&CPM_PIC>;
fsl,cpm-brg = <2>;
fsl,cpm-command = <0040>;
linux,planetcore-label = "SCC2";
};
usb@a00 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,mpc885-usb",
"fsl,cpm1-usb";
reg = <a00 18 1c00 80>;
interrupt-parent = <&CPM_PIC>;
interrupts = <1e>;
fsl,cpm-command = <0000>;
};
};
};
};

5
arch/powerpc/boot/dts/holly.dts
View File

@ -8,10 +8,6 @@
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without
* any warranty of any kind, whether express or implied.
*
* To build:
* dtc -I dts -O asm -o holly.S -b 0 holly.dts
* dtc -I dts -O dtb -o holly.dtb -b 0 holly.dts
*/
/ {
@ -35,7 +31,6 @@
timebase-frequency = <2faf080>;
clock-frequency = <23c34600>;
bus-frequency = <bebc200>;
32-bit;
};
};

252
arch/powerpc/boot/dts/kilauea.dts Normal file
View File

@ -0,0 +1,252 @@
/*
* Device Tree Source for AMCC Kilauea (405EX)
*
* Copyright 2007 DENX Software Engineering, Stefan Roese <sr@denx.de>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without
* any warranty of any kind, whether express or implied.
*/
/ {
#address-cells = <1>;
#size-cells = <1>;
model = "amcc,kilauea";
compatible = "amcc,kilauea";
dcr-parent = <&/cpus/PowerPC,405EX@0>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,405EX@0 {
device_type = "cpu";
reg = <0>;
clock-frequency = <0>; /* Filled in by U-Boot */
timebase-frequency = <0>; /* Filled in by U-Boot */
i-cache-line-size = <20>;
d-cache-line-size = <20>;
i-cache-size = <4000>; /* 16 kB */
d-cache-size = <4000>; /* 16 kB */
dcr-controller;
dcr-access-method = "native";
};
};
memory {
device_type = "memory";
reg = <0 0>; /* Filled in by U-Boot */
};
UIC0: interrupt-controller {
compatible = "ibm,uic-405ex", "ibm,uic";
interrupt-controller;
cell-index = <0>;
dcr-reg = <0c0 009>;
#address-cells = <0>;
#size-cells = <0>;
#interrupt-cells = <2>;
};
UIC1: interrupt-controller1 {
compatible = "ibm,uic-405ex","ibm,uic";
interrupt-controller;
cell-index = <1>;
dcr-reg = <0d0 009>;
#address-cells = <0>;
#size-cells = <0>;
#interrupt-cells = <2>;
interrupts = <1e 4 1f 4>; /* cascade */
interrupt-parent = <&UIC0>;
};
UIC2: interrupt-controller2 {
compatible = "ibm,uic-405ex","ibm,uic";
interrupt-controller;
cell-index = <2>;
dcr-reg = <0e0 009>;
#address-cells = <0>;
#size-cells = <0>;
#interrupt-cells = <2>;
interrupts = <1c 4 1d 4>; /* cascade */
interrupt-parent = <&UIC0>;
};
plb {
compatible = "ibm,plb-405ex", "ibm,plb4";
#address-cells = <1>;
#size-cells = <1>;
ranges;
clock-frequency = <0>; /* Filled in by U-Boot */
SDRAM0: memory-controller {
compatible = "ibm,sdram-405ex";
dcr-reg = <010 2>;
};
MAL0: mcmal {
compatible = "ibm,mcmal-405ex", "ibm,mcmal2";
dcr-reg = <180 62>;
num-tx-chans = <2>;
num-rx-chans = <2>;
interrupt-parent = <&MAL0>;
interrupts = <0 1 2 3 4>;
#interrupt-cells = <1>;
#address-cells = <0>;
#size-cells = <0>;
interrupt-map = </*TXEOB*/ 0 &UIC0 a 4
/*RXEOB*/ 1 &UIC0 b 4
/*SERR*/ 2 &UIC1 0 4
/*TXDE*/ 3 &UIC1 1 4
/*RXDE*/ 4 &UIC1 2 4>;
interrupt-map-mask = <ffffffff>;
};
POB0: opb {
compatible = "ibm,opb-405ex", "ibm,opb";
#address-cells = <1>;
#size-cells = <1>;
ranges = <80000000 80000000 10000000
ef600000 ef600000 a00000
f0000000 f0000000 10000000>;
dcr-reg = <0a0 5>;
clock-frequency = <0>; /* Filled in by U-Boot */
EBC0: ebc {
compatible = "ibm,ebc-405ex", "ibm,ebc";
dcr-reg = <012 2>;
#address-cells = <2>;
#size-cells = <1>;
clock-frequency = <0>; /* Filled in by U-Boot */
/* ranges property is supplied by U-Boot */
interrupts = <5 1>;
interrupt-parent = <&UIC1>;
nor_flash@0,0 {
compatible = "amd,s29gl512n", "cfi-flash";
bank-width = <2>;
reg = <0 000000 4000000>;
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "kernel";
reg = <0 200000>;
};
partition@200000 {
label = "root";
reg = <200000 200000>;
};
partition@400000 {
label = "user";
reg = <400000 3b60000>;
};
partition@3f60000 {
label = "env";
reg = <3f60000 40000>;
};
partition@3fa0000 {
label = "u-boot";
reg = <3fa0000 60000>;
};
};
};
UART0: serial@ef600200 {
device_type = "serial";
compatible = "ns16550";
reg = <ef600200 8>;
virtual-reg = <ef600200>;
clock-frequency = <0>; /* Filled in by U-Boot */
current-speed = <0>;
interrupt-parent = <&UIC0>;
interrupts = <1a 4>;
};
UART1: serial@ef600300 {
device_type = "serial";
compatible = "ns16550";
reg = <ef600300 8>;
virtual-reg = <ef600300>;
clock-frequency = <0>; /* Filled in by U-Boot */
current-speed = <0>;
interrupt-parent = <&UIC0>;
interrupts = <1 4>;
};
IIC0: i2c@ef600400 {
device_type = "i2c";
compatible = "ibm,iic-405ex", "ibm,iic";
reg = <ef600400 14>;
interrupt-parent = <&UIC0>;
interrupts = <2 4>;
};
IIC1: i2c@ef600500 {
device_type = "i2c";
compatible = "ibm,iic-405ex", "ibm,iic";
reg = <ef600500 14>;
interrupt-parent = <&UIC0>;
interrupts = <7 4>;
};
RGMII0: emac-rgmii@ef600b00 {
device_type = "rgmii-interface";
compatible = "ibm,rgmii-405ex", "ibm,rgmii";
reg = <ef600b00 104>;
};
EMAC0: ethernet@ef600900 {
linux,network-index = <0>;
device_type = "network";
compatible = "ibm,emac-405ex", "ibm,emac4";
interrupt-parent = <&EMAC0>;
interrupts = <0 1>;
#interrupt-cells = <1>;
#address-cells = <0>;
#size-cells = <0>;
interrupt-map = </*Status*/ 0 &UIC0 18 4
/*Wake*/ 1 &UIC1 1d 4>;
reg = <ef600900 70>;
local-mac-address = [000000000000]; /* Filled in by U-Boot */
mal-device = <&MAL0>;
mal-tx-channel = <0>;
mal-rx-channel = <0>;
cell-index = <0>;
max-frame-size = <5dc>;
rx-fifo-size = <1000>;
tx-fifo-size = <800>;
phy-mode = "rgmii";
phy-map = <00000000>;
rgmii-device = <&RGMII0>;
rgmii-channel = <0>;
};
EMAC1: ethernet@ef600a00 {
linux,network-index = <1>;
device_type = "network";
compatible = "ibm,emac-405ex", "ibm,emac4";
interrupt-parent = <&EMAC1>;
interrupts = <0 1>;
#interrupt-cells = <1>;
#address-cells = <0>;
#size-cells = <0>;
interrupt-map = </*Status*/ 0 &UIC0 19 4
/*Wake*/ 1 &UIC1 1f 4>;
reg = <ef600a00 70>;
local-mac-address = [000000000000]; /* Filled in by U-Boot */
mal-device = <&MAL0>;
mal-tx-channel = <1>;
mal-rx-channel = <1>;
cell-index = <1>;
max-frame-size = <5dc>;
rx-fifo-size = <1000>;
tx-fifo-size = <800>;
phy-mode = "rgmii";
phy-map = <00000000>;
rgmii-device = <&RGMII0>;
rgmii-channel = <1>;
};
};
};
};

9
arch/powerpc/boot/dts/kuroboxHD.dts
View File

@ -15,9 +15,6 @@
XXXX add flash parts, rtc, ??
build with: "dtc -f -I dts -O dtb -o kuroboxHD.dtb -V 16 kuroboxHD.dts"
*/
/ {
@ -50,7 +47,6 @@ build with: "dtc -f -I dts -O dtb -o kuroboxHD.dtb -V 16 kuroboxHD.dts"
soc10x { /* AFAICT need to make soc for 8245's uarts to be defined */
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
compatible = "mpc10x";
store-gathering = <0>; /* 0 == off, !0 == on */
@ -72,7 +68,7 @@ build with: "dtc -f -I dts -O dtb -o kuroboxHD.dtb -V 16 kuroboxHD.dts"
rtc@32 {
device_type = "rtc";
compatible = "ricoh,rs5c372b";
compatible = "ricoh,rs5c372a";
reg = <32>;
};
};
@ -83,7 +79,7 @@ build with: "dtc -f -I dts -O dtb -o kuroboxHD.dtb -V 16 kuroboxHD.dts"
reg = <80004500 8>;
clock-frequency = <5d08d88>;
current-speed = <2580>;
interrupts = <9 2>;
interrupts = <9 0>;
interrupt-parent = <&mpic>;
};
@ -104,7 +100,6 @@ build with: "dtc -f -I dts -O dtb -o kuroboxHD.dtb -V 16 kuroboxHD.dts"
compatible = "chrp,open-pic";
interrupt-controller;
reg = <80040000 40000>;
built-in;
};
pci@fec00000 {

9
arch/powerpc/boot/dts/kuroboxHG.dts
View File

@ -15,9 +15,6 @@
XXXX add flash parts, rtc, ??
build with: "dtc -f -I dts -O dtb -o kuroboxHG.dtb -V 16 kuroboxHG.dts"
*/
/ {
@ -50,7 +47,6 @@ build with: "dtc -f -I dts -O dtb -o kuroboxHG.dtb -V 16 kuroboxHG.dts"
soc10x { /* AFAICT need to make soc for 8245's uarts to be defined */
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
compatible = "mpc10x";
store-gathering = <0>; /* 0 == off, !0 == on */
@ -72,7 +68,7 @@ build with: "dtc -f -I dts -O dtb -o kuroboxHG.dtb -V 16 kuroboxHG.dts"
rtc@32 {
device_type = "rtc";
compatible = "ricoh,rs5c372b";
compatible = "ricoh,rs5c372a";
reg = <32>;
};
};
@ -83,7 +79,7 @@ build with: "dtc -f -I dts -O dtb -o kuroboxHG.dtb -V 16 kuroboxHG.dts"
reg = <80004500 8>;
clock-frequency = <7c044a8>;
current-speed = <2580>;
interrupts = <9 2>;
interrupts = <9 0>;
interrupt-parent = <&mpic>;
};
@ -104,7 +100,6 @@ build with: "dtc -f -I dts -O dtb -o kuroboxHG.dtb -V 16 kuroboxHG.dts"
compatible = "chrp,open-pic";
interrupt-controller;
reg = <80040000 40000>;
built-in;
};
pci@fec00000 {

59
arch/powerpc/boot/dts/lite5200.dts
View File

@ -19,7 +19,7 @@
/ {
model = "fsl,lite5200";
// revision = "1.0";
compatible = "fsl,lite5200\0generic-mpc5200";
compatible = "fsl,lite5200","generic-mpc5200";
#address-cells = <1>;
#size-cells = <1>;
@ -37,7 +37,6 @@
timebase-frequency = <0>; // from bootloader
bus-frequency = <0>; // from bootloader
clock-frequency = <0>; // from bootloader
32-bit;
};
};
@ -50,10 +49,9 @@
model = "fsl,mpc5200";
compatible = "mpc5200";
revision = ""; // from bootloader
#interrupt-cells = <3>;
device_type = "soc";
ranges = <0 f0000000 f0010000>;
reg = <f0000000 00010000>;
ranges = <0 f0000000 0000c000>;
reg = <f0000000 00000100>;
bus-frequency = <0>; // from bootloader
system-frequency = <0>; // from bootloader
@ -69,7 +67,6 @@
device_type = "interrupt-controller";
compatible = "mpc5200-pic";
reg = <500 80>;
built-in;
};
gpt@600 { // General Purpose Timer
@ -185,27 +182,6 @@
interrupt-parent = <&mpc5200_pic>;
};
pci@0d00 {
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
compatible = "mpc5200-pci";
reg = <d00 100>;
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3
c000 0 0 2 &mpc5200_pic 0 0 3
c000 0 0 3 &mpc5200_pic 0 0 3
c000 0 0 4 &mpc5200_pic 0 0 3>;
clock-frequency = <0>; // From boot loader
interrupts = <2 8 0 2 9 0 2 a 0>;
interrupt-parent = <&mpc5200_pic>;
bus-range = <0 0>;
ranges = <42000000 0 80000000 80000000 0 20000000
02000000 0 a0000000 a0000000 0 10000000
01000000 0 00000000 b0000000 0 01000000>;
};
spi@f00 {
device_type = "spi";
compatible = "mpc5200-spi";
@ -216,7 +192,7 @@
usb@1000 {
device_type = "usb-ohci-be";
compatible = "mpc5200-ohci\0ohci-be";
compatible = "mpc5200-ohci","ohci-be";
reg = <1000 ff>;
interrupts = <2 6 0>;
interrupt-parent = <&mpc5200_pic>;
@ -317,7 +293,7 @@
i2c@3d00 {
device_type = "i2c";
compatible = "mpc5200-i2c\0fsl-i2c";
compatible = "mpc5200-i2c","fsl-i2c";
cell-index = <0>;
reg = <3d00 40>;
interrupts = <2 f 0>;
@ -327,7 +303,7 @@
i2c@3d40 {
device_type = "i2c";
compatible = "mpc5200-i2c\0fsl-i2c";
compatible = "mpc5200-i2c","fsl-i2c";
cell-index = <1>;
reg = <3d40 40>;
interrupts = <2 10 0>;
@ -336,8 +312,29 @@
};
sram@8000 {
device_type = "sram";
compatible = "mpc5200-sram\0sram";
compatible = "mpc5200-sram","sram";
reg = <8000 4000>;
};
};
pci@f0000d00 {
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
compatible = "mpc5200-pci";
reg = <f0000d00 100>;
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3
c000 0 0 2 &mpc5200_pic 0 0 3
c000 0 0 3 &mpc5200_pic 0 0 3
c000 0 0 4 &mpc5200_pic 0 0 3>;
clock-frequency = <0>; // From boot loader
interrupts = <2 8 0 2 9 0 2 a 0>;
interrupt-parent = <&mpc5200_pic>;
bus-range = <0 0>;
ranges = <42000000 0 80000000 80000000 0 20000000
02000000 0 a0000000 a0000000 0 10000000
01000000 0 00000000 b0000000 0 01000000>;
};
};

119
arch/powerpc/boot/dts/lite5200b.dts
View File

@ -19,7 +19,7 @@
/ {
model = "fsl,lite5200b";
// revision = "1.0";
compatible = "fsl,lite5200b\0generic-mpc5200";
compatible = "fsl,lite5200b","generic-mpc5200";
#address-cells = <1>;
#size-cells = <1>;
@ -37,7 +37,6 @@
timebase-frequency = <0>; // from bootloader
bus-frequency = <0>; // from bootloader
clock-frequency = <0>; // from bootloader
32-bit;
};
};
@ -50,15 +49,14 @@
model = "fsl,mpc5200b";
compatible = "mpc5200";
revision = ""; // from bootloader
#interrupt-cells = <3>;
device_type = "soc";
ranges = <0 f0000000 f0010000>;
reg = <f0000000 00010000>;
ranges = <0 f0000000 0000c000>;
reg = <f0000000 00000100>;
bus-frequency = <0>; // from bootloader
system-frequency = <0>; // from bootloader
cdm@200 {
compatible = "mpc5200b-cdm\0mpc5200-cdm";
compatible = "mpc5200b-cdm","mpc5200-cdm";
reg = <200 38>;
};
@ -67,13 +65,12 @@
interrupt-controller;
#interrupt-cells = <3>;
device_type = "interrupt-controller";
compatible = "mpc5200b-pic\0mpc5200-pic";
compatible = "mpc5200b-pic","mpc5200-pic";
reg = <500 80>;
built-in;
};
gpt@600 { // General Purpose Timer
compatible = "mpc5200b-gpt\0mpc5200-gpt";
compatible = "mpc5200b-gpt","mpc5200-gpt";
device_type = "gpt";
cell-index = <0>;
reg = <600 10>;
@ -83,7 +80,7 @@
};
gpt@610 { // General Purpose Timer
compatible = "mpc5200b-gpt\0mpc5200-gpt";
compatible = "mpc5200b-gpt","mpc5200-gpt";
device_type = "gpt";
cell-index = <1>;
reg = <610 10>;
@ -92,7 +89,7 @@
};
gpt@620 { // General Purpose Timer
compatible = "mpc5200b-gpt\0mpc5200-gpt";
compatible = "mpc5200b-gpt","mpc5200-gpt";
device_type = "gpt";
cell-index = <2>;
reg = <620 10>;
@ -101,7 +98,7 @@
};
gpt@630 { // General Purpose Timer
compatible = "mpc5200b-gpt\0mpc5200-gpt";
compatible = "mpc5200b-gpt","mpc5200-gpt";
device_type = "gpt";
cell-index = <3>;
reg = <630 10>;
@ -110,7 +107,7 @@
};
gpt@640 { // General Purpose Timer
compatible = "mpc5200b-gpt\0mpc5200-gpt";
compatible = "mpc5200b-gpt","mpc5200-gpt";
device_type = "gpt";
cell-index = <4>;
reg = <640 10>;
@ -119,7 +116,7 @@
};
gpt@650 { // General Purpose Timer
compatible = "mpc5200b-gpt\0mpc5200-gpt";
compatible = "mpc5200b-gpt","mpc5200-gpt";
device_type = "gpt";
cell-index = <5>;
reg = <650 10>;
@ -128,7 +125,7 @@
};
gpt@660 { // General Purpose Timer
compatible = "mpc5200b-gpt\0mpc5200-gpt";
compatible = "mpc5200b-gpt","mpc5200-gpt";
device_type = "gpt";
cell-index = <6>;
reg = <660 10>;
@ -137,7 +134,7 @@
};
gpt@670 { // General Purpose Timer
compatible = "mpc5200b-gpt\0mpc5200-gpt";
compatible = "mpc5200b-gpt","mpc5200-gpt";
device_type = "gpt";
cell-index = <7>;
reg = <670 10>;
@ -146,7 +143,7 @@
};
rtc@800 { // Real time clock
compatible = "mpc5200b-rtc\0mpc5200-rtc";
compatible = "mpc5200b-rtc","mpc5200-rtc";
device_type = "rtc";
reg = <800 100>;
interrupts = <1 5 0 1 6 0>;
@ -155,7 +152,7 @@
mscan@900 {
device_type = "mscan";
compatible = "mpc5200b-mscan\0mpc5200-mscan";
compatible = "mpc5200b-mscan","mpc5200-mscan";
cell-index = <0>;
interrupts = <2 11 0>;
interrupt-parent = <&mpc5200_pic>;
@ -164,7 +161,7 @@
mscan@980 {
device_type = "mscan";
compatible = "mpc5200b-mscan\0mpc5200-mscan";
compatible = "mpc5200b-mscan","mpc5200-mscan";
cell-index = <1>;
interrupts = <2 12 0>;
interrupt-parent = <&mpc5200_pic>;
@ -172,48 +169,22 @@
};
gpio@b00 {
compatible = "mpc5200b-gpio\0mpc5200-gpio";
compatible = "mpc5200b-gpio","mpc5200-gpio";
reg = <b00 40>;
interrupts = <1 7 0>;
interrupt-parent = <&mpc5200_pic>;
};
gpio-wkup@c00 {
compatible = "mpc5200b-gpio-wkup\0mpc5200-gpio-wkup";
compatible = "mpc5200b-gpio-wkup","mpc5200-gpio-wkup";
reg = <c00 40>;
interrupts = <1 8 0 0 3 0>;
interrupt-parent = <&mpc5200_pic>;
};
pci@0d00 {
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
compatible = "mpc5200b-pci\0mpc5200-pci";
reg = <d00 100>;
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
c000 0 0 2 &mpc5200_pic 1 1 3
c000 0 0 3 &mpc5200_pic 1 2 3
c000 0 0 4 &mpc5200_pic 1 3 3
c800 0 0 1 &mpc5200_pic 1 1 3 // 2nd slot
c800 0 0 2 &mpc5200_pic 1 2 3
c800 0 0 3 &mpc5200_pic 1 3 3
c800 0 0 4 &mpc5200_pic 0 0 3>;
clock-frequency = <0>; // From boot loader
interrupts = <2 8 0 2 9 0 2 a 0>;
interrupt-parent = <&mpc5200_pic>;
bus-range = <0 0>;
ranges = <42000000 0 80000000 80000000 0 20000000
02000000 0 a0000000 a0000000 0 10000000
01000000 0 00000000 b0000000 0 01000000>;
};
spi@f00 {
device_type = "spi";
compatible = "mpc5200b-spi\0mpc5200-spi";
compatible = "mpc5200b-spi","mpc5200-spi";
reg = <f00 20>;
interrupts = <2 d 0 2 e 0>;
interrupt-parent = <&mpc5200_pic>;
@ -221,7 +192,7 @@
usb@1000 {
device_type = "usb-ohci-be";
compatible = "mpc5200b-ohci\0mpc5200-ohci\0ohci-be";
compatible = "mpc5200b-ohci","mpc5200-ohci","ohci-be";
reg = <1000 ff>;
interrupts = <2 6 0>;
interrupt-parent = <&mpc5200_pic>;
@ -229,7 +200,7 @@
bestcomm@1200 {
device_type = "dma-controller";
compatible = "mpc5200b-bestcomm\0mpc5200-bestcomm";
compatible = "mpc5200b-bestcomm","mpc5200-bestcomm";
reg = <1200 80>;
interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
3 4 0 3 5 0 3 6 0 3 7 0
@ -239,13 +210,13 @@
};
xlb@1f00 {
compatible = "mpc5200b-xlb\0mpc5200-xlb";
compatible = "mpc5200b-xlb","mpc5200-xlb";
reg = <1f00 100>;
};
serial@2000 { // PSC1
device_type = "serial";
compatible = "mpc5200b-psc-uart\0mpc5200-psc-uart";
compatible = "mpc5200b-psc-uart","mpc5200-psc-uart";
port-number = <0>; // Logical port assignment
cell-index = <0>;
reg = <2000 100>;
@ -256,7 +227,7 @@
// PSC2 in ac97 mode example
//ac97@2200 { // PSC2
// device_type = "sound";
// compatible = "mpc5200b-psc-ac97\0mpc5200-psc-ac97";
// compatible = "mpc5200b-psc-ac97","mpc5200-psc-ac97";
// cell-index = <1>;
// reg = <2200 100>;
// interrupts = <2 2 0>;
@ -276,7 +247,7 @@
// PSC4 in uart mode example
//serial@2600 { // PSC4
// device_type = "serial";
// compatible = "mpc5200b-psc-uart\0mpc5200-psc-uart";
// compatible = "mpc5200b-psc-uart","mpc5200-psc-uart";
// cell-index = <3>;
// reg = <2600 100>;
// interrupts = <2 b 0>;
@ -286,7 +257,7 @@
// PSC5 in uart mode example
//serial@2800 { // PSC5
// device_type = "serial";
// compatible = "mpc5200b-psc-uart\0mpc5200-psc-uart";
// compatible = "mpc5200b-psc-uart","mpc5200-psc-uart";
// cell-index = <4>;
// reg = <2800 100>;
// interrupts = <2 c 0>;
@ -296,7 +267,7 @@
// PSC6 in spi mode example
//spi@2c00 { // PSC6
// device_type = "spi";
// compatible = "mpc5200b-psc-spi\0mpc5200-psc-spi";
// compatible = "mpc5200b-psc-spi","mpc5200-psc-spi";
// cell-index = <5>;
// reg = <2c00 100>;
// interrupts = <2 4 0>;
@ -305,7 +276,7 @@
ethernet@3000 {
device_type = "network";
compatible = "mpc5200b-fec\0mpc5200-fec";
compatible = "mpc5200b-fec","mpc5200-fec";
reg = <3000 800>;
mac-address = [ 02 03 04 05 06 07 ]; // Bad!
interrupts = <2 5 0>;
@ -314,7 +285,7 @@
ata@3a00 {
device_type = "ata";
compatible = "mpc5200b-ata\0mpc5200-ata";
compatible = "mpc5200b-ata","mpc5200-ata";
reg = <3a00 100>;
interrupts = <2 7 0>;
interrupt-parent = <&mpc5200_pic>;
@ -322,7 +293,7 @@
i2c@3d00 {
device_type = "i2c";
compatible = "mpc5200b-i2c\0mpc5200-i2c\0fsl-i2c";
compatible = "mpc5200b-i2c","mpc5200-i2c","fsl-i2c";
cell-index = <0>;
reg = <3d00 40>;
interrupts = <2 f 0>;
@ -332,7 +303,7 @@
i2c@3d40 {
device_type = "i2c";
compatible = "mpc5200b-i2c\0mpc5200-i2c\0fsl-i2c";
compatible = "mpc5200b-i2c","mpc5200-i2c","fsl-i2c";
cell-index = <1>;
reg = <3d40 40>;
interrupts = <2 10 0>;
@ -341,8 +312,34 @@
};
sram@8000 {
device_type = "sram";
compatible = "mpc5200b-sram\0mpc5200-sram\0sram";
compatible = "mpc5200b-sram","mpc5200-sram","sram";
reg = <8000 4000>;
};
};
pci@f0000d00 {
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
compatible = "mpc5200b-pci","mpc5200-pci";
reg = <f0000d00 100>;
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
c000 0 0 2 &mpc5200_pic 1 1 3
c000 0 0 3 &mpc5200_pic 1 2 3
c000 0 0 4 &mpc5200_pic 1 3 3
c800 0 0 1 &mpc5200_pic 1 1 3 // 2nd slot
c800 0 0 2 &mpc5200_pic 1 2 3
c800 0 0 3 &mpc5200_pic 1 3 3
c800 0 0 4 &mpc5200_pic 0 0 3>;
clock-frequency = <0>; // From boot loader
interrupts = <2 8 0 2 9 0 2 a 0>;
interrupt-parent = <&mpc5200_pic>;
bus-range = <0 0>;
ranges = <42000000 0 80000000 80000000 0 20000000
02000000 0 a0000000 a0000000 0 10000000
01000000 0 00000000 b0000000 0 01000000>;
};
};

9
arch/powerpc/boot/dts/mpc7448hpc2.dts
View File

@ -31,7 +31,6 @@
timebase-frequency = <0>; // 33 MHz, from uboot
clock-frequency = <0>; // From U-Boot
bus-frequency = <0>; // From U-Boot
32-bit;
};
};
@ -44,7 +43,6 @@
tsi108@c0000000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "tsi-bridge";
ranges = <00000000 c0000000 00010000>;
reg = <c0000000 00010000>;
@ -80,6 +78,7 @@
};
ethernet@6200 {
linux,network-index = <0>;
#size-cells = <0>;
device_type = "network";
compatible = "tsi108-ethernet";
@ -92,6 +91,7 @@
};
ethernet@6600 {
linux,network-index = <1>;
#address-cells = <1>;
#size-cells = <0>;
device_type = "network";
@ -128,7 +128,6 @@
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <7400 400>;
built-in;
compatible = "chrp,open-pic";
device_type = "open-pic";
big-endian;
@ -180,12 +179,14 @@
device_type = "pic-router";
#address-cells = <0>;
#interrupt-cells = <2>;
built-in;
big-endian;
interrupts = <17 2>;
interrupt-parent = <&mpic>;
};
};
};
chosen {
linux,stdout-path = "/tsi108@c0000000/serial@7808";
};
};

401
arch/powerpc/boot/dts/mpc8272ads.dts
View File

@ -10,207 +10,240 @@
*/
/ {
model = "MPC8272ADS";
compatible = "MPC8260ADS";
#address-cells = <1>;
#size-cells = <1>;
model = "MPC8272ADS";
compatible = "fsl,mpc8272ads";
#address-cells = <1>;
#size-cells = <1>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,8272@0 {
device_type = "cpu";
reg = <0>;
d-cache-line-size = <20>; // 32 bytes
i-cache-line-size = <20>; // 32 bytes
d-cache-size = <4000>; // L1, 16K
i-cache-size = <4000>; // L1, 16K
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
32-bit;
};
};
PowerPC,8272@0 {
device_type = "cpu";
reg = <0>;
d-cache-line-size = <d#32>;
i-cache-line-size = <d#32>;
d-cache-size = <d#16384>;
i-cache-size = <d#16384>;
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
};
};
pci_pic: interrupt-controller@f8200000 {
#address-cells = <0>;
#interrupt-cells = <2>;
interrupt-controller;
reg = <f8200000 f8200004>;
built-in;
device_type = "pci-pic";
};
memory {
device_type = "memory";
reg = <00000000 4000000 f4500000 00000020>;
};
memory {
device_type = "memory";
reg = <0 0>;
};
chosen {
name = "chosen";
linux,platform = <0>;
interrupt-controller = <&Cpm_pic>;
};
localbus@f0010100 {
compatible = "fsl,mpc8272-localbus",
"fsl,pq2-localbus";
#address-cells = <2>;
#size-cells = <1>;
reg = <f0010100 40>;
soc8272@f0000000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
ranges = <00000000 f0000000 00053000>;
reg = <f0000000 10000>;
ranges = <0 0 fe000000 02000000
1 0 f4500000 00008000
3 0 f8200000 00008000>;
mdio@0 {
device_type = "mdio";
compatible = "fs_enet";
reg = <0 0>;
#address-cells = <1>;
#size-cells = <0>;
phy0:ethernet-phy@0 {
interrupt-parent = <&Cpm_pic>;
interrupts = <17 4>;
reg = <0>;
bitbang = [ 12 12 13 02 02 01 ];
device_type = "ethernet-phy";
};
phy1:ethernet-phy@1 {
interrupt-parent = <&Cpm_pic>;
interrupts = <17 4>;
bitbang = [ 12 12 13 02 02 01 ];
reg = <3>;
device_type = "ethernet-phy";
};
};
flash@0,0 {
compatible = "jedec-flash";
reg = <0 0 2000000>;
bank-width = <4>;
device-width = <1>;
};
ethernet@24000 {
#address-cells = <1>;
#size-cells = <0>;
device_type = "network";
device-id = <1>;
compatible = "fs_enet";
model = "FCC";
reg = <11300 20 8400 100 11380 30>;
mac-address = [ 00 11 2F 99 43 54 ];
interrupts = <20 2>;
interrupt-parent = <&Cpm_pic>;
phy-handle = <&Phy0>;
rx-clock = <13>;
tx-clock = <12>;
};
board-control@1,0 {
reg = <1 0 20>;
compatible = "fsl,mpc8272ads-bcsr";
};
ethernet@25000 {
device_type = "network";
device-id = <2>;
compatible = "fs_enet";
model = "FCC";
reg = <11320 20 8500 100 113b0 30>;
mac-address = [ 00 11 2F 99 44 54 ];
interrupts = <21 2>;
interrupt-parent = <&Cpm_pic>;
phy-handle = <&Phy1>;
rx-clock = <17>;
tx-clock = <18>;
};
PCI_PIC: interrupt-controller@3,0 {
compatible = "fsl,mpc8272ads-pci-pic",
"fsl,pq2ads-pci-pic";
#interrupt-cells = <1>;
interrupt-controller;
reg = <3 0 8>;
interrupt-parent = <&PIC>;
interrupts = <14 8>;
};
};
cpm@f0000000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "cpm";
model = "CPM2";
ranges = <00000000 00000000 20000>;
reg = <0 20000>;
command-proc = <119c0>;
brg-frequency = <17D7840>;
cpm_clk = <BEBC200>;
scc@11a00 {
device_type = "serial";
compatible = "cpm_uart";
model = "SCC";
device-id = <1>;
reg = <11a00 20 8000 100>;
current-speed = <1c200>;
interrupts = <28 2>;
interrupt-parent = <&Cpm_pic>;
clock-setup = <0 00ffffff>;
rx-clock = <1>;
tx-clock = <1>;
};
pci@f0010800 {
device_type = "pci";
reg = <f0010800 10c f00101ac 8 f00101c4 8>;
compatible = "fsl,mpc8272-pci", "fsl,pq2-pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
clock-frequency = <d#66666666>;
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x16 */
b000 0 0 1 &PCI_PIC 0
b000 0 0 2 &PCI_PIC 1
b000 0 0 3 &PCI_PIC 2
b000 0 0 4 &PCI_PIC 3
scc@11a60 {
device_type = "serial";
compatible = "cpm_uart";
model = "SCC";
device-id = <4>;
reg = <11a60 20 8300 100>;
current-speed = <1c200>;
interrupts = <2b 2>;
interrupt-parent = <&Cpm_pic>;
clock-setup = <1b ffffff00>;
rx-clock = <4>;
tx-clock = <4>;
};
/* IDSEL 0x17 */
b800 0 0 1 &PCI_PIC 4
b800 0 0 2 &PCI_PIC 5
b800 0 0 3 &PCI_PIC 6
b800 0 0 4 &PCI_PIC 7
};
cpm_pic:interrupt-controller@10c00 {
#address-cells = <0>;
#interrupt-cells = <2>;
interrupt-controller;
reg = <10c00 80>;
built-in;
device_type = "cpm-pic";
compatible = "CPM2";
};
pci@0500 {
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
compatible = "8272";
device_type = "pci";
reg = <10430 4dc>;
clock-frequency = <3f940aa>;
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x18 */
c000 0 0 1 &PCI_PIC 8
c000 0 0 2 &PCI_PIC 9
c000 0 0 3 &PCI_PIC a
c000 0 0 4 &PCI_PIC b>;
/* IDSEL 0x16 */
b000 0 0 1 f8200000 40 8
b000 0 0 2 f8200000 41 8
b000 0 0 3 f8200000 42 8
b000 0 0 4 f8200000 43 8
interrupt-parent = <&PIC>;
interrupts = <12 8>;
ranges = <42000000 0 80000000 80000000 0 20000000
02000000 0 a0000000 a0000000 0 20000000
01000000 0 00000000 f6000000 0 02000000>;
};
/* IDSEL 0x17 */
b800 0 0 1 f8200000 43 8
b800 0 0 2 f8200000 40 8
b800 0 0 3 f8200000 41 8
b800 0 0 4 f8200000 42 8
soc@f0000000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
compatible = "fsl,mpc8272", "fsl,pq2-soc";
ranges = <00000000 f0000000 00053000>;
/* IDSEL 0x18 */
c000 0 0 1 f8200000 42 8
c000 0 0 2 f8200000 43 8
c000 0 0 3 f8200000 40 8
c000 0 0 4 f8200000 41 8>;
interrupt-parent = <&Cpm_pic>;
interrupts = <14 8>;
bus-range = <0 0>;
ranges = <02000000 0 80000000 80000000 0 40000000
01000000 0 00000000 f6000000 0 02000000>;
};
// Temporary -- will go away once kernel uses ranges for get_immrbase().
reg = <f0000000 00053000>;
cpm@119c0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8272-cpm", "fsl,cpm2";
reg = <119c0 30>;
ranges;
muram@0 {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 10000>;
data@0 {
compatible = "fsl,cpm-muram-data";
reg = <0 2000 9800 800>;
};
};
brg@119f0 {
compatible = "fsl,mpc8272-brg",
"fsl,cpm2-brg",
"fsl,cpm-brg";
reg = <119f0 10 115f0 10>;
};
serial@11a00 {
device_type = "serial";
compatible = "fsl,mpc8272-scc-uart",
"fsl,cpm2-scc-uart";
reg = <11a00 20 8000 100>;
interrupts = <28 8>;
interrupt-parent = <&PIC>;
fsl,cpm-brg = <1>;
fsl,cpm-command = <00800000>;
};
serial@11a60 {
device_type = "serial";
compatible = "fsl,mpc8272-scc-uart",
"fsl,cpm2-scc-uart";
reg = <11a60 20 8300 100>;
interrupts = <2b 8>;
interrupt-parent = <&PIC>;
fsl,cpm-brg = <4>;
fsl,cpm-command = <0ce00000>;
};
mdio@10d40 {
device_type = "mdio";
compatible = "fsl,mpc8272ads-mdio-bitbang",
"fsl,mpc8272-mdio-bitbang",
"fsl,cpm2-mdio-bitbang";
reg = <10d40 14>;
#address-cells = <1>;
#size-cells = <0>;
fsl,mdio-pin = <12>;
fsl,mdc-pin = <13>;
PHY0: ethernet-phy@0 {
interrupt-parent = <&PIC>;
interrupts = <17 8>;
reg = <0>;
device_type = "ethernet-phy";
};
PHY1: ethernet-phy@1 {
interrupt-parent = <&PIC>;
interrupts = <17 8>;
reg = <3>;
device_type = "ethernet-phy";
};
};
ethernet@11300 {
device_type = "network";
compatible = "fsl,mpc8272-fcc-enet",
"fsl,cpm2-fcc-enet";
reg = <11300 20 8400 100 11390 1>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <20 8>;
interrupt-parent = <&PIC>;
phy-handle = <&PHY0>;
linux,network-index = <0>;
fsl,cpm-command = <12000300>;
};
ethernet@11320 {
device_type = "network";
compatible = "fsl,mpc8272-fcc-enet",
"fsl,cpm2-fcc-enet";
reg = <11320 20 8500 100 113b0 1>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <21 8>;
interrupt-parent = <&PIC>;
phy-handle = <&PHY1>;
linux,network-index = <1>;
fsl,cpm-command = <16200300>;
};
};
PIC: interrupt-controller@10c00 {
#interrupt-cells = <2>;
interrupt-controller;
reg = <10c00 80>;
compatible = "fsl,mpc8272-pic", "fsl,cpm2-pic";
};
/* May need to remove if on a part without crypto engine */
crypto@30000 {
device_type = "crypto";
model = "SEC2";
compatible = "talitos";
reg = <30000 10000>;
interrupts = <b 2>;
interrupt-parent = <&Cpm_pic>;
num-channels = <4>;
channel-fifo-len = <18>;
exec-units-mask = <0000007e>;
crypto@30000 {
device_type = "crypto";
model = "SEC2";
compatible = "fsl,mpc8272-talitos-sec2",
"fsl,talitos-sec2",
"fsl,talitos",
"talitos";
reg = <30000 10000>;
interrupts = <b 8>;
interrupt-parent = <&PIC>;
num-channels = <4>;
channel-fifo-len = <18>;
exec-units-mask = <0000007e>;
/* desc mask is for rev1.x, we need runtime fixup for >=2.x */
descriptor-types-mask = <01010ebf>;
};
descriptor-types-mask = <01010ebf>;
};
};
};
chosen {
linux,stdout-path = "/soc/cpm/serial@11a00";
};
};

67
arch/powerpc/boot/dts/mpc8313erdb.dts
View File

@ -29,7 +29,6 @@
timebase-frequency = <0>; // from bootloader
bus-frequency = <0>; // from bootloader
clock-frequency = <0>; // from bootloader
32-bit;
};
};
@ -41,7 +40,6 @@
soc8313@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00000200>;
@ -73,11 +71,11 @@
spi@7000 {
device_type = "spi";
compatible = "mpc83xx_spi";
compatible = "fsl_spi";
reg = <7000 1000>;
interrupts = <10 8>;
interrupt-parent = < &ipic >;
mode = <0>;
mode = "cpu";
};
/* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
@ -152,36 +150,6 @@
interrupt-parent = < &ipic >;
};
pci@8500 {
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x0E -mini PCI */
7000 0 0 1 &ipic 12 8
7000 0 0 2 &ipic 12 8
7000 0 0 3 &ipic 12 8
7000 0 0 4 &ipic 12 8
/* IDSEL 0x0F - PCI slot */
7800 0 0 1 &ipic 11 8
7800 0 0 2 &ipic 12 8
7800 0 0 3 &ipic 11 8
7800 0 0 4 &ipic 12 8>;
interrupt-parent = < &ipic >;
interrupts = <42 8>;
bus-range = <0 0>;
ranges = <02000000 0 90000000 90000000 0 10000000
42000000 0 80000000 80000000 0 10000000
01000000 0 00000000 e2000000 0 00100000>;
clock-frequency = <3f940aa>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <8500 100>;
compatible = "fsl,mpc8349-pci";
device_type = "pci";
};
crypto@30000 {
device_type = "crypto";
model = "SEC2";
@ -207,8 +175,37 @@
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <700 100>;
built-in;
device_type = "ipic";
};
};
pci@e0008500 {
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x0E -mini PCI */
7000 0 0 1 &ipic 12 8
7000 0 0 2 &ipic 12 8
7000 0 0 3 &ipic 12 8
7000 0 0 4 &ipic 12 8
/* IDSEL 0x0F - PCI slot */
7800 0 0 1 &ipic 11 8
7800 0 0 2 &ipic 12 8
7800 0 0 3 &ipic 11 8
7800 0 0 4 &ipic 12 8>;
interrupt-parent = < &ipic >;
interrupts = <42 8>;
bus-range = <0 0>;
ranges = <02000000 0 90000000 90000000 0 10000000
42000000 0 80000000 80000000 0 10000000
01000000 0 00000000 e2000000 0 00100000>;
clock-frequency = <3f940aa>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <e0008500 100>;
compatible = "fsl,mpc8349-pci";
device_type = "pci";
};
};

122
arch/powerpc/boot/dts/mpc832x_mds.dts
View File

@ -29,7 +29,6 @@
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
32-bit;
};
};
@ -46,7 +45,6 @@
soc8323@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00000200>;
@ -99,71 +97,11 @@
descriptor-types-mask = <0122003f>;
};
pci@8500 {
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x11 AD17 */
8800 0 0 1 &ipic 14 8
8800 0 0 2 &ipic 15 8
8800 0 0 3 &ipic 16 8
8800 0 0 4 &ipic 17 8
/* IDSEL 0x12 AD18 */
9000 0 0 1 &ipic 16 8
9000 0 0 2 &ipic 17 8
9000 0 0 3 &ipic 14 8
9000 0 0 4 &ipic 15 8
/* IDSEL 0x13 AD19 */
9800 0 0 1 &ipic 17 8
9800 0 0 2 &ipic 14 8
9800 0 0 3 &ipic 15 8
9800 0 0 4 &ipic 16 8
/* IDSEL 0x15 AD21*/
a800 0 0 1 &ipic 14 8
a800 0 0 2 &ipic 15 8
a800 0 0 3 &ipic 16 8
a800 0 0 4 &ipic 17 8
/* IDSEL 0x16 AD22*/
b000 0 0 1 &ipic 17 8
b000 0 0 2 &ipic 14 8
b000 0 0 3 &ipic 15 8
b000 0 0 4 &ipic 16 8
/* IDSEL 0x17 AD23*/
b800 0 0 1 &ipic 16 8
b800 0 0 2 &ipic 17 8
b800 0 0 3 &ipic 14 8
b800 0 0 4 &ipic 15 8
/* IDSEL 0x18 AD24*/
c000 0 0 1 &ipic 15 8
c000 0 0 2 &ipic 16 8
c000 0 0 3 &ipic 17 8
c000 0 0 4 &ipic 14 8>;
interrupt-parent = < &ipic >;
interrupts = <42 8>;
bus-range = <0 0>;
ranges = <02000000 0 90000000 90000000 0 10000000
42000000 0 80000000 80000000 0 10000000
01000000 0 00000000 d0000000 0 00100000>;
clock-frequency = <0>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <8500 100>;
compatible = "fsl,mpc8349-pci";
device_type = "pci";
};
ipic: pic@700 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <700 100>;
built-in;
device_type = "ipic";
};
@ -333,10 +271,68 @@
#address-cells = <0>;
#interrupt-cells = <1>;
reg = <80 80>;
built-in;
big-endian;
interrupts = <20 8 21 8>; //high:32 low:33
interrupt-parent = < &ipic >;
};
};
pci@e0008500 {
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x11 AD17 */
8800 0 0 1 &ipic 14 8
8800 0 0 2 &ipic 15 8
8800 0 0 3 &ipic 16 8
8800 0 0 4 &ipic 17 8
/* IDSEL 0x12 AD18 */
9000 0 0 1 &ipic 16 8
9000 0 0 2 &ipic 17 8
9000 0 0 3 &ipic 14 8
9000 0 0 4 &ipic 15 8
/* IDSEL 0x13 AD19 */
9800 0 0 1 &ipic 17 8
9800 0 0 2 &ipic 14 8
9800 0 0 3 &ipic 15 8
9800 0 0 4 &ipic 16 8
/* IDSEL 0x15 AD21*/
a800 0 0 1 &ipic 14 8
a800 0 0 2 &ipic 15 8
a800 0 0 3 &ipic 16 8
a800 0 0 4 &ipic 17 8
/* IDSEL 0x16 AD22*/
b000 0 0 1 &ipic 17 8
b000 0 0 2 &ipic 14 8
b000 0 0 3 &ipic 15 8
b000 0 0 4 &ipic 16 8
/* IDSEL 0x17 AD23*/
b800 0 0 1 &ipic 16 8
b800 0 0 2 &ipic 17 8
b800 0 0 3 &ipic 14 8
b800 0 0 4 &ipic 15 8
/* IDSEL 0x18 AD24*/
c000 0 0 1 &ipic 15 8
c000 0 0 2 &ipic 16 8
c000 0 0 3 &ipic 17 8
c000 0 0 4 &ipic 14 8>;
interrupt-parent = < &ipic >;
interrupts = <42 8>;
bus-range = <0 0>;
ranges = <02000000 0 90000000 90000000 0 10000000
42000000 0 80000000 80000000 0 10000000
01000000 0 00000000 d0000000 0 00100000>;
clock-frequency = <0>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <e0008500 100>;
compatible = "fsl,mpc8349-pci";
device_type = "pci";
};
};

72
arch/powerpc/boot/dts/mpc832x_rdb.dts
View File

@ -29,7 +29,6 @@
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
32-bit;
};
};
@ -41,7 +40,6 @@
soc8323@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00000200>;
@ -94,45 +92,11 @@
descriptor-types-mask = <0122003f>;
};
pci@8500 {
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x10 AD16 (USB) */
8000 0 0 1 &pic 11 8
/* IDSEL 0x11 AD17 (Mini1)*/
8800 0 0 1 &pic 12 8
8800 0 0 2 &pic 13 8
8800 0 0 3 &pic 14 8
8800 0 0 4 &pic 30 8
/* IDSEL 0x12 AD18 (PCI/Mini2) */
9000 0 0 1 &pic 13 8
9000 0 0 2 &pic 14 8
9000 0 0 3 &pic 30 8
9000 0 0 4 &pic 11 8>;
interrupt-parent = <&pic>;
interrupts = <42 8>;
bus-range = <0 0>;
ranges = <42000000 0 80000000 80000000 0 10000000
02000000 0 90000000 90000000 0 10000000
01000000 0 d0000000 d0000000 0 04000000>;
clock-frequency = <0>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <8500 100>;
compatible = "fsl,mpc8349-pci";
device_type = "pci";
};
pic:pic@700 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <700 100>;
built-in;
device_type = "ipic";
};
@ -211,7 +175,7 @@
reg = <4c0 40>;
interrupts = <2>;
interrupt-parent = <&qeic>;
mode = "cpu";
mode = "cpu-qe";
};
spi@500 {
@ -292,10 +256,42 @@
#address-cells = <0>;
#interrupt-cells = <1>;
reg = <80 80>;
built-in;
big-endian;
interrupts = <20 8 21 8>; //high:32 low:33
interrupt-parent = <&pic>;
};
};
pci@e0008500 {
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x10 AD16 (USB) */
8000 0 0 1 &pic 11 8
/* IDSEL 0x11 AD17 (Mini1)*/
8800 0 0 1 &pic 12 8
8800 0 0 2 &pic 13 8
8800 0 0 3 &pic 14 8
8800 0 0 4 &pic 30 8
/* IDSEL 0x12 AD18 (PCI/Mini2) */
9000 0 0 1 &pic 13 8
9000 0 0 2 &pic 14 8
9000 0 0 3 &pic 30 8
9000 0 0 4 &pic 11 8>;
interrupt-parent = <&pic>;
interrupts = <42 8>;
bus-range = <0 0>;
ranges = <42000000 0 80000000 80000000 0 10000000
02000000 0 90000000 90000000 0 10000000
01000000 0 d0000000 d0000000 0 04000000>;
clock-frequency = <0>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <e0008500 100>;
compatible = "fsl,mpc8349-pci";
device_type = "pci";
};
};

104
arch/powerpc/boot/dts/mpc8349emitx.dts
View File

@ -28,7 +28,6 @@
timebase-frequency = <0>; // from bootloader
bus-frequency = <0>; // from bootloader
clock-frequency = <0>; // from bootloader
32-bit;
};
};
@ -40,7 +39,6 @@
soc8349@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00000200>;
@ -72,11 +70,11 @@
spi@7000 {
device_type = "spi";
compatible = "mpc83xx_spi";
compatible = "fsl_spi";
reg = <7000 1000>;
interrupts = <10 8>;
interrupt-parent = < &ipic >;
mode = <0>;
mode = "cpu";
};
usb@22000 {
@ -142,6 +140,7 @@
interrupts = <20 8 21 8 22 8>;
interrupt-parent = < &ipic >;
phy-handle = < &phy1c >;
linux,network-index = <0>;
};
ethernet@25000 {
@ -161,6 +160,7 @@
interrupts = <23 8 24 8 25 8>;
interrupt-parent = < &ipic >;
phy-handle = < &phy1f >;
linux,network-index = <1>;
};
serial@4500 {
@ -181,52 +181,6 @@
interrupt-parent = < &ipic >;
};
pci@8500 {
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x10 - SATA */
8000 0 0 1 &ipic 16 8 /* SATA_INTA */
>;
interrupt-parent = < &ipic >;
interrupts = <42 8>;
bus-range = <0 0>;
ranges = <42000000 0 80000000 80000000 0 10000000
02000000 0 90000000 90000000 0 10000000
01000000 0 00000000 e2000000 0 01000000>;
clock-frequency = <3f940aa>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <8500 100>;
compatible = "fsl,mpc8349-pci";
device_type = "pci";
};
pci@8600 {
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x0E - MiniPCI Slot */
7000 0 0 1 &ipic 15 8 /* PCI_INTA */
/* IDSEL 0x0F - PCI Slot */
7800 0 0 1 &ipic 14 8 /* PCI_INTA */
7800 0 0 2 &ipic 15 8 /* PCI_INTB */
>;
interrupt-parent = < &ipic >;
interrupts = <43 8>;
bus-range = <1 1>;
ranges = <42000000 0 a0000000 a0000000 0 10000000
02000000 0 b0000000 b0000000 0 10000000
01000000 0 00000000 e3000000 0 01000000>;
clock-frequency = <3f940aa>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <8600 100>;
compatible = "fsl,mpc8349-pci";
device_type = "pci";
};
crypto@30000 {
device_type = "crypto";
model = "SEC2";
@ -245,8 +199,56 @@
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <700 100>;
built-in;
device_type = "ipic";
};
};
pci@e0008500 {
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x10 - SATA */
8000 0 0 1 &ipic 16 8 /* SATA_INTA */
>;
interrupt-parent = < &ipic >;
interrupts = <42 8>;
bus-range = <0 0>;
ranges = <42000000 0 80000000 80000000 0 10000000
02000000 0 90000000 90000000 0 10000000
01000000 0 00000000 e2000000 0 01000000>;
clock-frequency = <3f940aa>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <e0008500 100>;
compatible = "fsl,mpc8349-pci";
device_type = "pci";
};
pci@e0008600 {
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x0E - MiniPCI Slot */
7000 0 0 1 &ipic 15 8 /* PCI_INTA */
/* IDSEL 0x0F - PCI Slot */
7800 0 0 1 &ipic 14 8 /* PCI_INTA */
7800 0 0 2 &ipic 15 8 /* PCI_INTB */
>;
interrupt-parent = < &ipic >;
interrupts = <43 8>;
bus-range = <0 0>;
ranges = <42000000 0 a0000000 a0000000 0 10000000
02000000 0 b0000000 b0000000 0 10000000
01000000 0 00000000 e3000000 0 01000000>;
clock-frequency = <3f940aa>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <e0008600 100>;
compatible = "fsl,mpc8349-pci";
device_type = "pci";
};
};

52
arch/powerpc/boot/dts/mpc8349emitxgp.dts
View File

@ -28,7 +28,6 @@
timebase-frequency = <0>; // from bootloader
bus-frequency = <0>; // from bootloader
clock-frequency = <0>; // from bootloader
32-bit;
};
};
@ -40,7 +39,6 @@
soc8349@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00000200>;
@ -72,11 +70,11 @@
spi@7000 {
device_type = "spi";
compatible = "mpc83xx_spi";
compatible = "fsl_spi";
reg = <7000 1000>;
interrupts = <10 8>;
interrupt-parent = < &ipic >;
mode = <0>;
mode = "cpu";
};
usb@23000 {
@ -116,6 +114,7 @@
interrupts = <20 8 21 8 22 8>;
interrupt-parent = < &ipic >;
phy-handle = < &phy1c >;
linux,network-index = <0>;
};
serial@4500 {
@ -136,28 +135,6 @@
interrupt-parent = < &ipic >;
};
pci@8600 {
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x0F - PCI Slot */
7800 0 0 1 &ipic 14 8 /* PCI_INTA */
7800 0 0 2 &ipic 15 8 /* PCI_INTB */
>;
interrupt-parent = < &ipic >;
interrupts = <43 8>;
bus-range = <1 1>;
ranges = <42000000 0 a0000000 a0000000 0 10000000
02000000 0 b0000000 b0000000 0 10000000
01000000 0 00000000 e3000000 0 01000000>;
clock-frequency = <3f940aa>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <8600 100>;
compatible = "fsl,mpc8349-pci";
device_type = "pci";
};
crypto@30000 {
device_type = "crypto";
model = "SEC2";
@ -176,8 +153,29 @@
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <700 100>;
built-in;
device_type = "ipic";
};
};
pci@e0008600 {
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x0F - PCI Slot */
7800 0 0 1 &ipic 14 8 /* PCI_INTA */
7800 0 0 2 &ipic 15 8 /* PCI_INTB */
>;
interrupt-parent = < &ipic >;
interrupts = <43 8>;
bus-range = <1 1>;
ranges = <42000000 0 a0000000 a0000000 0 10000000
02000000 0 b0000000 b0000000 0 10000000
01000000 0 00000000 e3000000 0 01000000>;
clock-frequency = <3f940aa>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <e0008600 100>;
compatible = "fsl,mpc8349-pci";
device_type = "pci";
};
};

249
arch/powerpc/boot/dts/mpc834x_mds.dts
View File

@ -29,7 +29,6 @@
timebase-frequency = <0>; // from bootloader
bus-frequency = <0>; // from bootloader
clock-frequency = <0>; // from bootloader
32-bit;
};
};
@ -46,7 +45,6 @@
soc8349@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00000200>;
@ -78,11 +76,11 @@
spi@7000 {
device_type = "spi";
compatible = "mpc83xx_spi";
compatible = "fsl_spi";
reg = <7000 1000>;
interrupts = <10 8>;
interrupt-parent = < &ipic >;
mode = <0>;
mode = "cpu";
};
/* phy type (ULPI or SERIAL) are only types supportted for MPH */
@ -146,6 +144,7 @@
interrupts = <20 8 21 8 22 8>;
interrupt-parent = < &ipic >;
phy-handle = < &phy0 >;
linux,network-index = <0>;
};
ethernet@25000 {
@ -165,6 +164,7 @@
interrupts = <23 8 24 8 25 8>;
interrupt-parent = < &ipic >;
phy-handle = < &phy1 >;
linux,network-index = <1>;
};
serial@4500 {
@ -185,126 +185,6 @@
interrupt-parent = < &ipic >;
};
pci@8500 {
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x11 */
8800 0 0 1 &ipic 14 8
8800 0 0 2 &ipic 15 8
8800 0 0 3 &ipic 16 8
8800 0 0 4 &ipic 17 8
/* IDSEL 0x12 */
9000 0 0 1 &ipic 16 8
9000 0 0 2 &ipic 17 8
9000 0 0 3 &ipic 14 8
9000 0 0 4 &ipic 15 8
/* IDSEL 0x13 */
9800 0 0 1 &ipic 17 8
9800 0 0 2 &ipic 14 8
9800 0 0 3 &ipic 15 8
9800 0 0 4 &ipic 16 8
/* IDSEL 0x15 */
a800 0 0 1 &ipic 14 8
a800 0 0 2 &ipic 15 8
a800 0 0 3 &ipic 16 8
a800 0 0 4 &ipic 17 8
/* IDSEL 0x16 */
b000 0 0 1 &ipic 17 8
b000 0 0 2 &ipic 14 8
b000 0 0 3 &ipic 15 8
b000 0 0 4 &ipic 16 8
/* IDSEL 0x17 */
b800 0 0 1 &ipic 16 8
b800 0 0 2 &ipic 17 8
b800 0 0 3 &ipic 14 8
b800 0 0 4 &ipic 15 8
/* IDSEL 0x18 */
c000 0 0 1 &ipic 15 8
c000 0 0 2 &ipic 16 8
c000 0 0 3 &ipic 17 8
c000 0 0 4 &ipic 14 8>;
interrupt-parent = < &ipic >;
interrupts = <42 8>;
bus-range = <0 0>;
ranges = <02000000 0 90000000 90000000 0 10000000
42000000 0 80000000 80000000 0 10000000
01000000 0 00000000 e2000000 0 00100000>;
clock-frequency = <3f940aa>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <8500 100>;
compatible = "fsl,mpc8349-pci";
device_type = "pci";
};
pci@8600 {
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x11 */
8800 0 0 1 &ipic 14 8
8800 0 0 2 &ipic 15 8
8800 0 0 3 &ipic 16 8
8800 0 0 4 &ipic 17 8
/* IDSEL 0x12 */
9000 0 0 1 &ipic 16 8
9000 0 0 2 &ipic 17 8
9000 0 0 3 &ipic 14 8
9000 0 0 4 &ipic 15 8
/* IDSEL 0x13 */
9800 0 0 1 &ipic 17 8
9800 0 0 2 &ipic 14 8
9800 0 0 3 &ipic 15 8
9800 0 0 4 &ipic 16 8
/* IDSEL 0x15 */
a800 0 0 1 &ipic 14 8
a800 0 0 2 &ipic 15 8
a800 0 0 3 &ipic 16 8
a800 0 0 4 &ipic 17 8
/* IDSEL 0x16 */
b000 0 0 1 &ipic 17 8
b000 0 0 2 &ipic 14 8
b000 0 0 3 &ipic 15 8
b000 0 0 4 &ipic 16 8
/* IDSEL 0x17 */
b800 0 0 1 &ipic 16 8
b800 0 0 2 &ipic 17 8
b800 0 0 3 &ipic 14 8
b800 0 0 4 &ipic 15 8
/* IDSEL 0x18 */
c000 0 0 1 &ipic 15 8
c000 0 0 2 &ipic 16 8
c000 0 0 3 &ipic 17 8
c000 0 0 4 &ipic 14 8>;
interrupt-parent = < &ipic >;
interrupts = <42 8>;
bus-range = <0 0>;
ranges = <02000000 0 b0000000 b0000000 0 10000000
42000000 0 a0000000 a0000000 0 10000000
01000000 0 00000000 e2100000 0 00100000>;
clock-frequency = <3f940aa>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <8600 100>;
compatible = "fsl,mpc8349-pci";
device_type = "pci";
};
/* May need to remove if on a part without crypto engine */
crypto@30000 {
device_type = "crypto";
@ -332,8 +212,127 @@
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <700 100>;
built-in;
device_type = "ipic";
};
};
pci@e0008500 {
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x11 */
8800 0 0 1 &ipic 14 8
8800 0 0 2 &ipic 15 8
8800 0 0 3 &ipic 16 8
8800 0 0 4 &ipic 17 8
/* IDSEL 0x12 */
9000 0 0 1 &ipic 16 8
9000 0 0 2 &ipic 17 8
9000 0 0 3 &ipic 14 8
9000 0 0 4 &ipic 15 8
/* IDSEL 0x13 */
9800 0 0 1 &ipic 17 8
9800 0 0 2 &ipic 14 8
9800 0 0 3 &ipic 15 8
9800 0 0 4 &ipic 16 8
/* IDSEL 0x15 */
a800 0 0 1 &ipic 14 8
a800 0 0 2 &ipic 15 8
a800 0 0 3 &ipic 16 8
a800 0 0 4 &ipic 17 8
/* IDSEL 0x16 */
b000 0 0 1 &ipic 17 8
b000 0 0 2 &ipic 14 8
b000 0 0 3 &ipic 15 8
b000 0 0 4 &ipic 16 8
/* IDSEL 0x17 */
b800 0 0 1 &ipic 16 8
b800 0 0 2 &ipic 17 8
b800 0 0 3 &ipic 14 8
b800 0 0 4 &ipic 15 8
/* IDSEL 0x18 */
c000 0 0 1 &ipic 15 8
c000 0 0 2 &ipic 16 8
c000 0 0 3 &ipic 17 8
c000 0 0 4 &ipic 14 8>;
interrupt-parent = < &ipic >;
interrupts = <42 8>;
bus-range = <0 0>;
ranges = <02000000 0 90000000 90000000 0 10000000
42000000 0 80000000 80000000 0 10000000
01000000 0 00000000 e2000000 0 00100000>;
clock-frequency = <3f940aa>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <e0008500 100>;
compatible = "fsl,mpc8349-pci";
device_type = "pci";
};
pci@e0008600 {
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x11 */
8800 0 0 1 &ipic 14 8
8800 0 0 2 &ipic 15 8
8800 0 0 3 &ipic 16 8
8800 0 0 4 &ipic 17 8
/* IDSEL 0x12 */
9000 0 0 1 &ipic 16 8
9000 0 0 2 &ipic 17 8
9000 0 0 3 &ipic 14 8
9000 0 0 4 &ipic 15 8
/* IDSEL 0x13 */
9800 0 0 1 &ipic 17 8
9800 0 0 2 &ipic 14 8
9800 0 0 3 &ipic 15 8
9800 0 0 4 &ipic 16 8
/* IDSEL 0x15 */
a800 0 0 1 &ipic 14 8
a800 0 0 2 &ipic 15 8
a800 0 0 3 &ipic 16 8
a800 0 0 4 &ipic 17 8
/* IDSEL 0x16 */
b000 0 0 1 &ipic 17 8
b000 0 0 2 &ipic 14 8
b000 0 0 3 &ipic 15 8
b000 0 0 4 &ipic 16 8
/* IDSEL 0x17 */
b800 0 0 1 &ipic 16 8
b800 0 0 2 &ipic 17 8
b800 0 0 3 &ipic 14 8
b800 0 0 4 &ipic 15 8
/* IDSEL 0x18 */
c000 0 0 1 &ipic 15 8
c000 0 0 2 &ipic 16 8
c000 0 0 3 &ipic 17 8
c000 0 0 4 &ipic 14 8>;
interrupt-parent = < &ipic >;
interrupts = <42 8>;
bus-range = <0 0>;
ranges = <02000000 0 b0000000 b0000000 0 10000000
42000000 0 a0000000 a0000000 0 10000000
01000000 0 00000000 e2100000 0 00100000>;
clock-frequency = <3f940aa>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <e0008600 100>;
compatible = "fsl,mpc8349-pci";
device_type = "pci";
};
};

123
arch/powerpc/boot/dts/mpc836x_mds.dts
View File

@ -34,7 +34,6 @@
timebase-frequency = <3EF1480>;
bus-frequency = <FBC5200>;
clock-frequency = <1F78A400>;
32-bit;
};
};
@ -51,7 +50,6 @@
soc8360@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00000200>;
@ -113,72 +111,11 @@
descriptor-types-mask = <01010ebf>;
};
pci@8500 {
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x11 AD17 */
8800 0 0 1 &ipic 14 8
8800 0 0 2 &ipic 15 8
8800 0 0 3 &ipic 16 8
8800 0 0 4 &ipic 17 8
/* IDSEL 0x12 AD18 */
9000 0 0 1 &ipic 16 8
9000 0 0 2 &ipic 17 8
9000 0 0 3 &ipic 14 8
9000 0 0 4 &ipic 15 8
/* IDSEL 0x13 AD19 */
9800 0 0 1 &ipic 17 8
9800 0 0 2 &ipic 14 8
9800 0 0 3 &ipic 15 8
9800 0 0 4 &ipic 16 8
/* IDSEL 0x15 AD21*/
a800 0 0 1 &ipic 14 8
a800 0 0 2 &ipic 15 8
a800 0 0 3 &ipic 16 8
a800 0 0 4 &ipic 17 8
/* IDSEL 0x16 AD22*/
b000 0 0 1 &ipic 17 8
b000 0 0 2 &ipic 14 8
b000 0 0 3 &ipic 15 8
b000 0 0 4 &ipic 16 8
/* IDSEL 0x17 AD23*/
b800 0 0 1 &ipic 16 8
b800 0 0 2 &ipic 17 8
b800 0 0 3 &ipic 14 8
b800 0 0 4 &ipic 15 8
/* IDSEL 0x18 AD24*/
c000 0 0 1 &ipic 15 8
c000 0 0 2 &ipic 16 8
c000 0 0 3 &ipic 17 8
c000 0 0 4 &ipic 14 8>;
interrupt-parent = < &ipic >;
interrupts = <42 8>;
bus-range = <0 0>;
ranges = <02000000 0 a0000000 a0000000 0 10000000
42000000 0 80000000 80000000 0 10000000
01000000 0 00000000 e2000000 0 00100000>;
clock-frequency = <3f940aa>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <8500 100>;
compatible = "fsl,mpc8349-pci";
device_type = "pci";
};
ipic: pic@700 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <700 100>;
built-in;
device_type = "ipic";
};
@ -364,11 +301,69 @@
#address-cells = <0>;
#interrupt-cells = <1>;
reg = <80 80>;
built-in;
big-endian;
interrupts = <20 8 21 8>; //high:32 low:33
interrupt-parent = < &ipic >;
};
};
pci@e0008500 {
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x11 AD17 */
8800 0 0 1 &ipic 14 8
8800 0 0 2 &ipic 15 8
8800 0 0 3 &ipic 16 8
8800 0 0 4 &ipic 17 8
/* IDSEL 0x12 AD18 */
9000 0 0 1 &ipic 16 8
9000 0 0 2 &ipic 17 8
9000 0 0 3 &ipic 14 8
9000 0 0 4 &ipic 15 8
/* IDSEL 0x13 AD19 */
9800 0 0 1 &ipic 17 8
9800 0 0 2 &ipic 14 8
9800 0 0 3 &ipic 15 8
9800 0 0 4 &ipic 16 8
/* IDSEL 0x15 AD21*/
a800 0 0 1 &ipic 14 8
a800 0 0 2 &ipic 15 8
a800 0 0 3 &ipic 16 8
a800 0 0 4 &ipic 17 8
/* IDSEL 0x16 AD22*/
b000 0 0 1 &ipic 17 8
b000 0 0 2 &ipic 14 8
b000 0 0 3 &ipic 15 8
b000 0 0 4 &ipic 16 8
/* IDSEL 0x17 AD23*/
b800 0 0 1 &ipic 16 8
b800 0 0 2 &ipic 17 8
b800 0 0 3 &ipic 14 8
b800 0 0 4 &ipic 15 8
/* IDSEL 0x18 AD24*/
c000 0 0 1 &ipic 15 8
c000 0 0 2 &ipic 16 8
c000 0 0 3 &ipic 17 8
c000 0 0 4 &ipic 14 8>;
interrupt-parent = < &ipic >;
interrupts = <42 8>;
bus-range = <0 0>;
ranges = <02000000 0 a0000000 a0000000 0 10000000
42000000 0 80000000 80000000 0 10000000
01000000 0 00000000 e2000000 0 00100000>;
clock-frequency = <3f940aa>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <e0008500 100>;
compatible = "fsl,mpc8349-pci";
device_type = "pci";
};
};

181
arch/powerpc/boot/dts/mpc8540ads.dts
View File

@ -30,7 +30,6 @@
timebase-frequency = <0>; // 33 MHz, from uboot
bus-frequency = <0>; // 166 MHz
clock-frequency = <0>; // 825 MHz, from uboot
32-bit;
};
};
@ -42,7 +41,6 @@
soc8540@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00100000>; // CCSRBAR 1M
@ -173,105 +171,104 @@
interrupts = <2a 2>;
interrupt-parent = <&mpic>;
};
pci@8000 {
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x02 */
1000 0 0 1 &mpic 1 1
1000 0 0 2 &mpic 2 1
1000 0 0 3 &mpic 3 1
1000 0 0 4 &mpic 4 1
/* IDSEL 0x03 */
1800 0 0 1 &mpic 4 1
1800 0 0 2 &mpic 1 1
1800 0 0 3 &mpic 2 1
1800 0 0 4 &mpic 3 1
/* IDSEL 0x04 */
2000 0 0 1 &mpic 3 1
2000 0 0 2 &mpic 4 1
2000 0 0 3 &mpic 1 1
2000 0 0 4 &mpic 2 1
/* IDSEL 0x05 */
2800 0 0 1 &mpic 2 1
2800 0 0 2 &mpic 3 1
2800 0 0 3 &mpic 4 1
2800 0 0 4 &mpic 1 1
/* IDSEL 0x0c */
6000 0 0 1 &mpic 1 1
6000 0 0 2 &mpic 2 1
6000 0 0 3 &mpic 3 1
6000 0 0 4 &mpic 4 1
/* IDSEL 0x0d */
6800 0 0 1 &mpic 4 1
6800 0 0 2 &mpic 1 1
6800 0 0 3 &mpic 2 1
6800 0 0 4 &mpic 3 1
/* IDSEL 0x0e */
7000 0 0 1 &mpic 3 1
7000 0 0 2 &mpic 4 1
7000 0 0 3 &mpic 1 1
7000 0 0 4 &mpic 2 1
/* IDSEL 0x0f */
7800 0 0 1 &mpic 2 1
7800 0 0 2 &mpic 3 1
7800 0 0 3 &mpic 4 1
7800 0 0 4 &mpic 1 1
/* IDSEL 0x12 */
9000 0 0 1 &mpic 1 1
9000 0 0 2 &mpic 2 1
9000 0 0 3 &mpic 3 1
9000 0 0 4 &mpic 4 1
/* IDSEL 0x13 */
9800 0 0 1 &mpic 4 1
9800 0 0 2 &mpic 1 1
9800 0 0 3 &mpic 2 1
9800 0 0 4 &mpic 3 1
/* IDSEL 0x14 */
a000 0 0 1 &mpic 3 1
a000 0 0 2 &mpic 4 1
a000 0 0 3 &mpic 1 1
a000 0 0 4 &mpic 2 1
/* IDSEL 0x15 */
a800 0 0 1 &mpic 2 1
a800 0 0 2 &mpic 3 1
a800 0 0 3 &mpic 4 1
a800 0 0 4 &mpic 1 1>;
interrupt-parent = <&mpic>;
interrupts = <18 2>;
bus-range = <0 0>;
ranges = <02000000 0 80000000 80000000 0 20000000
01000000 0 00000000 e2000000 0 00100000>;
clock-frequency = <3f940aa>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <8000 1000>;
compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
device_type = "pci";
};
mpic: pic@40000 {
clock-frequency = <0>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <40000 40000>;
built-in;
compatible = "chrp,open-pic";
device_type = "open-pic";
big-endian;
};
};
pci@e0008000 {
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x02 */
1000 0 0 1 &mpic 1 1
1000 0 0 2 &mpic 2 1
1000 0 0 3 &mpic 3 1
1000 0 0 4 &mpic 4 1
/* IDSEL 0x03 */
1800 0 0 1 &mpic 4 1
1800 0 0 2 &mpic 1 1
1800 0 0 3 &mpic 2 1
1800 0 0 4 &mpic 3 1
/* IDSEL 0x04 */
2000 0 0 1 &mpic 3 1
2000 0 0 2 &mpic 4 1
2000 0 0 3 &mpic 1 1
2000 0 0 4 &mpic 2 1
/* IDSEL 0x05 */
2800 0 0 1 &mpic 2 1
2800 0 0 2 &mpic 3 1
2800 0 0 3 &mpic 4 1
2800 0 0 4 &mpic 1 1
/* IDSEL 0x0c */
6000 0 0 1 &mpic 1 1
6000 0 0 2 &mpic 2 1
6000 0 0 3 &mpic 3 1
6000 0 0 4 &mpic 4 1
/* IDSEL 0x0d */
6800 0 0 1 &mpic 4 1
6800 0 0 2 &mpic 1 1
6800 0 0 3 &mpic 2 1
6800 0 0 4 &mpic 3 1
/* IDSEL 0x0e */
7000 0 0 1 &mpic 3 1
7000 0 0 2 &mpic 4 1
7000 0 0 3 &mpic 1 1
7000 0 0 4 &mpic 2 1
/* IDSEL 0x0f */
7800 0 0 1 &mpic 2 1
7800 0 0 2 &mpic 3 1
7800 0 0 3 &mpic 4 1
7800 0 0 4 &mpic 1 1
/* IDSEL 0x12 */
9000 0 0 1 &mpic 1 1
9000 0 0 2 &mpic 2 1
9000 0 0 3 &mpic 3 1
9000 0 0 4 &mpic 4 1
/* IDSEL 0x13 */
9800 0 0 1 &mpic 4 1
9800 0 0 2 &mpic 1 1
9800 0 0 3 &mpic 2 1
9800 0 0 4 &mpic 3 1
/* IDSEL 0x14 */
a000 0 0 1 &mpic 3 1
a000 0 0 2 &mpic 4 1
a000 0 0 3 &mpic 1 1
a000 0 0 4 &mpic 2 1
/* IDSEL 0x15 */
a800 0 0 1 &mpic 2 1
a800 0 0 2 &mpic 3 1
a800 0 0 3 &mpic 4 1
a800 0 0 4 &mpic 1 1>;
interrupt-parent = <&mpic>;
interrupts = <18 2>;
bus-range = <0 0>;
ranges = <02000000 0 80000000 80000000 0 20000000
01000000 0 00000000 e2000000 0 00100000>;
clock-frequency = <3f940aa>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <e0008000 1000>;
compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
device_type = "pci";
};
};

232
arch/powerpc/boot/dts/mpc8541cds.dts
View File

@ -30,7 +30,6 @@
timebase-frequency = <0>; // 33 MHz, from uboot
bus-frequency = <0>; // 166 MHz
clock-frequency = <0>; // 825 MHz, from uboot
32-bit;
};
};
@ -42,10 +41,9 @@
soc8541@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00100000>; // CCSRBAR 1M
reg = <e0000000 00001000>; // CCSRBAR 1M
bus-frequency = <0>;
memory-controller@2000 {
@ -137,113 +135,145 @@
interrupt-parent = <&mpic>;
};
pci1: pci@8000 {
interrupt-map-mask = <1f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x10 */
08000 0 0 1 &mpic 0 1
08000 0 0 2 &mpic 1 1
08000 0 0 3 &mpic 2 1
08000 0 0 4 &mpic 3 1
/* IDSEL 0x11 */
08800 0 0 1 &mpic 0 1
08800 0 0 2 &mpic 1 1
08800 0 0 3 &mpic 2 1
08800 0 0 4 &mpic 3 1
/* IDSEL 0x12 (Slot 1) */
09000 0 0 1 &mpic 0 1
09000 0 0 2 &mpic 1 1
09000 0 0 3 &mpic 2 1
09000 0 0 4 &mpic 3 1
/* IDSEL 0x13 (Slot 2) */
09800 0 0 1 &mpic 1 1
09800 0 0 2 &mpic 2 1
09800 0 0 3 &mpic 3 1
09800 0 0 4 &mpic 0 1
/* IDSEL 0x14 (Slot 3) */
0a000 0 0 1 &mpic 2 1
0a000 0 0 2 &mpic 3 1
0a000 0 0 3 &mpic 0 1
0a000 0 0 4 &mpic 1 1
/* IDSEL 0x15 (Slot 4) */
0a800 0 0 1 &mpic 3 1
0a800 0 0 2 &mpic 0 1
0a800 0 0 3 &mpic 1 1
0a800 0 0 4 &mpic 2 1
/* Bus 1 (Tundra Bridge) */
/* IDSEL 0x12 (ISA bridge) */
19000 0 0 1 &mpic 0 1
19000 0 0 2 &mpic 1 1
19000 0 0 3 &mpic 2 1
19000 0 0 4 &mpic 3 1>;
interrupt-parent = <&mpic>;
interrupts = <18 2>;
bus-range = <0 0>;
ranges = <02000000 0 80000000 80000000 0 20000000
01000000 0 00000000 e2000000 0 00100000>;
clock-frequency = <3f940aa>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <8000 1000>;
compatible = "fsl,mpc8540-pci";
device_type = "pci";
i8259@19000 {
clock-frequency = <0>;
interrupt-controller;
device_type = "interrupt-controller";
reg = <19000 0 0 0 1>;
#address-cells = <0>;
#interrupt-cells = <2>;
built-in;
compatible = "chrp,iic";
big-endian;
interrupts = <1>;
interrupt-parent = <&pci1>;
};
};
pci@9000 {
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x15 */
a800 0 0 1 &mpic b 1
a800 0 0 2 &mpic b 1
a800 0 0 3 &mpic b 1
a800 0 0 4 &mpic b 1>;
interrupt-parent = <&mpic>;
interrupts = <19 2>;
bus-range = <0 0>;
ranges = <02000000 0 a0000000 a0000000 0 20000000
01000000 0 00000000 e3000000 0 00100000>;
clock-frequency = <3f940aa>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <9000 1000>;
compatible = "fsl,mpc8540-pci";
device_type = "pci";
};
mpic: pic@40000 {
clock-frequency = <0>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <40000 40000>;
built-in;
compatible = "chrp,open-pic";
device_type = "open-pic";
big-endian;
};
cpm@919c0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8541-cpm", "fsl,cpm2";
reg = <919c0 30>;
ranges;
muram@80000 {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 80000 10000>;
data@0 {
compatible = "fsl,cpm-muram-data";
reg = <0 2000 9000 1000>;
};
};
brg@919f0 {
compatible = "fsl,mpc8541-brg",
"fsl,cpm2-brg",
"fsl,cpm-brg";
reg = <919f0 10 915f0 10>;
};
cpmpic: pic@90c00 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
interrupts = <2e 2>;
interrupt-parent = <&mpic>;
reg = <90c00 80>;
compatible = "fsl,mpc8541-cpm-pic", "fsl,cpm2-pic";
};
};
};
pci1: pci@e0008000 {
interrupt-map-mask = <1f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x10 */
08000 0 0 1 &mpic 0 1
08000 0 0 2 &mpic 1 1
08000 0 0 3 &mpic 2 1
08000 0 0 4 &mpic 3 1
/* IDSEL 0x11 */
08800 0 0 1 &mpic 0 1
08800 0 0 2 &mpic 1 1
08800 0 0 3 &mpic 2 1
08800 0 0 4 &mpic 3 1
/* IDSEL 0x12 (Slot 1) */
09000 0 0 1 &mpic 0 1
09000 0 0 2 &mpic 1 1
09000 0 0 3 &mpic 2 1
09000 0 0 4 &mpic 3 1
/* IDSEL 0x13 (Slot 2) */
09800 0 0 1 &mpic 1 1
09800 0 0 2 &mpic 2 1
09800 0 0 3 &mpic 3 1
09800 0 0 4 &mpic 0 1
/* IDSEL 0x14 (Slot 3) */
0a000 0 0 1 &mpic 2 1
0a000 0 0 2 &mpic 3 1
0a000 0 0 3 &mpic 0 1
0a000 0 0 4 &mpic 1 1
/* IDSEL 0x15 (Slot 4) */
0a800 0 0 1 &mpic 3 1
0a800 0 0 2 &mpic 0 1
0a800 0 0 3 &mpic 1 1
0a800 0 0 4 &mpic 2 1
/* Bus 1 (Tundra Bridge) */
/* IDSEL 0x12 (ISA bridge) */
19000 0 0 1 &mpic 0 1
19000 0 0 2 &mpic 1 1
19000 0 0 3 &mpic 2 1
19000 0 0 4 &mpic 3 1>;
interrupt-parent = <&mpic>;
interrupts = <18 2>;
bus-range = <0 0>;
ranges = <02000000 0 80000000 80000000 0 20000000
01000000 0 00000000 e2000000 0 00100000>;
clock-frequency = <3f940aa>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <e0008000 1000>;
compatible = "fsl,mpc8540-pci";
device_type = "pci";
i8259@19000 {
interrupt-controller;
device_type = "interrupt-controller";
reg = <19000 0 0 0 1>;
#address-cells = <0>;
#interrupt-cells = <2>;
compatible = "chrp,iic";
interrupts = <1>;
interrupt-parent = <&pci1>;
};
};
pci@e0009000 {
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x15 */
a800 0 0 1 &mpic b 1
a800 0 0 2 &mpic b 1
a800 0 0 3 &mpic b 1
a800 0 0 4 &mpic b 1>;
interrupt-parent = <&mpic>;
interrupts = <19 2>;
bus-range = <0 0>;
ranges = <02000000 0 a0000000 a0000000 0 20000000
01000000 0 00000000 e3000000 0 00100000>;
clock-frequency = <3f940aa>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <e0009000 1000>;
compatible = "fsl,mpc8540-pci";
device_type = "pci";
};
};

419
arch/powerpc/boot/dts/mpc8544ds.dts
View File

@ -30,7 +30,6 @@
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
32-bit;
};
};
@ -42,19 +41,9 @@
soc8544@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
ranges = <00001000 e0001000 000ff000
80000000 80000000 20000000
a0000000 a0000000 10000000
b0000000 b0000000 00100000
c0000000 c0000000 20000000
b0100000 b0100000 00100000
e1000000 e1000000 00010000
e1010000 e1010000 00010000
e1020000 e1020000 00010000>;
ranges = <00000000 e0000000 00100000>;
reg = <e0000000 00001000>; // CCSRBAR 1M
bus-frequency = <0>; // Filled out by uboot.
@ -149,195 +138,6 @@
interrupt-parent = <&mpic>;
};
pci@8000 {
compatible = "fsl,mpc8540-pci";
device_type = "pci";
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x11 J17 Slot 1 */
8800 0 0 1 &mpic 2 1
8800 0 0 2 &mpic 3 1
8800 0 0 3 &mpic 4 1
8800 0 0 4 &mpic 1 1
/* IDSEL 0x12 J16 Slot 2 */
9000 0 0 1 &mpic 3 1
9000 0 0 2 &mpic 4 1
9000 0 0 3 &mpic 2 1
9000 0 0 4 &mpic 1 1>;
interrupt-parent = <&mpic>;
interrupts = <18 2>;
bus-range = <0 ff>;
ranges = <02000000 0 c0000000 c0000000 0 20000000
01000000 0 00000000 e1000000 0 00010000>;
clock-frequency = <3f940aa>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <8000 1000>;
};
pcie@9000 {
compatible = "fsl,mpc8548-pcie";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <9000 1000>;
bus-range = <0 ff>;
ranges = <02000000 0 80000000 80000000 0 20000000
01000000 0 00000000 e1010000 0 00010000>;
clock-frequency = <1fca055>;
interrupt-parent = <&mpic>;
interrupts = <1a 2>;
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x0 */
0000 0 0 1 &mpic 4 1
0000 0 0 2 &mpic 5 1
0000 0 0 3 &mpic 6 1
0000 0 0 4 &mpic 7 1
>;
};
pcie@a000 {
compatible = "fsl,mpc8548-pcie";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <a000 1000>;
bus-range = <0 ff>;
ranges = <02000000 0 a0000000 a0000000 0 10000000
01000000 0 00000000 e1020000 0 00010000>;
clock-frequency = <1fca055>;
interrupt-parent = <&mpic>;
interrupts = <19 2>;
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x0 */
0000 0 0 1 &mpic 0 1
0000 0 0 2 &mpic 1 1
0000 0 0 3 &mpic 2 1
0000 0 0 4 &mpic 3 1
>;
};
pcie@b000 {
compatible = "fsl,mpc8548-pcie";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <b000 1000>;
bus-range = <0 ff>;
ranges = <02000000 0 b0000000 b0000000 0 00100000
01000000 0 00000000 b0100000 0 00100000>;
clock-frequency = <1fca055>;
interrupt-parent = <&mpic>;
interrupts = <1b 2>;
interrupt-map-mask = <fb00 0 0 0>;
interrupt-map = <
// IDSEL 0x1c USB
e000 0 0 0 &i8259 c 2
e100 0 0 0 &i8259 9 2
e200 0 0 0 &i8259 a 2
e300 0 0 0 &i8259 b 2
// IDSEL 0x1d Audio
e800 0 0 0 &i8259 6 2
// IDSEL 0x1e Legacy
f000 0 0 0 &i8259 7 2
f100 0 0 0 &i8259 7 2
// IDSEL 0x1f IDE/SATA
f800 0 0 0 &i8259 e 2
f900 0 0 0 &i8259 5 2
>;
uli1575@0 {
reg = <0 0 0 0 0>;
#size-cells = <2>;
#address-cells = <3>;
ranges = <02000000 0 b0000000
02000000 0 b0000000
0 00100000
01000000 0 00000000
01000000 0 00000000
0 00100000>;
pci_bridge@0 {
reg = <0 0 0 0 0>;
#size-cells = <2>;
#address-cells = <3>;
ranges = <02000000 0 b0000000
02000000 0 b0000000
0 00100000
01000000 0 00000000
01000000 0 00000000
0 00100000>;
isa@1e {
device_type = "isa";
#interrupt-cells = <2>;
#size-cells = <1>;
#address-cells = <2>;
reg = <f000 0 0 0 0>;
ranges = <1 0
01000000 0 0
00001000>;
interrupt-parent = <&i8259>;
i8259: interrupt-controller@20 {
reg = <1 20 2
1 a0 2
1 4d0 2>;
clock-frequency = <0>;
interrupt-controller;
device_type = "interrupt-controller";
#address-cells = <0>;
#interrupt-cells = <2>;
built-in;
compatible = "chrp,iic";
interrupts = <9 2>;
interrupt-parent = <&mpic>;
};
i8042@60 {
#size-cells = <0>;
#address-cells = <1>;
reg = <1 60 1 1 64 1>;
interrupts = <1 3 c 3>;
interrupt-parent = <&i8259>;
keyboard@0 {
reg = <0>;
compatible = "pnpPNP,303";
};
mouse@1 {
reg = <1>;
compatible = "pnpPNP,f03";
};
};
rtc@70 {
compatible = "pnpPNP,b00";
reg = <1 70 2>;
};
gpio@400 {
reg = <1 400 80>;
};
};
};
};
};
global-utilities@e0000 { //global utilities block
compatible = "fsl,mpc8548-guts";
reg = <e0000 1000>;
@ -350,10 +150,225 @@
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <40000 40000>;
built-in;
compatible = "chrp,open-pic";
device_type = "open-pic";
big-endian;
};
};
pci@e0008000 {
compatible = "fsl,mpc8540-pci";
device_type = "pci";
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x11 J17 Slot 1 */
8800 0 0 1 &mpic 2 1
8800 0 0 2 &mpic 3 1
8800 0 0 3 &mpic 4 1
8800 0 0 4 &mpic 1 1
/* IDSEL 0x12 J16 Slot 2 */
9000 0 0 1 &mpic 3 1
9000 0 0 2 &mpic 4 1
9000 0 0 3 &mpic 2 1
9000 0 0 4 &mpic 1 1>;
interrupt-parent = <&mpic>;
interrupts = <18 2>;
bus-range = <0 ff>;
ranges = <02000000 0 c0000000 c0000000 0 20000000
01000000 0 00000000 e1000000 0 00010000>;
clock-frequency = <3f940aa>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <e0008000 1000>;
};
pcie@e0009000 {
compatible = "fsl,mpc8548-pcie";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <e0009000 1000>;
bus-range = <0 ff>;
ranges = <02000000 0 80000000 80000000 0 20000000
01000000 0 00000000 e1010000 0 00010000>;
clock-frequency = <1fca055>;
interrupt-parent = <&mpic>;
interrupts = <1a 2>;
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x0 */
0000 0 0 1 &mpic 4 1
0000 0 0 2 &mpic 5 1
0000 0 0 3 &mpic 6 1
0000 0 0 4 &mpic 7 1
>;
pcie@0 {
reg = <0 0 0 0 0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
ranges = <02000000 0 80000000
02000000 0 80000000
0 20000000
01000000 0 00000000
01000000 0 00000000
0 00010000>;
};
};
pcie@e000a000 {
compatible = "fsl,mpc8548-pcie";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <e000a000 1000>;
bus-range = <0 ff>;
ranges = <02000000 0 a0000000 a0000000 0 10000000
01000000 0 00000000 e1020000 0 00010000>;
clock-frequency = <1fca055>;
interrupt-parent = <&mpic>;
interrupts = <19 2>;
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x0 */
0000 0 0 1 &mpic 0 1
0000 0 0 2 &mpic 1 1
0000 0 0 3 &mpic 2 1
0000 0 0 4 &mpic 3 1
>;
pcie@0 {
reg = <0 0 0 0 0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
ranges = <02000000 0 a0000000
02000000 0 a0000000
0 10000000
01000000 0 00000000
01000000 0 00000000
0 00010000>;
};
};
pcie@e000b000 {
compatible = "fsl,mpc8548-pcie";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <e000b000 1000>;
bus-range = <0 ff>;
ranges = <02000000 0 b0000000 b0000000 0 00100000
01000000 0 00000000 b0100000 0 00100000>;
clock-frequency = <1fca055>;
interrupt-parent = <&mpic>;
interrupts = <1b 2>;
interrupt-map-mask = <fb00 0 0 0>;
interrupt-map = <
// IDSEL 0x1c USB
e000 0 0 0 &i8259 c 2
e100 0 0 0 &i8259 9 2
e200 0 0 0 &i8259 a 2
e300 0 0 0 &i8259 b 2
// IDSEL 0x1d Audio
e800 0 0 0 &i8259 6 2
// IDSEL 0x1e Legacy
f000 0 0 0 &i8259 7 2
f100 0 0 0 &i8259 7 2
// IDSEL 0x1f IDE/SATA
f800 0 0 0 &i8259 e 2
f900 0 0 0 &i8259 5 2
>;
pcie@0 {
reg = <0 0 0 0 0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
ranges = <02000000 0 b0000000
02000000 0 b0000000
0 00100000
01000000 0 00000000
01000000 0 00000000
0 00100000>;
uli1575@0 {
reg = <0 0 0 0 0>;
#size-cells = <2>;
#address-cells = <3>;
ranges = <02000000 0 b0000000
02000000 0 b0000000
0 00100000
01000000 0 00000000
01000000 0 00000000
0 00100000>;
isa@1e {
device_type = "isa";
#interrupt-cells = <2>;
#size-cells = <1>;
#address-cells = <2>;
reg = <f000 0 0 0 0>;
ranges = <1 0
01000000 0 0
00001000>;
interrupt-parent = <&i8259>;
i8259: interrupt-controller@20 {
reg = <1 20 2
1 a0 2
1 4d0 2>;
interrupt-controller;
device_type = "interrupt-controller";
#address-cells = <0>;
#interrupt-cells = <2>;
compatible = "chrp,iic";
interrupts = <9 2>;
interrupt-parent = <&mpic>;
};
i8042@60 {
#size-cells = <0>;
#address-cells = <1>;
reg = <1 60 1 1 64 1>;
interrupts = <1 3 c 3>;
interrupt-parent = <&i8259>;
keyboard@0 {
reg = <0>;
compatible = "pnpPNP,303";
};
mouse@1 {
reg = <1>;
compatible = "pnpPNP,f03";
};
};
rtc@70 {
compatible = "pnpPNP,b00";
reg = <1 70 2>;
};
gpio@400 {
reg = <1 400 80>;
};
};
};
};
};
};

420
arch/powerpc/boot/dts/mpc8548cds.dts
View File

@ -30,7 +30,6 @@
timebase-frequency = <0>; // 33 MHz, from uboot
bus-frequency = <0>; // 166 MHz
clock-frequency = <0>; // 825 MHz, from uboot
32-bit;
};
};
@ -42,15 +41,8 @@
soc8548@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
ranges = <00001000 e0001000 000ff000
80000000 80000000 10000000
e2000000 e2000000 00800000
90000000 90000000 10000000
e2800000 e2800000 00800000
a0000000 a0000000 20000000
e3000000 e3000000 01000000>;
ranges = <00000000 e0000000 00100000>;
reg = <e0000000 00001000>; // CCSRBAR
bus-frequency = <0>;
@ -189,215 +181,225 @@
fsl,has-rstcr;
};
pci@8000 {
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x4 (PCIX Slot 2) */
02000 0 0 1 &mpic 0 1
02000 0 0 2 &mpic 1 1
02000 0 0 3 &mpic 2 1
02000 0 0 4 &mpic 3 1
/* IDSEL 0x5 (PCIX Slot 3) */
02800 0 0 1 &mpic 1 1
02800 0 0 2 &mpic 2 1
02800 0 0 3 &mpic 3 1
02800 0 0 4 &mpic 0 1
/* IDSEL 0x6 (PCIX Slot 4) */
03000 0 0 1 &mpic 2 1
03000 0 0 2 &mpic 3 1
03000 0 0 3 &mpic 0 1
03000 0 0 4 &mpic 1 1
/* IDSEL 0x8 (PCIX Slot 5) */
04000 0 0 1 &mpic 0 1
04000 0 0 2 &mpic 1 1
04000 0 0 3 &mpic 2 1
04000 0 0 4 &mpic 3 1
/* IDSEL 0xC (Tsi310 bridge) */
06000 0 0 1 &mpic 0 1
06000 0 0 2 &mpic 1 1
06000 0 0 3 &mpic 2 1
06000 0 0 4 &mpic 3 1
/* IDSEL 0x14 (Slot 2) */
0a000 0 0 1 &mpic 0 1
0a000 0 0 2 &mpic 1 1
0a000 0 0 3 &mpic 2 1
0a000 0 0 4 &mpic 3 1
/* IDSEL 0x15 (Slot 3) */
0a800 0 0 1 &mpic 1 1
0a800 0 0 2 &mpic 2 1
0a800 0 0 3 &mpic 3 1
0a800 0 0 4 &mpic 0 1
/* IDSEL 0x16 (Slot 4) */
0b000 0 0 1 &mpic 2 1
0b000 0 0 2 &mpic 3 1
0b000 0 0 3 &mpic 0 1
0b000 0 0 4 &mpic 1 1
/* IDSEL 0x18 (Slot 5) */
0c000 0 0 1 &mpic 0 1
0c000 0 0 2 &mpic 1 1
0c000 0 0 3 &mpic 2 1
0c000 0 0 4 &mpic 3 1
/* IDSEL 0x1C (Tsi310 bridge PCI primary) */
0E000 0 0 1 &mpic 0 1
0E000 0 0 2 &mpic 1 1
0E000 0 0 3 &mpic 2 1
0E000 0 0 4 &mpic 3 1>;
interrupt-parent = <&mpic>;
interrupts = <18 2>;
bus-range = <0 0>;
ranges = <02000000 0 80000000 80000000 0 10000000
01000000 0 00000000 e2000000 0 00800000>;
clock-frequency = <3f940aa>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <8000 1000>;
compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
device_type = "pci";
pci_bridge@1c {
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x00 (PrPMC Site) */
0000 0 0 1 &mpic 0 1
0000 0 0 2 &mpic 1 1
0000 0 0 3 &mpic 2 1
0000 0 0 4 &mpic 3 1
/* IDSEL 0x04 (VIA chip) */
2000 0 0 1 &mpic 0 1
2000 0 0 2 &mpic 1 1
2000 0 0 3 &mpic 2 1
2000 0 0 4 &mpic 3 1
/* IDSEL 0x05 (8139) */
2800 0 0 1 &mpic 1 1
/* IDSEL 0x06 (Slot 6) */
3000 0 0 1 &mpic 2 1
3000 0 0 2 &mpic 3 1
3000 0 0 3 &mpic 0 1
3000 0 0 4 &mpic 1 1
/* IDESL 0x07 (Slot 7) */
3800 0 0 1 &mpic 3 1
3800 0 0 2 &mpic 0 1
3800 0 0 3 &mpic 1 1
3800 0 0 4 &mpic 2 1>;
reg = <e000 0 0 0 0>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
ranges = <02000000 0 80000000
02000000 0 80000000
0 20000000
01000000 0 00000000
01000000 0 00000000
0 00080000>;
clock-frequency = <1fca055>;
isa@4 {
device_type = "isa";
#interrupt-cells = <2>;
#size-cells = <1>;
#address-cells = <2>;
reg = <2000 0 0 0 0>;
ranges = <1 0 01000000 0 0 00001000>;
interrupt-parent = <&i8259>;
i8259: interrupt-controller@20 {
clock-frequency = <0>;
interrupt-controller;
device_type = "interrupt-controller";
reg = <1 20 2
1 a0 2
1 4d0 2>;
#address-cells = <0>;
#interrupt-cells = <2>;
built-in;
compatible = "chrp,iic";
interrupts = <0 1>;
interrupt-parent = <&mpic>;
};
rtc@70 {
compatible = "pnpPNP,b00";
reg = <1 70 2>;
};
};
};
};
pci@9000 {
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x15 */
a800 0 0 1 &mpic b 1
a800 0 0 2 &mpic 1 1
a800 0 0 3 &mpic 2 1
a800 0 0 4 &mpic 3 1>;
interrupt-parent = <&mpic>;
interrupts = <19 2>;
bus-range = <0 0>;
ranges = <02000000 0 90000000 90000000 0 10000000
01000000 0 00000000 e2800000 0 00800000>;
clock-frequency = <3f940aa>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <9000 1000>;
compatible = "fsl,mpc8540-pci";
device_type = "pci";
};
/* PCI Express */
pcie@a000 {
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x0 (PEX) */
00000 0 0 1 &mpic 0 1
00000 0 0 2 &mpic 1 1
00000 0 0 3 &mpic 2 1
00000 0 0 4 &mpic 3 1>;
interrupt-parent = <&mpic>;
interrupts = <1a 2>;
bus-range = <0 ff>;
ranges = <02000000 0 a0000000 a0000000 0 20000000
01000000 0 00000000 e3000000 0 08000000>;
clock-frequency = <1fca055>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <a000 1000>;
compatible = "fsl,mpc8548-pcie";
device_type = "pci";
};
mpic: pic@40000 {
clock-frequency = <0>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <40000 40000>;
built-in;
compatible = "chrp,open-pic";
device_type = "open-pic";
big-endian;
};
};
pci@e0008000 {
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x4 (PCIX Slot 2) */
02000 0 0 1 &mpic 0 1
02000 0 0 2 &mpic 1 1
02000 0 0 3 &mpic 2 1
02000 0 0 4 &mpic 3 1
/* IDSEL 0x5 (PCIX Slot 3) */
02800 0 0 1 &mpic 1 1
02800 0 0 2 &mpic 2 1
02800 0 0 3 &mpic 3 1
02800 0 0 4 &mpic 0 1
/* IDSEL 0x6 (PCIX Slot 4) */
03000 0 0 1 &mpic 2 1
03000 0 0 2 &mpic 3 1
03000 0 0 3 &mpic 0 1
03000 0 0 4 &mpic 1 1
/* IDSEL 0x8 (PCIX Slot 5) */
04000 0 0 1 &mpic 0 1
04000 0 0 2 &mpic 1 1
04000 0 0 3 &mpic 2 1
04000 0 0 4 &mpic 3 1
/* IDSEL 0xC (Tsi310 bridge) */
06000 0 0 1 &mpic 0 1
06000 0 0 2 &mpic 1 1
06000 0 0 3 &mpic 2 1
06000 0 0 4 &mpic 3 1
/* IDSEL 0x14 (Slot 2) */
0a000 0 0 1 &mpic 0 1
0a000 0 0 2 &mpic 1 1
0a000 0 0 3 &mpic 2 1
0a000 0 0 4 &mpic 3 1
/* IDSEL 0x15 (Slot 3) */
0a800 0 0 1 &mpic 1 1
0a800 0 0 2 &mpic 2 1
0a800 0 0 3 &mpic 3 1
0a800 0 0 4 &mpic 0 1
/* IDSEL 0x16 (Slot 4) */
0b000 0 0 1 &mpic 2 1
0b000 0 0 2 &mpic 3 1
0b000 0 0 3 &mpic 0 1
0b000 0 0 4 &mpic 1 1
/* IDSEL 0x18 (Slot 5) */
0c000 0 0 1 &mpic 0 1
0c000 0 0 2 &mpic 1 1
0c000 0 0 3 &mpic 2 1
0c000 0 0 4 &mpic 3 1
/* IDSEL 0x1C (Tsi310 bridge PCI primary) */
0E000 0 0 1 &mpic 0 1
0E000 0 0 2 &mpic 1 1
0E000 0 0 3 &mpic 2 1
0E000 0 0 4 &mpic 3 1>;
interrupt-parent = <&mpic>;
interrupts = <18 2>;
bus-range = <0 0>;
ranges = <02000000 0 80000000 80000000 0 10000000
01000000 0 00000000 e2000000 0 00800000>;
clock-frequency = <3f940aa>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <e0008000 1000>;
compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
device_type = "pci";
pci_bridge@1c {
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x00 (PrPMC Site) */
0000 0 0 1 &mpic 0 1
0000 0 0 2 &mpic 1 1
0000 0 0 3 &mpic 2 1
0000 0 0 4 &mpic 3 1
/* IDSEL 0x04 (VIA chip) */
2000 0 0 1 &mpic 0 1
2000 0 0 2 &mpic 1 1
2000 0 0 3 &mpic 2 1
2000 0 0 4 &mpic 3 1
/* IDSEL 0x05 (8139) */
2800 0 0 1 &mpic 1 1
/* IDSEL 0x06 (Slot 6) */
3000 0 0 1 &mpic 2 1
3000 0 0 2 &mpic 3 1
3000 0 0 3 &mpic 0 1
3000 0 0 4 &mpic 1 1
/* IDESL 0x07 (Slot 7) */
3800 0 0 1 &mpic 3 1
3800 0 0 2 &mpic 0 1
3800 0 0 3 &mpic 1 1
3800 0 0 4 &mpic 2 1>;
reg = <e000 0 0 0 0>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
ranges = <02000000 0 80000000
02000000 0 80000000
0 20000000
01000000 0 00000000
01000000 0 00000000
0 00080000>;
clock-frequency = <1fca055>;
isa@4 {
device_type = "isa";
#interrupt-cells = <2>;
#size-cells = <1>;
#address-cells = <2>;
reg = <2000 0 0 0 0>;
ranges = <1 0 01000000 0 0 00001000>;
interrupt-parent = <&i8259>;
i8259: interrupt-controller@20 {
interrupt-controller;
device_type = "interrupt-controller";
reg = <1 20 2
1 a0 2
1 4d0 2>;
#address-cells = <0>;
#interrupt-cells = <2>;
compatible = "chrp,iic";
interrupts = <0 1>;
interrupt-parent = <&mpic>;
};
rtc@70 {
compatible = "pnpPNP,b00";
reg = <1 70 2>;
};
};
};
};
pci@e0009000 {
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x15 */
a800 0 0 1 &mpic b 1
a800 0 0 2 &mpic 1 1
a800 0 0 3 &mpic 2 1
a800 0 0 4 &mpic 3 1>;
interrupt-parent = <&mpic>;
interrupts = <19 2>;
bus-range = <0 0>;
ranges = <02000000 0 90000000 90000000 0 10000000
01000000 0 00000000 e2800000 0 00800000>;
clock-frequency = <3f940aa>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <e0009000 1000>;
compatible = "fsl,mpc8540-pci";
device_type = "pci";
};
pcie@e000a000 {
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x0 (PEX) */
00000 0 0 1 &mpic 0 1
00000 0 0 2 &mpic 1 1
00000 0 0 3 &mpic 2 1
00000 0 0 4 &mpic 3 1>;
interrupt-parent = <&mpic>;
interrupts = <1a 2>;
bus-range = <0 ff>;
ranges = <02000000 0 a0000000 a0000000 0 20000000
01000000 0 00000000 e3000000 0 08000000>;
clock-frequency = <1fca055>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <e000a000 1000>;
compatible = "fsl,mpc8548-pcie";
device_type = "pci";
pcie@0 {
reg = <0 0 0 0 0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
ranges = <02000000 0 a0000000
02000000 0 a0000000
0 20000000
01000000 0 00000000
01000000 0 00000000
0 08000000>;
};
};
};

232
arch/powerpc/boot/dts/mpc8555cds.dts
View File

@ -30,7 +30,6 @@
timebase-frequency = <0>; // 33 MHz, from uboot
bus-frequency = <0>; // 166 MHz
clock-frequency = <0>; // 825 MHz, from uboot
32-bit;
};
};
@ -42,10 +41,9 @@
soc8555@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00100000>; // CCSRBAR 1M
reg = <e0000000 00001000>; // CCSRBAR 1M
bus-frequency = <0>;
memory-controller@2000 {
@ -137,113 +135,145 @@
interrupt-parent = <&mpic>;
};
pci1: pci@8000 {
interrupt-map-mask = <1f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x10 */
08000 0 0 1 &mpic 0 1
08000 0 0 2 &mpic 1 1
08000 0 0 3 &mpic 2 1
08000 0 0 4 &mpic 3 1
/* IDSEL 0x11 */
08800 0 0 1 &mpic 0 1
08800 0 0 2 &mpic 1 1
08800 0 0 3 &mpic 2 1
08800 0 0 4 &mpic 3 1
/* IDSEL 0x12 (Slot 1) */
09000 0 0 1 &mpic 0 1
09000 0 0 2 &mpic 1 1
09000 0 0 3 &mpic 2 1
09000 0 0 4 &mpic 3 1
/* IDSEL 0x13 (Slot 2) */
09800 0 0 1 &mpic 1 1
09800 0 0 2 &mpic 2 1
09800 0 0 3 &mpic 3 1
09800 0 0 4 &mpic 0 1
/* IDSEL 0x14 (Slot 3) */
0a000 0 0 1 &mpic 2 1
0a000 0 0 2 &mpic 3 1
0a000 0 0 3 &mpic 0 1
0a000 0 0 4 &mpic 1 1
/* IDSEL 0x15 (Slot 4) */
0a800 0 0 1 &mpic 3 1
0a800 0 0 2 &mpic 0 1
0a800 0 0 3 &mpic 1 1
0a800 0 0 4 &mpic 2 1
/* Bus 1 (Tundra Bridge) */
/* IDSEL 0x12 (ISA bridge) */
19000 0 0 1 &mpic 0 1
19000 0 0 2 &mpic 1 1
19000 0 0 3 &mpic 2 1
19000 0 0 4 &mpic 3 1>;
interrupt-parent = <&mpic>;
interrupts = <18 2>;
bus-range = <0 0>;
ranges = <02000000 0 80000000 80000000 0 20000000
01000000 0 00000000 e2000000 0 00100000>;
clock-frequency = <3f940aa>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <8000 1000>;
compatible = "fsl,mpc8540-pci";
device_type = "pci";
i8259@19000 {
clock-frequency = <0>;
interrupt-controller;
device_type = "interrupt-controller";
reg = <19000 0 0 0 1>;
#address-cells = <0>;
#interrupt-cells = <2>;
built-in;
compatible = "chrp,iic";
big-endian;
interrupts = <1>;
interrupt-parent = <&pci1>;
};
};
pci@9000 {
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x15 */
a800 0 0 1 &mpic b 1
a800 0 0 2 &mpic b 1
a800 0 0 3 &mpic b 1
a800 0 0 4 &mpic b 1>;
interrupt-parent = <&mpic>;
interrupts = <19 2>;
bus-range = <0 0>;
ranges = <02000000 0 a0000000 a0000000 0 20000000
01000000 0 00000000 e3000000 0 00100000>;
clock-frequency = <3f940aa>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <9000 1000>;
compatible = "fsl,mpc8540-pci";
device_type = "pci";
};
mpic: pic@40000 {
clock-frequency = <0>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <40000 40000>;
built-in;
compatible = "chrp,open-pic";
device_type = "open-pic";
big-endian;
};
cpm@919c0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8555-cpm", "fsl,cpm2";
reg = <919c0 30>;
ranges;
muram@80000 {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 80000 10000>;
data@0 {
compatible = "fsl,cpm-muram-data";
reg = <0 2000 9000 1000>;
};
};
brg@919f0 {
compatible = "fsl,mpc8555-brg",
"fsl,cpm2-brg",
"fsl,cpm-brg";
reg = <919f0 10 915f0 10>;
};
cpmpic: pic@90c00 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
interrupts = <2e 2>;
interrupt-parent = <&mpic>;
reg = <90c00 80>;
compatible = "fsl,mpc8555-cpm-pic", "fsl,cpm2-pic";
};
};
};
pci1: pci@e0008000 {
interrupt-map-mask = <1f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x10 */
08000 0 0 1 &mpic 0 1
08000 0 0 2 &mpic 1 1
08000 0 0 3 &mpic 2 1
08000 0 0 4 &mpic 3 1
/* IDSEL 0x11 */
08800 0 0 1 &mpic 0 1
08800 0 0 2 &mpic 1 1
08800 0 0 3 &mpic 2 1
08800 0 0 4 &mpic 3 1
/* IDSEL 0x12 (Slot 1) */
09000 0 0 1 &mpic 0 1
09000 0 0 2 &mpic 1 1
09000 0 0 3 &mpic 2 1
09000 0 0 4 &mpic 3 1
/* IDSEL 0x13 (Slot 2) */
09800 0 0 1 &mpic 1 1
09800 0 0 2 &mpic 2 1
09800 0 0 3 &mpic 3 1
09800 0 0 4 &mpic 0 1
/* IDSEL 0x14 (Slot 3) */
0a000 0 0 1 &mpic 2 1
0a000 0 0 2 &mpic 3 1
0a000 0 0 3 &mpic 0 1
0a000 0 0 4 &mpic 1 1
/* IDSEL 0x15 (Slot 4) */
0a800 0 0 1 &mpic 3 1
0a800 0 0 2 &mpic 0 1
0a800 0 0 3 &mpic 1 1
0a800 0 0 4 &mpic 2 1
/* Bus 1 (Tundra Bridge) */
/* IDSEL 0x12 (ISA bridge) */
19000 0 0 1 &mpic 0 1
19000 0 0 2 &mpic 1 1
19000 0 0 3 &mpic 2 1
19000 0 0 4 &mpic 3 1>;
interrupt-parent = <&mpic>;
interrupts = <18 2>;
bus-range = <0 0>;
ranges = <02000000 0 80000000 80000000 0 20000000
01000000 0 00000000 e2000000 0 00100000>;
clock-frequency = <3f940aa>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <e0008000 1000>;
compatible = "fsl,mpc8540-pci";
device_type = "pci";
i8259@19000 {
interrupt-controller;
device_type = "interrupt-controller";
reg = <19000 0 0 0 1>;
#address-cells = <0>;
#interrupt-cells = <2>;
compatible = "chrp,iic";
interrupts = <1>;
interrupt-parent = <&pci1>;
};
};
pci@e0009000 {
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x15 */
a800 0 0 1 &mpic b 1
a800 0 0 2 &mpic b 1
a800 0 0 3 &mpic b 1
a800 0 0 4 &mpic b 1>;
interrupt-parent = <&mpic>;
interrupts = <19 2>;
bus-range = <0 0>;
ranges = <02000000 0 a0000000 a0000000 0 20000000
01000000 0 00000000 e3000000 0 00100000>;
clock-frequency = <3f940aa>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <e0009000 1000>;
compatible = "fsl,mpc8540-pci";
device_type = "pci";
};
};

267
arch/powerpc/boot/dts/mpc8560ads.dts
View File

@ -30,7 +30,6 @@
timebase-frequency = <04ead9a0>;
bus-frequency = <13ab6680>;
clock-frequency = <312c8040>;
32-bit;
};
};
@ -42,7 +41,6 @@
soc8560@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00000200>;
@ -132,115 +130,39 @@
phy-handle = <&phy1>;
};
pci@8000 {
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
device_type = "pci";
reg = <8000 1000>;
clock-frequency = <3f940aa>;
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x2 */
1000 0 0 1 &mpic 1 1
1000 0 0 2 &mpic 2 1
1000 0 0 3 &mpic 3 1
1000 0 0 4 &mpic 4 1
/* IDSEL 0x3 */
1800 0 0 1 &mpic 4 1
1800 0 0 2 &mpic 1 1
1800 0 0 3 &mpic 2 1
1800 0 0 4 &mpic 3 1
/* IDSEL 0x4 */
2000 0 0 1 &mpic 3 1
2000 0 0 2 &mpic 4 1
2000 0 0 3 &mpic 1 1
2000 0 0 4 &mpic 2 1
/* IDSEL 0x5 */
2800 0 0 1 &mpic 2 1
2800 0 0 2 &mpic 3 1
2800 0 0 3 &mpic 4 1
2800 0 0 4 &mpic 1 1
/* IDSEL 12 */
6000 0 0 1 &mpic 1 1
6000 0 0 2 &mpic 2 1
6000 0 0 3 &mpic 3 1
6000 0 0 4 &mpic 4 1
/* IDSEL 13 */
6800 0 0 1 &mpic 4 1
6800 0 0 2 &mpic 1 1
6800 0 0 3 &mpic 2 1
6800 0 0 4 &mpic 3 1
/* IDSEL 14*/
7000 0 0 1 &mpic 3 1
7000 0 0 2 &mpic 4 1
7000 0 0 3 &mpic 1 1
7000 0 0 4 &mpic 2 1
/* IDSEL 15 */
7800 0 0 1 &mpic 2 1
7800 0 0 2 &mpic 3 1
7800 0 0 3 &mpic 4 1
7800 0 0 4 &mpic 1 1
/* IDSEL 18 */
9000 0 0 1 &mpic 1 1
9000 0 0 2 &mpic 2 1
9000 0 0 3 &mpic 3 1
9000 0 0 4 &mpic 4 1
/* IDSEL 19 */
9800 0 0 1 &mpic 4 1
9800 0 0 2 &mpic 1 1
9800 0 0 3 &mpic 2 1
9800 0 0 4 &mpic 3 1
/* IDSEL 20 */
a000 0 0 1 &mpic 3 1
a000 0 0 2 &mpic 4 1
a000 0 0 3 &mpic 1 1
a000 0 0 4 &mpic 2 1
/* IDSEL 21 */
a800 0 0 1 &mpic 2 1
a800 0 0 2 &mpic 3 1
a800 0 0 3 &mpic 4 1
a800 0 0 4 &mpic 1 1>;
interrupt-parent = <&mpic>;
interrupts = <18 2>;
bus-range = <0 0>;
ranges = <02000000 0 80000000 80000000 0 20000000
01000000 0 00000000 e2000000 0 01000000>;
};
mpic: pic@40000 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <40000 40000>;
built-in;
device_type = "open-pic";
};
cpm@e0000000 {
cpm@919c0 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "cpm";
model = "CPM2";
ranges = <0 0 c0000>;
reg = <80000 40000>;
command-proc = <919c0>;
brg-frequency = <9d5b340>;
compatible = "fsl,mpc8560-cpm", "fsl,cpm2";
reg = <919c0 30>;
ranges;
muram@80000 {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 80000 10000>;
data@0 {
compatible = "fsl,cpm-muram-data";
reg = <0 4000 9000 2000>;
};
};
brg@919f0 {
compatible = "fsl,mpc8560-brg",
"fsl,cpm2-brg",
"fsl,cpm-brg";
reg = <919f0 10 915f0 10>;
clock-frequency = <d#165000000>;
};
cpmpic: pic@90c00 {
interrupt-controller;
@ -249,44 +171,38 @@
interrupts = <2e 2>;
interrupt-parent = <&mpic>;
reg = <90c00 80>;
built-in;
device_type = "cpm-pic";
compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic";
};
scc@91a00 {
serial@91a00 {
device_type = "serial";
compatible = "cpm_uart";
model = "SCC";
device-id = <1>;
compatible = "fsl,mpc8560-scc-uart",
"fsl,cpm2-scc-uart";
reg = <91a00 20 88000 100>;
clock-setup = <00ffffff 0>;
rx-clock = <1>;
tx-clock = <1>;
fsl,cpm-brg = <1>;
fsl,cpm-command = <00800000>;
current-speed = <1c200>;
interrupts = <28 8>;
interrupt-parent = <&cpmpic>;
};
scc@91a20 {
serial@91a20 {
device_type = "serial";
compatible = "cpm_uart";
model = "SCC";
device-id = <2>;
compatible = "fsl,mpc8560-scc-uart",
"fsl,cpm2-scc-uart";
reg = <91a20 20 88100 100>;
clock-setup = <ff00ffff 90000>;
rx-clock = <2>;
tx-clock = <2>;
fsl,cpm-brg = <2>;
fsl,cpm-command = <04a00000>;
current-speed = <1c200>;
interrupts = <29 8>;
interrupt-parent = <&cpmpic>;
};
fcc@91320 {
ethernet@91320 {
device_type = "network";
compatible = "fs_enet";
model = "FCC";
device-id = <2>;
reg = <91320 20 88500 100 913a0 30>;
compatible = "fsl,mpc8560-fcc-enet",
"fsl,cpm2-fcc-enet";
reg = <91320 20 88500 100 913b0 1>;
/*
* mac-address is deprecated and will be removed
* in 2.6.25. Only recent versions of
@ -294,20 +210,17 @@
*/
mac-address = [ 00 00 00 00 00 00 ];
local-mac-address = [ 00 00 00 00 00 00 ];
clock-setup = <ff00ffff 250000>;
rx-clock = <15>;
tx-clock = <16>;
fsl,cpm-command = <16200300>;
interrupts = <21 8>;
interrupt-parent = <&cpmpic>;
phy-handle = <&phy2>;
};
fcc@91340 {
ethernet@91340 {
device_type = "network";
compatible = "fs_enet";
model = "FCC";
device-id = <3>;
reg = <91340 20 88600 100 913d0 30>;
compatible = "fsl,mpc8560-fcc-enet",
"fsl,cpm2-fcc-enet";
reg = <91340 20 88600 100 913d0 1>;
/*
* mac-address is deprecated and will be removed
* in 2.6.25. Only recent versions of
@ -315,13 +228,101 @@
*/
mac-address = [ 00 00 00 00 00 00 ];
local-mac-address = [ 00 00 00 00 00 00 ];
clock-setup = <ffff00ff 3700>;
rx-clock = <17>;
tx-clock = <18>;
fsl,cpm-command = <1a400300>;
interrupts = <22 8>;
interrupt-parent = <&cpmpic>;
phy-handle = <&phy3>;
};
};
};
pci@e0008000 {
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
device_type = "pci";
reg = <e0008000 1000>;
clock-frequency = <3f940aa>;
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x2 */
1000 0 0 1 &mpic 1 1
1000 0 0 2 &mpic 2 1
1000 0 0 3 &mpic 3 1
1000 0 0 4 &mpic 4 1
/* IDSEL 0x3 */
1800 0 0 1 &mpic 4 1
1800 0 0 2 &mpic 1 1
1800 0 0 3 &mpic 2 1
1800 0 0 4 &mpic 3 1
/* IDSEL 0x4 */
2000 0 0 1 &mpic 3 1
2000 0 0 2 &mpic 4 1
2000 0 0 3 &mpic 1 1
2000 0 0 4 &mpic 2 1
/* IDSEL 0x5 */
2800 0 0 1 &mpic 2 1
2800 0 0 2 &mpic 3 1
2800 0 0 3 &mpic 4 1
2800 0 0 4 &mpic 1 1
/* IDSEL 12 */
6000 0 0 1 &mpic 1 1
6000 0 0 2 &mpic 2 1
6000 0 0 3 &mpic 3 1
6000 0 0 4 &mpic 4 1
/* IDSEL 13 */
6800 0 0 1 &mpic 4 1
6800 0 0 2 &mpic 1 1
6800 0 0 3 &mpic 2 1
6800 0 0 4 &mpic 3 1
/* IDSEL 14*/
7000 0 0 1 &mpic 3 1
7000 0 0 2 &mpic 4 1
7000 0 0 3 &mpic 1 1
7000 0 0 4 &mpic 2 1
/* IDSEL 15 */
7800 0 0 1 &mpic 2 1
7800 0 0 2 &mpic 3 1
7800 0 0 3 &mpic 4 1
7800 0 0 4 &mpic 1 1
/* IDSEL 18 */
9000 0 0 1 &mpic 1 1
9000 0 0 2 &mpic 2 1
9000 0 0 3 &mpic 3 1
9000 0 0 4 &mpic 4 1
/* IDSEL 19 */
9800 0 0 1 &mpic 4 1
9800 0 0 2 &mpic 1 1
9800 0 0 3 &mpic 2 1
9800 0 0 4 &mpic 3 1
/* IDSEL 20 */
a000 0 0 1 &mpic 3 1
a000 0 0 2 &mpic 4 1
a000 0 0 3 &mpic 1 1
a000 0 0 4 &mpic 2 1
/* IDSEL 21 */
a800 0 0 1 &mpic 2 1
a800 0 0 2 &mpic 3 1
a800 0 0 3 &mpic 4 1
a800 0 0 4 &mpic 1 1>;
interrupt-parent = <&mpic>;
interrupts = <18 2>;
bus-range = <0 0>;
ranges = <02000000 0 80000000 80000000 0 20000000
01000000 0 00000000 e2000000 0 01000000>;
};
};

160
arch/powerpc/boot/dts/mpc8568mds.dts
View File

@ -34,7 +34,6 @@
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
32-bit;
};
};
@ -51,10 +50,9 @@
soc8568@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00100000>;
reg = <e0000000 00001000>;
bus-frequency = <0>;
memory-controller@2000 {
@ -74,15 +72,24 @@
};
i2c@3000 {
#address-cells = <1>;
#size-cells = <0>;
device_type = "i2c";
compatible = "fsl-i2c";
reg = <3000 100>;
interrupts = <2b 2>;
interrupt-parent = <&mpic>;
dfsrr;
rtc@68 {
compatible = "dallas,ds1374";
reg = <68>;
};
};
i2c@3100 {
#address-cells = <1>;
#size-cells = <0>;
device_type = "i2c";
compatible = "fsl-i2c";
reg = <3100 100>;
@ -97,10 +104,10 @@
device_type = "mdio";
compatible = "gianfar";
reg = <24520 20>;
phy0: ethernet-phy@0 {
phy0: ethernet-phy@7 {
interrupt-parent = <&mpic>;
interrupts = <1 1>;
reg = <0>;
reg = <7>;
device_type = "ethernet-phy";
};
phy1: ethernet-phy@1 {
@ -176,60 +183,6 @@
fsl,has-rstcr;
};
pci@8000 {
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x12 AD18 */
9000 0 0 1 &mpic 5 1
9000 0 0 2 &mpic 6 1
9000 0 0 3 &mpic 7 1
9000 0 0 4 &mpic 4 1
/* IDSEL 0x13 AD19 */
9800 0 0 1 &mpic 6 1
9800 0 0 2 &mpic 7 1
9800 0 0 3 &mpic 4 1
9800 0 0 4 &mpic 5 1>;
interrupt-parent = <&mpic>;
interrupts = <18 2>;
bus-range = <0 ff>;
ranges = <02000000 0 80000000 80000000 0 20000000
01000000 0 00000000 e2000000 0 00800000>;
clock-frequency = <3f940aa>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <8000 1000>;
compatible = "fsl,mpc8540-pci";
device_type = "pci";
};
/* PCI Express */
pcie@a000 {
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x0 (PEX) */
00000 0 0 1 &mpic 0 1
00000 0 0 2 &mpic 1 1
00000 0 0 3 &mpic 2 1
00000 0 0 4 &mpic 3 1>;
interrupt-parent = <&mpic>;
interrupts = <1a 2>;
bus-range = <0 ff>;
ranges = <02000000 0 a0000000 a0000000 0 20000000
01000000 0 00000000 e3000000 0 08000000>;
clock-frequency = <1fca055>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <a000 1000>;
compatible = "fsl,mpc8548-pcie";
device_type = "pci";
};
serial@4600 {
device_type = "serial";
compatible = "ns16550";
@ -258,11 +211,11 @@
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <40000 40000>;
built-in;
compatible = "chrp,open-pic";
device_type = "open-pic";
big-endian;
};
par_io@e0100 {
reg = <e0100 100>;
device_type = "par_io";
@ -289,12 +242,13 @@
4 1a 2 0 2 0 /* RxD7 */
4 0b 1 0 2 0 /* TX_EN */
4 18 1 0 2 0 /* TX_ER */
4 0f 2 0 2 0 /* RX_DV */
4 10 2 0 2 0 /* RX_DV */
4 1e 2 0 2 0 /* RX_ER */
4 11 2 0 2 0 /* RX_CLK */
4 13 1 0 2 0 /* GTX_CLK */
1 1f 2 0 3 0>; /* GTX125 */
};
pio2: ucc_pin@02 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
@ -380,10 +334,10 @@
mac-address = [ 00 00 00 00 00 00 ];
local-mac-address = [ 00 00 00 00 00 00 ];
rx-clock = <0>;
tx-clock = <19>;
phy-handle = <&qe_phy0>;
phy-connection-type = "gmii";
tx-clock = <20>;
pio-handle = <&pio1>;
phy-handle = <&phy0>;
phy-connection-type = "rgmii-id";
};
ucc@3000 {
@ -402,10 +356,10 @@
mac-address = [ 00 00 00 00 00 00 ];
local-mac-address = [ 00 00 00 00 00 00 ];
rx-clock = <0>;
tx-clock = <14>;
phy-handle = <&qe_phy1>;
phy-connection-type = "gmii";
tx-clock = <20>;
pio-handle = <&pio2>;
phy-handle = <&phy1>;
phy-connection-type = "rgmii-id";
};
mdio@2120 {
@ -417,10 +371,10 @@
/* These are the same PHYs as on
* gianfar's MDIO bus */
qe_phy0: ethernet-phy@00 {
qe_phy0: ethernet-phy@07 {
interrupt-parent = <&mpic>;
interrupts = <1 1>;
reg = <0>;
reg = <7>;
device_type = "ethernet-phy";
};
qe_phy1: ethernet-phy@01 {
@ -449,11 +403,77 @@
#address-cells = <0>;
#interrupt-cells = <1>;
reg = <80 80>;
built-in;
big-endian;
interrupts = <2e 2 2e 2>; //high:30 low:30
interrupt-parent = <&mpic>;
};
};
pci@e0008000 {
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x12 AD18 */
9000 0 0 1 &mpic 5 1
9000 0 0 2 &mpic 6 1
9000 0 0 3 &mpic 7 1
9000 0 0 4 &mpic 4 1
/* IDSEL 0x13 AD19 */
9800 0 0 1 &mpic 6 1
9800 0 0 2 &mpic 7 1
9800 0 0 3 &mpic 4 1
9800 0 0 4 &mpic 5 1>;
interrupt-parent = <&mpic>;
interrupts = <18 2>;
bus-range = <0 ff>;
ranges = <02000000 0 80000000 80000000 0 20000000
01000000 0 00000000 e2000000 0 00800000>;
clock-frequency = <3f940aa>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <e0008000 1000>;
compatible = "fsl,mpc8540-pci";
device_type = "pci";
};
/* PCI Express */
pcie@e000a000 {
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x0 (PEX) */
00000 0 0 1 &mpic 0 1
00000 0 0 2 &mpic 1 1
00000 0 0 3 &mpic 2 1
00000 0 0 4 &mpic 3 1>;
interrupt-parent = <&mpic>;
interrupts = <1a 2>;
bus-range = <0 ff>;
ranges = <02000000 0 a0000000 a0000000 0 10000000
01000000 0 00000000 e2800000 0 00800000>;
clock-frequency = <1fca055>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <e000a000 1000>;
compatible = "fsl,mpc8548-pcie";
device_type = "pci";
pcie@0 {
reg = <0 0 0 0 0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
ranges = <02000000 0 a0000000
02000000 0 a0000000
0 10000000
01000000 0 00000000
01000000 0 00000000
0 00800000>;
};
};
};

404
arch/powerpc/boot/dts/mpc8572ds.dts Normal file
View File

@ -0,0 +1,404 @@
/*
* MPC8572 DS Device Tree Source
*
* Copyright 2007 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
/ {
model = "fsl,MPC8572DS";
compatible = "fsl,MPC8572DS";
#address-cells = <1>;
#size-cells = <1>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,8572@0 {
device_type = "cpu";
reg = <0>;
d-cache-line-size = <20>; // 32 bytes
i-cache-line-size = <20>; // 32 bytes
d-cache-size = <8000>; // L1, 32K
i-cache-size = <8000>; // L1, 32K
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
};
};
memory {
device_type = "memory";
reg = <00000000 00000000>; // Filled by U-Boot
};
soc8572@ffe00000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
ranges = <00000000 ffe00000 00100000>;
reg = <ffe00000 00001000>; // CCSRBAR & soc regs, remove once parse code for immrbase fixed
bus-frequency = <0>; // Filled out by uboot.
memory-controller@2000 {
compatible = "fsl,mpc8572-memory-controller";
reg = <2000 1000>;
interrupt-parent = <&mpic>;
interrupts = <12 2>;
};
memory-controller@6000 {
compatible = "fsl,mpc8572-memory-controller";
reg = <6000 1000>;
interrupt-parent = <&mpic>;
interrupts = <12 2>;
};
l2-cache-controller@20000 {
compatible = "fsl,mpc8572-l2-cache-controller";
reg = <20000 1000>;
cache-line-size = <20>; // 32 bytes
cache-size = <80000>; // L2, 512K
interrupt-parent = <&mpic>;
interrupts = <10 2>;
};
i2c@3000 {
device_type = "i2c";
compatible = "fsl-i2c";
reg = <3000 100>;
interrupts = <2b 2>;
interrupt-parent = <&mpic>;
dfsrr;
};
i2c@3100 {
device_type = "i2c";
compatible = "fsl-i2c";
reg = <3100 100>;
interrupts = <2b 2>;
interrupt-parent = <&mpic>;
dfsrr;
};
mdio@24520 {
#address-cells = <1>;
#size-cells = <0>;
device_type = "mdio";
compatible = "gianfar";
reg = <24520 20>;
phy0: ethernet-phy@0 {
interrupt-parent = <&mpic>;
interrupts = <a 1>;
reg = <0>;
};
phy1: ethernet-phy@1 {
interrupt-parent = <&mpic>;
interrupts = <a 1>;
reg = <1>;
};
phy2: ethernet-phy@2 {
interrupt-parent = <&mpic>;
interrupts = <a 1>;
reg = <2>;
};
phy3: ethernet-phy@3 {
interrupt-parent = <&mpic>;
interrupts = <a 1>;
reg = <3>;
};
};
ethernet@24000 {
#address-cells = <1>;
#size-cells = <0>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <24000 1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <1d 2 1e 2 22 2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy0>;
phy-connection-type = "rgmii-id";
};
ethernet@25000 {
#address-cells = <1>;
#size-cells = <0>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <25000 1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <23 2 24 2 28 2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy1>;
phy-connection-type = "rgmii-id";
};
ethernet@26000 {
#address-cells = <1>;
#size-cells = <0>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <26000 1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <1f 2 20 2 21 2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy2>;
phy-connection-type = "rgmii-id";
};
ethernet@27000 {
#address-cells = <1>;
#size-cells = <0>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <27000 1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <25 2 26 2 27 2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy3>;
phy-connection-type = "rgmii-id";
};
serial@4500 {
device_type = "serial";
compatible = "ns16550";
reg = <4500 100>;
clock-frequency = <0>;
interrupts = <2a 2>;
interrupt-parent = <&mpic>;
};
serial@4600 {
device_type = "serial";
compatible = "ns16550";
reg = <4600 100>;
clock-frequency = <0>;
interrupts = <2a 2>;
interrupt-parent = <&mpic>;
};
global-utilities@e0000 { //global utilities block
compatible = "fsl,mpc8572-guts";
reg = <e0000 1000>;
fsl,has-rstcr;
};
mpic: pic@40000 {
clock-frequency = <0>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <40000 40000>;
compatible = "chrp,open-pic";
device_type = "open-pic";
big-endian;
};
};
pcie@ffe08000 {
compatible = "fsl,mpc8548-pcie";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <ffe08000 1000>;
bus-range = <0 ff>;
ranges = <02000000 0 80000000 80000000 0 20000000
01000000 0 00000000 ffc00000 0 00010000>;
clock-frequency = <1fca055>;
interrupt-parent = <&mpic>;
interrupts = <18 2>;
interrupt-map-mask = <fb00 0 0 0>;
interrupt-map = <
/* IDSEL 0x11 - PCI slot 1 */
8800 0 0 1 &mpic 2 1
8800 0 0 2 &mpic 3 1
8800 0 0 3 &mpic 4 1
8800 0 0 4 &mpic 1 1
/* IDSEL 0x12 - PCI slot 2 */
9000 0 0 1 &mpic 3 1
9000 0 0 2 &mpic 4 1
9000 0 0 3 &mpic 1 1
9000 0 0 4 &mpic 2 1
// IDSEL 0x1c USB
e000 0 0 0 &i8259 c 2
e100 0 0 0 &i8259 9 2
e200 0 0 0 &i8259 a 2
e300 0 0 0 &i8259 b 2
// IDSEL 0x1d Audio
e800 0 0 0 &i8259 6 2
// IDSEL 0x1e Legacy
f000 0 0 0 &i8259 7 2
f100 0 0 0 &i8259 7 2
// IDSEL 0x1f IDE/SATA
f800 0 0 0 &i8259 e 2
f900 0 0 0 &i8259 5 2
>;
pcie@0 {
reg = <0 0 0 0 0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
ranges = <02000000 0 80000000
02000000 0 80000000
0 20000000
01000000 0 00000000
01000000 0 00000000
0 00100000>;
uli1575@0 {
reg = <0 0 0 0 0>;
#size-cells = <2>;
#address-cells = <3>;
ranges = <02000000 0 80000000
02000000 0 80000000
0 20000000
01000000 0 00000000
01000000 0 00000000
0 00100000>;
isa@1e {
device_type = "isa";
#interrupt-cells = <2>;
#size-cells = <1>;
#address-cells = <2>;
reg = <f000 0 0 0 0>;
ranges = <1 0 01000000 0 0
00001000>;
interrupt-parent = <&i8259>;
i8259: interrupt-controller@20 {
reg = <1 20 2
1 a0 2
1 4d0 2>;
interrupt-controller;
device_type = "interrupt-controller";
#address-cells = <0>;
#interrupt-cells = <2>;
compatible = "chrp,iic";
interrupts = <9 2>;
interrupt-parent = <&mpic>;
};
i8042@60 {
#size-cells = <0>;
#address-cells = <1>;
reg = <1 60 1 1 64 1>;
interrupts = <1 3 c 3>;
interrupt-parent =
<&i8259>;
keyboard@0 {
reg = <0>;
compatible = "pnpPNP,303";
};
mouse@1 {
reg = <1>;
compatible = "pnpPNP,f03";
};
};
rtc@70 {
compatible = "pnpPNP,b00";
reg = <1 70 2>;
};
gpio@400 {
reg = <1 400 80>;
};
};
};
};
};
pcie@ffe09000 {
compatible = "fsl,mpc8548-pcie";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <ffe09000 1000>;
bus-range = <0 ff>;
ranges = <02000000 0 a0000000 a0000000 0 20000000
01000000 0 00000000 ffc10000 0 00010000>;
clock-frequency = <1fca055>;
interrupt-parent = <&mpic>;
interrupts = <1a 2>;
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x0 */
0000 0 0 1 &mpic 4 1
0000 0 0 2 &mpic 5 1
0000 0 0 3 &mpic 6 1
0000 0 0 4 &mpic 7 1
>;
pcie@0 {
reg = <0 0 0 0 0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
ranges = <02000000 0 a0000000
02000000 0 a0000000
0 20000000
01000000 0 00000000
01000000 0 00000000
0 00100000>;
};
};
pcie@ffe0a000 {
compatible = "fsl,mpc8548-pcie";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <ffe0a000 1000>;
bus-range = <0 ff>;
ranges = <02000000 0 c0000000 c0000000 0 20000000
01000000 0 00000000 ffc20000 0 00010000>;
clock-frequency = <1fca055>;
interrupt-parent = <&mpic>;
interrupts = <1b 2>;
interrupt-map = <
/* IDSEL 0x0 */
0000 0 0 1 &mpic 0 1
0000 0 0 2 &mpic 1 1
0000 0 0 3 &mpic 2 1
0000 0 0 4 &mpic 3 1
>;
pcie@0 {
reg = <0 0 0 0 0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
ranges = <02000000 0 c0000000
02000000 0 c0000000
0 20000000
01000000 0 00000000
01000000 0 00000000
0 00100000>;
};
};
};

191
arch/powerpc/boot/dts/mpc8610_hpcd.dts Normal file
View File

@ -0,0 +1,191 @@
/*
* MPC8610 HPCD Device Tree Source
*
* Copyright 2007 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License Version 2 as published
* by the Free Software Foundation.
*/
/ {
model = "MPC8610HPCD";
compatible = "fsl,MPC8610HPCD";
#address-cells = <1>;
#size-cells = <1>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,8610@0 {
device_type = "cpu";
reg = <0>;
d-cache-line-size = <d# 32>; // bytes
i-cache-line-size = <d# 32>; // bytes
d-cache-size = <8000>; // L1, 32K
i-cache-size = <8000>; // L1, 32K
timebase-frequency = <0>; // 33 MHz, from uboot
bus-frequency = <0>; // From uboot
clock-frequency = <0>; // From uboot
};
};
memory {
device_type = "memory";
reg = <00000000 20000000>; // 512M at 0x0
};
soc@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 1000>;
bus-frequency = <0>;
i2c@3000 {
device_type = "i2c";
compatible = "fsl-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <3000 100>;
interrupts = <2b 2>;
interrupt-parent = <&mpic>;
dfsrr;
};
i2c@3100 {
device_type = "i2c";
compatible = "fsl-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <3100 100>;
interrupts = <2b 2>;
interrupt-parent = <&mpic>;
dfsrr;
};
serial@4500 {
device_type = "serial";
compatible = "ns16550";
reg = <4500 100>;
clock-frequency = <0>;
interrupts = <2a 2>;
interrupt-parent = <&mpic>;
};
serial@4600 {
device_type = "serial";
compatible = "ns16550";
reg = <4600 100>;
clock-frequency = <0>;
interrupts = <1c 2>;
interrupt-parent = <&mpic>;
};
mpic: interrupt-controller@40000 {
clock-frequency = <0>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <40000 40000>;
compatible = "chrp,open-pic";
device_type = "open-pic";
big-endian;
};
global-utilities@e0000 {
compatible = "fsl,mpc8610-guts";
reg = <e0000 1000>;
fsl,has-rstcr;
};
};
pci@e0008000 {
compatible = "fsl,mpc8610-pci";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <e0008000 1000>;
bus-range = <0 0>;
ranges = <02000000 0 80000000 80000000 0 10000000
01000000 0 00000000 e1000000 0 00100000>;
clock-frequency = <1fca055>;
interrupt-parent = <&mpic>;
interrupts = <18 2>;
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x11 */
8800 0 0 1 &mpic 4 1
8800 0 0 2 &mpic 5 1
8800 0 0 3 &mpic 6 1
8800 0 0 4 &mpic 7 1
/* IDSEL 0x12 */
9000 0 0 1 &mpic 5 1
9000 0 0 2 &mpic 6 1
9000 0 0 3 &mpic 7 1
9000 0 0 4 &mpic 4 1
>;
};
pcie@e000a000 {
compatible = "fsl,mpc8641-pcie";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <e000a000 1000>;
bus-range = <1 3>;
ranges = <02000000 0 a0000000 a0000000 0 10000000
01000000 0 00000000 e3000000 0 00100000>;
clock-frequency = <1fca055>;
interrupt-parent = <&mpic>;
interrupts = <1a 2>;
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x1b */
d800 0 0 1 &mpic 2 1
/* IDSEL 0x1c*/
e000 0 0 1 &mpic 1 1
e000 0 0 2 &mpic 1 1
e000 0 0 3 &mpic 1 1
e000 0 0 4 &mpic 1 1
/* IDSEL 0x1f */
f800 0 0 1 &mpic 3 0
f800 0 0 2 &mpic 0 1
>;
pcie@0 {
reg = <0 0 0 0 0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
ranges = <02000000 0 a0000000
02000000 0 a0000000
0 10000000
01000000 0 00000000
01000000 0 00000000
0 00100000>;
uli1575@0 {
reg = <0 0 0 0 0>;
#size-cells = <2>;
#address-cells = <3>;
ranges = <02000000 0 a0000000
02000000 0 a0000000
0 10000000
01000000 0 00000000
01000000 0 00000000
0 00100000>;
};
};
};
};

285
arch/powerpc/boot/dts/mpc8641_hpcn.dts
View File

@ -30,7 +30,6 @@
timebase-frequency = <0>; // 33 MHz, from uboot
bus-frequency = <0>; // From uboot
clock-frequency = <0>; // From uboot
32-bit;
};
PowerPC,8641@1 {
device_type = "cpu";
@ -42,7 +41,6 @@
timebase-frequency = <0>; // 33 MHz, from uboot
bus-frequency = <0>; // From uboot
clock-frequency = <0>; // From uboot
32-bit;
};
};
@ -54,13 +52,8 @@
soc8641@f8000000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
ranges = <00001000 f8001000 000ff000
80000000 80000000 20000000
e2000000 e2000000 00100000
a0000000 a0000000 20000000
e3000000 e3000000 00100000>;
ranges = <00000000 f8000000 00100000>;
reg = <f8000000 00001000>; // CCSRBAR
bus-frequency = <0>;
@ -211,50 +204,81 @@
interrupt-parent = <&mpic>;
};
pcie@8000 {
compatible = "fsl,mpc8641-pcie";
device_type = "pci";
#interrupt-cells = <1>;
mpic: pic@40000 {
clock-frequency = <0>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <40000 40000>;
compatible = "chrp,open-pic";
device_type = "open-pic";
big-endian;
};
global-utilities@e0000 {
compatible = "fsl,mpc8641-guts";
reg = <e0000 1000>;
fsl,has-rstcr;
};
};
pcie@f8008000 {
compatible = "fsl,mpc8641-pcie";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <f8008000 1000>;
bus-range = <0 ff>;
ranges = <02000000 0 80000000 80000000 0 20000000
01000000 0 00000000 e2000000 0 00100000>;
clock-frequency = <1fca055>;
interrupt-parent = <&mpic>;
interrupts = <18 2>;
interrupt-map-mask = <fb00 0 0 0>;
interrupt-map = <
/* IDSEL 0x11 */
8800 0 0 1 &i8259 9 2
8800 0 0 2 &i8259 a 2
8800 0 0 3 &i8259 b 2
8800 0 0 4 &i8259 c 2
/* IDSEL 0x12 */
9000 0 0 1 &i8259 a 2
9000 0 0 2 &i8259 b 2
9000 0 0 3 &i8259 c 2
9000 0 0 4 &i8259 9 2
// IDSEL 0x1c USB
e000 0 0 0 &i8259 c 2
e100 0 0 0 &i8259 9 2
e200 0 0 0 &i8259 a 2
e300 0 0 0 &i8259 b 2
// IDSEL 0x1d Audio
e800 0 0 0 &i8259 6 2
// IDSEL 0x1e Legacy
f000 0 0 0 &i8259 7 2
f100 0 0 0 &i8259 7 2
// IDSEL 0x1f IDE/SATA
f800 0 0 0 &i8259 e 2
f900 0 0 0 &i8259 5 2
>;
pcie@0 {
reg = <0 0 0 0 0>;
#size-cells = <2>;
#address-cells = <3>;
reg = <8000 1000>;
bus-range = <0 ff>;
ranges = <02000000 0 80000000 80000000 0 20000000
01000000 0 00000000 e2000000 0 00100000>;
clock-frequency = <1fca055>;
interrupt-parent = <&mpic>;
interrupts = <18 2>;
interrupt-map-mask = <fb00 0 0 0>;
interrupt-map = <
/* IDSEL 0x11 */
8800 0 0 1 &i8259 9 2
8800 0 0 2 &i8259 a 2
8800 0 0 3 &i8259 b 2
8800 0 0 4 &i8259 c 2
device_type = "pci";
ranges = <02000000 0 80000000
02000000 0 80000000
0 20000000
/* IDSEL 0x12 */
9000 0 0 1 &i8259 a 2
9000 0 0 2 &i8259 b 2
9000 0 0 3 &i8259 c 2
9000 0 0 4 &i8259 9 2
// IDSEL 0x1c USB
e000 0 0 0 &i8259 c 2
e100 0 0 0 &i8259 9 2
e200 0 0 0 &i8259 a 2
e300 0 0 0 &i8259 b 2
// IDSEL 0x1d Audio
e800 0 0 0 &i8259 6 2
// IDSEL 0x1e Legacy
f000 0 0 0 &i8259 7 2
f100 0 0 0 &i8259 7 2
// IDSEL 0x1f IDE/SATA
f800 0 0 0 &i8259 e 2
f900 0 0 0 &i8259 5 2
>;
01000000 0 00000000
01000000 0 00000000
0 00100000>;
uli1575@0 {
reg = <0 0 0 0 0>;
#size-cells = <2>;
@ -265,111 +289,96 @@
01000000 0 00000000
01000000 0 00000000
0 00100000>;
isa@1e {
device_type = "isa";
#interrupt-cells = <2>;
#size-cells = <1>;
#address-cells = <2>;
reg = <f000 0 0 0 0>;
ranges = <1 0 01000000 0 0
00001000>;
interrupt-parent = <&i8259>;
pci_bridge@0 {
reg = <0 0 0 0 0>;
#size-cells = <2>;
#address-cells = <3>;
ranges = <02000000 0 80000000
02000000 0 80000000
0 20000000
01000000 0 00000000
01000000 0 00000000
0 00100000>;
isa@1e {
device_type = "isa";
i8259: interrupt-controller@20 {
reg = <1 20 2
1 a0 2
1 4d0 2>;
interrupt-controller;
device_type = "interrupt-controller";
#address-cells = <0>;
#interrupt-cells = <2>;
#size-cells = <1>;
#address-cells = <2>;
reg = <f000 0 0 0 0>;
ranges = <1 0 01000000 0 0
00001000>;
interrupt-parent = <&i8259>;
compatible = "chrp,iic";
interrupts = <9 2>;
interrupt-parent = <&mpic>;
};
i8259: interrupt-controller@20 {
reg = <1 20 2
1 a0 2
1 4d0 2>;
clock-frequency = <0>;
interrupt-controller;
device_type = "interrupt-controller";
#address-cells = <0>;
#interrupt-cells = <2>;
built-in;
compatible = "chrp,iic";
interrupts = <9 2>;
interrupt-parent =
<&mpic>;
i8042@60 {
#size-cells = <0>;
#address-cells = <1>;
reg = <1 60 1 1 64 1>;
interrupts = <1 3 c 3>;
interrupt-parent =
<&i8259>;
keyboard@0 {
reg = <0>;
compatible = "pnpPNP,303";
};
i8042@60 {
#size-cells = <0>;
#address-cells = <1>;
reg = <1 60 1 1 64 1>;
interrupts = <1 3 c 3>;
interrupt-parent =
<&i8259>;
keyboard@0 {
reg = <0>;
compatible = "pnpPNP,303";
};
mouse@1 {
reg = <1>;
compatible = "pnpPNP,f03";
};
mouse@1 {
reg = <1>;
compatible = "pnpPNP,f03";
};
};
rtc@70 {
compatible =
"pnpPNP,b00";
reg = <1 70 2>;
};
rtc@70 {
compatible =
"pnpPNP,b00";
reg = <1 70 2>;
};
gpio@400 {
reg = <1 400 80>;
};
gpio@400 {
reg = <1 400 80>;
};
};
};
};
pcie@9000 {
compatible = "fsl,mpc8641-pcie";
device_type = "pci";
#interrupt-cells = <1>;
};
pcie@f8009000 {
compatible = "fsl,mpc8641-pcie";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <f8009000 1000>;
bus-range = <0 ff>;
ranges = <02000000 0 a0000000 a0000000 0 20000000
01000000 0 00000000 e3000000 0 00100000>;
clock-frequency = <1fca055>;
interrupt-parent = <&mpic>;
interrupts = <19 2>;
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x0 */
0000 0 0 1 &mpic 4 1
0000 0 0 2 &mpic 5 1
0000 0 0 3 &mpic 6 1
0000 0 0 4 &mpic 7 1
>;
pcie@0 {
reg = <0 0 0 0 0>;
#size-cells = <2>;
#address-cells = <3>;
reg = <9000 1000>;
bus-range = <0 ff>;
ranges = <02000000 0 a0000000 a0000000 0 20000000
01000000 0 00000000 e3000000 0 00100000>;
clock-frequency = <1fca055>;
interrupt-parent = <&mpic>;
interrupts = <19 2>;
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x0 */
0000 0 0 1 &mpic 4 1
0000 0 0 2 &mpic 5 1
0000 0 0 3 &mpic 6 1
0000 0 0 4 &mpic 7 1
>;
};
device_type = "pci";
ranges = <02000000 0 a0000000
02000000 0 a0000000
0 20000000
mpic: pic@40000 {
clock-frequency = <0>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <40000 40000>;
built-in;
compatible = "chrp,open-pic";
device_type = "open-pic";
big-endian;
01000000 0 00000000
01000000 0 00000000
0 00100000>;
};
};
};

5
arch/powerpc/boot/dts/mpc866ads.dts
View File

@ -30,7 +30,6 @@
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
32-bit;
interrupts = <f 2>; // decrementer interrupt
interrupt-parent = <&Mpc8xx_pic>;
};
@ -44,7 +43,6 @@
soc866@ff000000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
ranges = <0 ff000000 00100000>;
reg = <ff000000 00000200>;
@ -78,7 +76,6 @@
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0 24>;
built-in;
device_type = "mpc8xx-pic";
compatible = "CPM";
};
@ -86,7 +83,6 @@
cpm@ff000000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "cpm";
model = "CPM";
ranges = <0 0 4000>;
@ -103,7 +99,6 @@
interrupts = <5 2 0 2>;
interrupt-parent = <&Mpc8xx_pic>;
reg = <930 20>;
built-in;
device_type = "cpm-pic";
compatible = "CPM";
};

211
arch/powerpc/boot/dts/mpc885ads.dts
View File

@ -2,6 +2,7 @@
* MPC885 ADS Device Tree Source
*
* Copyright 2006 MontaVista Software, Inc.
* Copyright 2007 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
@ -12,7 +13,7 @@
/ {
model = "MPC885ADS";
compatible = "mpc8xx";
compatible = "fsl,mpc885ads";
#address-cells = <1>;
#size-cells = <1>;
@ -23,161 +24,199 @@
PowerPC,885@0 {
device_type = "cpu";
reg = <0>;
d-cache-line-size = <20>; // 32 bytes
i-cache-line-size = <20>; // 32 bytes
d-cache-size = <2000>; // L1, 8K
i-cache-size = <2000>; // L1, 8K
d-cache-line-size = <d#16>;
i-cache-line-size = <d#16>;
d-cache-size = <d#8192>;
i-cache-size = <d#8192>;
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
32-bit;
interrupts = <f 2>; // decrementer interrupt
interrupt-parent = <&Mpc8xx_pic>;
interrupt-parent = <&PIC>;
};
};
memory {
device_type = "memory";
reg = <00000000 800000>;
reg = <0 0>;
};
soc885@ff000000 {
localbus@ff000100 {
compatible = "fsl,mpc885-localbus", "fsl,pq1-localbus";
#address-cells = <2>;
#size-cells = <1>;
reg = <ff000100 40>;
ranges = <
0 0 fe000000 00800000
1 0 ff080000 00008000
5 0 ff0a0000 00008000
>;
flash@0,0 {
compatible = "jedec-flash";
reg = <0 0 800000>;
bank-width = <4>;
device-width = <1>;
};
board-control@1,0 {
reg = <1 0 20 5 300 4>;
compatible = "fsl,mpc885ads-bcsr";
};
};
soc@ff000000 {
compatible = "fsl,mpc885", "fsl,pq1-soc";
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
ranges = <0 ff000000 00100000>;
reg = <ff000000 00000200>;
ranges = <0 ff000000 00004000>;
bus-frequency = <0>;
mdio@e80 {
device_type = "mdio";
compatible = "fs_enet";
reg = <e80 8>;
// Temporary -- will go away once kernel uses ranges for get_immrbase().
reg = <ff000000 4000>;
mdio@e00 {
compatible = "fsl,mpc885-fec-mdio", "fsl,pq1-fec-mdio";
reg = <e00 188>;
#address-cells = <1>;
#size-cells = <0>;
Phy0: ethernet-phy@0 {
PHY0: ethernet-phy@0 {
reg = <0>;
device_type = "ethernet-phy";
};
Phy1: ethernet-phy@1 {
PHY1: ethernet-phy@1 {
reg = <1>;
device_type = "ethernet-phy";
};
Phy2: ethernet-phy@2 {
PHY2: ethernet-phy@2 {
reg = <2>;
device_type = "ethernet-phy";
};
};
fec@e00 {
ethernet@e00 {
device_type = "network";
compatible = "fs_enet";
model = "FEC";
device-id = <1>;
compatible = "fsl,mpc885-fec-enet",
"fsl,pq1-fec-enet";
reg = <e00 188>;
mac-address = [ 00 00 0C 00 01 FD ];
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <3 1>;
interrupt-parent = <&Mpc8xx_pic>;
phy-handle = <&Phy1>;
interrupt-parent = <&PIC>;
phy-handle = <&PHY0>;
linux,network-index = <0>;
};
fec@1e00 {
ethernet@1e00 {
device_type = "network";
compatible = "fs_enet";
model = "FEC";
device-id = <2>;
compatible = "fsl,mpc885-fec-enet",
"fsl,pq1-fec-enet";
reg = <1e00 188>;
mac-address = [ 00 00 0C 00 02 FD ];
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <7 1>;
interrupt-parent = <&Mpc8xx_pic>;
phy-handle = <&Phy2>;
interrupt-parent = <&PIC>;
phy-handle = <&PHY1>;
linux,network-index = <1>;
};
Mpc8xx_pic: pic@ff000000 {
PIC: interrupt-controller@0 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0 24>;
built-in;
device_type = "mpc8xx-pic";
compatible = "CPM";
compatible = "fsl,mpc885-pic", "fsl,pq1-pic";
};
pcmcia@0080 {
pcmcia@80 {
#address-cells = <3>;
#interrupt-cells = <1>;
#size-cells = <2>;
compatible = "fsl,pq-pcmcia";
device_type = "pcmcia";
reg = <80 80>;
interrupt-parent = <&Mpc8xx_pic>;
interrupt-parent = <&PIC>;
interrupts = <d 1>;
};
cpm@ff000000 {
cpm@9c0 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "cpm";
model = "CPM";
ranges = <0 0 4000>;
reg = <860 f0>;
compatible = "fsl,mpc885-cpm", "fsl,cpm1";
command-proc = <9c0>;
brg-frequency = <0>;
interrupts = <0 2>; // cpm error interrupt
interrupt-parent = <&Cpm_pic>;
interrupts = <0>; // cpm error interrupt
interrupt-parent = <&CPM_PIC>;
reg = <9c0 40>;
ranges;
Cpm_pic: pic@930 {
muram@2000 {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 2000 2000>;
data@0 {
compatible = "fsl,cpm-muram-data";
reg = <0 1c00>;
};
};
brg@9f0 {
compatible = "fsl,mpc885-brg",
"fsl,cpm1-brg",
"fsl,cpm-brg";
reg = <9f0 10>;
};
CPM_PIC: interrupt-controller@930 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
#interrupt-cells = <1>;
interrupts = <5 2 0 2>;
interrupt-parent = <&Mpc8xx_pic>;
interrupt-parent = <&PIC>;
reg = <930 20>;
built-in;
device_type = "cpm-pic";
compatible = "CPM";
compatible = "fsl,mpc885-cpm-pic",
"fsl,cpm1-pic";
};
smc@a80 {
serial@a80 {
device_type = "serial";
compatible = "cpm_uart";
model = "SMC";
device-id = <1>;
compatible = "fsl,mpc885-smc-uart",
"fsl,cpm1-smc-uart";
reg = <a80 10 3e80 40>;
clock-setup = <00ffffff 0>;
rx-clock = <1>;
tx-clock = <1>;
current-speed = <0>;
interrupts = <4 3>;
interrupt-parent = <&Cpm_pic>;
interrupts = <4>;
interrupt-parent = <&CPM_PIC>;
fsl,cpm-brg = <1>;
fsl,cpm-command = <0090>;
};
smc@a90 {
serial@a90 {
device_type = "serial";
compatible = "cpm_uart";
model = "SMC";
device-id = <2>;
reg = <a90 20 3f80 40>;
clock-setup = <ff00ffff 90000>;
rx-clock = <2>;
tx-clock = <2>;
current-speed = <0>;
interrupts = <3 3>;
interrupt-parent = <&Cpm_pic>;
compatible = "fsl,mpc885-smc-uart",
"fsl,cpm1-smc-uart";
reg = <a90 10 3f80 40>;
interrupts = <3>;
interrupt-parent = <&CPM_PIC>;
fsl,cpm-brg = <2>;
fsl,cpm-command = <00d0>;
};
scc@a40 {
ethernet@a40 {
device_type = "network";
compatible = "fs_enet";
model = "SCC";
device-id = <3>;
reg = <a40 18 3e00 80>;
mac-address = [ 00 00 0C 00 03 FD ];
interrupts = <1c 3>;
interrupt-parent = <&Cpm_pic>;
phy-handle = <&Phy2>;
compatible = "fsl,mpc885-scc-enet",
"fsl,cpm1-scc-enet";
reg = <a40 18 3e00 100>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <1c>;
interrupt-parent = <&CPM_PIC>;
phy-handle = <&PHY2>;
fsl,cpm-command = <0080>;
linux,network-index = <2>;
};
};
};
chosen {
linux,stdout-path = "/soc/cpm/serial@a80";
};
};

240
arch/powerpc/boot/dts/pq2fads.dts Normal file
View File

@ -0,0 +1,240 @@
/*
* Device Tree for the PQ2FADS-ZU board with an MPC8280 chip.
*
* Copyright 2007 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
/ {
model = "pq2fads";
compatible = "fsl,pq2fads";
#address-cells = <1>;
#size-cells = <1>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
reg = <0>;
d-cache-line-size = <d#32>;
i-cache-line-size = <d#32>;
d-cache-size = <d#16384>;
i-cache-size = <d#16384>;
timebase-frequency = <0>;
clock-frequency = <0>;
};
};
memory {
device_type = "memory";
reg = <0 0>;
};
localbus@f0010100 {
compatible = "fsl,mpc8280-localbus",
"fsl,pq2-localbus";
#address-cells = <2>;
#size-cells = <1>;
reg = <f0010100 60>;
ranges = <0 0 fe000000 00800000
1 0 f4500000 00008000
8 0 f8200000 00008000>;
flash@0,0 {
compatible = "jedec-flash";
reg = <0 0 800000>;
bank-width = <4>;
device-width = <1>;
};
bcsr@1,0 {
reg = <1 0 20>;
compatible = "fsl,pq2fads-bcsr";
};
PCI_PIC: pic@8,0 {
#interrupt-cells = <1>;
interrupt-controller;
reg = <8 0 8>;
compatible = "fsl,pq2ads-pci-pic";
interrupt-parent = <&PIC>;
interrupts = <18 8>;
};
};
pci@f0010800 {
device_type = "pci";
reg = <f0010800 10c f00101ac 8 f00101c4 8>;
compatible = "fsl,mpc8280-pci", "fsl,pq2-pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
clock-frequency = <d#66000000>;
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x16 */
b000 0 0 1 &PCI_PIC 0
b000 0 0 2 &PCI_PIC 1
b000 0 0 3 &PCI_PIC 2
b000 0 0 4 &PCI_PIC 3
/* IDSEL 0x17 */
b800 0 0 1 &PCI_PIC 4
b800 0 0 2 &PCI_PIC 5
b800 0 0 3 &PCI_PIC 6
b800 0 0 4 &PCI_PIC 7
/* IDSEL 0x18 */
c000 0 0 1 &PCI_PIC 8
c000 0 0 2 &PCI_PIC 9
c000 0 0 3 &PCI_PIC a
c000 0 0 4 &PCI_PIC b>;
interrupt-parent = <&PIC>;
interrupts = <12 8>;
ranges = <42000000 0 80000000 80000000 0 20000000
02000000 0 a0000000 a0000000 0 20000000
01000000 0 00000000 f6000000 0 02000000>;
};
soc@f0000000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
compatible = "fsl,mpc8280", "fsl,pq2-soc";
ranges = <00000000 f0000000 00053000>;
// Temporary -- will go away once kernel uses ranges for get_immrbase().
reg = <f0000000 00053000>;
cpm@119c0 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
compatible = "fsl,mpc8280-cpm", "fsl,cpm2";
reg = <119c0 30>;
ranges;
muram@0 {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 10000>;
data@0 {
compatible = "fsl,cpm-muram-data";
reg = <0 2000 9800 800>;
};
};
brg@119f0 {
compatible = "fsl,mpc8280-brg",
"fsl,cpm2-brg",
"fsl,cpm-brg";
reg = <119f0 10 115f0 10>;
};
serial@11a00 {
device_type = "serial";
compatible = "fsl,mpc8280-scc-uart",
"fsl,cpm2-scc-uart";
reg = <11a00 20 8000 100>;
interrupts = <28 8>;
interrupt-parent = <&PIC>;
fsl,cpm-brg = <1>;
fsl,cpm-command = <00800000>;
};
serial@11a20 {
device_type = "serial";
compatible = "fsl,mpc8280-scc-uart",
"fsl,cpm2-scc-uart";
reg = <11a20 20 8100 100>;
interrupts = <29 8>;
interrupt-parent = <&PIC>;
fsl,cpm-brg = <2>;
fsl,cpm-command = <04a00000>;
};
ethernet@11320 {
device_type = "network";
compatible = "fsl,mpc8280-fcc-enet",
"fsl,cpm2-fcc-enet";
reg = <11320 20 8500 100 113b0 1>;
interrupts = <21 8>;
interrupt-parent = <&PIC>;
phy-handle = <&PHY0>;
linux,network-index = <0>;
fsl,cpm-command = <16200300>;
};
ethernet@11340 {
device_type = "network";
compatible = "fsl,mpc8280-fcc-enet",
"fsl,cpm2-fcc-enet";
reg = <11340 20 8600 100 113d0 1>;
interrupts = <22 8>;
interrupt-parent = <&PIC>;
phy-handle = <&PHY1>;
linux,network-index = <1>;
fsl,cpm-command = <1a400300>;
local-mac-address = [00 e0 0c 00 79 01];
};
mdio@10d40 {
device_type = "mdio";
compatible = "fsl,pq2fads-mdio-bitbang",
"fsl,mpc8280-mdio-bitbang",
"fsl,cpm2-mdio-bitbang";
#address-cells = <1>;
#size-cells = <0>;
reg = <10d40 14>;
fsl,mdio-pin = <9>;
fsl,mdc-pin = <a>;
PHY0: ethernet-phy@0 {
interrupt-parent = <&PIC>;
interrupts = <19 2>;
reg = <0>;
device_type = "ethernet-phy";
};
PHY1: ethernet-phy@1 {
interrupt-parent = <&PIC>;
interrupts = <19 2>;
reg = <3>;
device_type = "ethernet-phy";
};
};
usb@11b60 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,mpc8280-usb",
"fsl,cpm2-usb";
reg = <11b60 18 8b00 100>;
interrupt-parent = <&PIC>;
interrupts = <b 8>;
fsl,cpm-command = <2e600000>;
};
};
PIC: interrupt-controller@10c00 {
#interrupt-cells = <2>;
interrupt-controller;
reg = <10c00 80>;
compatible = "fsl,mpc8280-pic", "fsl,cpm2-pic";
};
};
chosen {
linux,stdout-path = "/soc/cpm/serial@11a00";
};
};

5
arch/powerpc/boot/dts/prpmc2800.dts
View File

@ -9,10 +9,6 @@
*
* Property values that are labeled as "Default" will be updated by bootwrapper
* if it can determine the exact PrPMC type.
*
* To build:
* dtc -I dts -O asm -o prpmc2800.S -b 0 prpmc2800.dts
* dtc -I dts -O dtb -o prpmc2800.dtb -b 0 prpmc2800.dts
*/
/ {
@ -47,7 +43,6 @@
mv64x60@f1000000 { /* Marvell Discovery */
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <1>;
model = "mv64360"; /* Default */
compatible = "marvell,mv64x60";
clock-frequency = <7f28155>; /* 133.333333 MHz */

302
arch/powerpc/boot/dts/sequoia.dts Normal file
View File

@ -0,0 +1,302 @@
/*
* Device Tree Source for AMCC Sequoia
*
* Based on Bamboo code by Josh Boyer <jwboyer@linux.vnet.ibm.com>
* Copyright (c) 2006, 2007 IBM Corp.
*
* FIXME: Draft only!
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without
* any warranty of any kind, whether express or implied.
*
*/
/ {
#address-cells = <2>;
#size-cells = <1>;
model = "amcc,sequoia";
compatible = "amcc,sequoia";
dcr-parent = <&/cpus/PowerPC,440EPx@0>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,440EPx@0 {
device_type = "cpu";
reg = <0>;
clock-frequency = <0>; /* Filled in by zImage */
timebase-frequency = <0>; /* Filled in by zImage */
i-cache-line-size = <20>;
d-cache-line-size = <20>;
i-cache-size = <8000>;
d-cache-size = <8000>;
dcr-controller;
dcr-access-method = "native";
};
};
memory {
device_type = "memory";
reg = <0 0 0>; /* Filled in by zImage */
};
UIC0: interrupt-controller0 {
compatible = "ibm,uic-440epx","ibm,uic";
interrupt-controller;
cell-index = <0>;
dcr-reg = <0c0 009>;
#address-cells = <0>;
#size-cells = <0>;
#interrupt-cells = <2>;
};
UIC1: interrupt-controller1 {
compatible = "ibm,uic-440epx","ibm,uic";
interrupt-controller;
cell-index = <1>;
dcr-reg = <0d0 009>;
#address-cells = <0>;
#size-cells = <0>;
#interrupt-cells = <2>;
interrupts = <1e 4 1f 4>; /* cascade */
interrupt-parent = <&UIC0>;
};
UIC2: interrupt-controller2 {
compatible = "ibm,uic-440epx","ibm,uic";
interrupt-controller;
cell-index = <2>;
dcr-reg = <0e0 009>;
#address-cells = <0>;
#size-cells = <0>;
#interrupt-cells = <2>;
interrupts = <1c 4 1d 4>; /* cascade */
interrupt-parent = <&UIC0>;
};
SDR0: sdr {
compatible = "ibm,sdr-440epx", "ibm,sdr-440ep";
dcr-reg = <00e 002>;
};
CPR0: cpr {
compatible = "ibm,cpr-440epx", "ibm,cpr-440ep";
dcr-reg = <00c 002>;
};
plb {
compatible = "ibm,plb-440epx", "ibm,plb4";
#address-cells = <2>;
#size-cells = <1>;
ranges;
clock-frequency = <0>; /* Filled in by zImage */
SDRAM0: sdram {
device_type = "memory-controller";
compatible = "ibm,sdram-440epx", "ibm,sdram-44x-ddr2denali";
dcr-reg = <010 2>;
};
DMA0: dma {
compatible = "ibm,dma-440epx", "ibm,dma-4xx";
dcr-reg = <100 027>;
};
MAL0: mcmal {
compatible = "ibm,mcmal-440epx", "ibm,mcmal2";
dcr-reg = <180 62>;
num-tx-chans = <2>;
num-rx-chans = <2>;
interrupt-parent = <&MAL0>;
interrupts = <0 1 2 3 4>;
#interrupt-cells = <1>;
#address-cells = <0>;
#size-cells = <0>;
interrupt-map = </*TXEOB*/ 0 &UIC0 a 4
/*RXEOB*/ 1 &UIC0 b 4
/*SERR*/ 2 &UIC1 0 4
/*TXDE*/ 3 &UIC1 1 4
/*RXDE*/ 4 &UIC1 2 4>;
interrupt-map-mask = <ffffffff>;
};
POB0: opb {
compatible = "ibm,opb-440epx", "ibm,opb";
#address-cells = <1>;
#size-cells = <1>;
ranges = <00000000 1 00000000 80000000
80000000 1 80000000 80000000>;
interrupt-parent = <&UIC1>;
interrupts = <7 4>;
clock-frequency = <0>; /* Filled in by zImage */
EBC0: ebc {
compatible = "ibm,ebc-440epx", "ibm,ebc";
dcr-reg = <012 2>;
#address-cells = <2>;
#size-cells = <1>;
clock-frequency = <0>; /* Filled in by zImage */
interrupts = <5 1>;
interrupt-parent = <&UIC1>;
nor_flash@0,0 {
compatible = "amd,s29gl256n", "cfi-flash";
bank-width = <2>;
reg = <0 000000 4000000>;
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "Kernel";
reg = <0 180000>;
};
partition@180000 {
label = "ramdisk";
reg = <180000 200000>;
};
partition@380000 {
label = "file system";
reg = <380000 3aa0000>;
};
partition@3e20000 {
label = "kozio";
reg = <3e20000 140000>;
};
partition@3f60000 {
label = "env";
reg = <3f60000 40000>;
};
partition@3fa0000 {
label = "u-boot";
reg = <3fa0000 60000>;
};
};
};
UART0: serial@ef600300 {
device_type = "serial";
compatible = "ns16550";
reg = <ef600300 8>;
virtual-reg = <ef600300>;
clock-frequency = <0>; /* Filled in by zImage */
current-speed = <1c200>;
interrupt-parent = <&UIC0>;
interrupts = <0 4>;
};
UART1: serial@ef600400 {
device_type = "serial";
compatible = "ns16550";
reg = <ef600400 8>;
virtual-reg = <ef600400>;
clock-frequency = <0>;
current-speed = <0>;
interrupt-parent = <&UIC0>;
interrupts = <1 4>;
};
UART2: serial@ef600500 {
device_type = "serial";
compatible = "ns16550";
reg = <ef600500 8>;
virtual-reg = <ef600500>;
clock-frequency = <0>;
current-speed = <0>;
interrupt-parent = <&UIC1>;
interrupts = <3 4>;
};
UART3: serial@ef600600 {
device_type = "serial";
compatible = "ns16550";
reg = <ef600600 8>;
virtual-reg = <ef600600>;
clock-frequency = <0>;
current-speed = <0>;
interrupt-parent = <&UIC1>;
interrupts = <4 4>;
};
IIC0: i2c@ef600700 {
device_type = "i2c";
compatible = "ibm,iic-440epx", "ibm,iic";
reg = <ef600700 14>;
interrupt-parent = <&UIC0>;
interrupts = <2 4>;
};
IIC1: i2c@ef600800 {
device_type = "i2c";
compatible = "ibm,iic-440epx", "ibm,iic";
reg = <ef600800 14>;
interrupt-parent = <&UIC0>;
interrupts = <7 4>;
};
ZMII0: emac-zmii@ef600d00 {
device_type = "zmii-interface";
compatible = "ibm,zmii-440epx", "ibm,zmii";
reg = <ef600d00 c>;
};
EMAC0: ethernet@ef600e00 {
linux,network-index = <0>;
device_type = "network";
compatible = "ibm,emac-440epx", "ibm,emac4";
interrupt-parent = <&EMAC0>;
interrupts = <0 1>;
#interrupt-cells = <1>;
#address-cells = <0>;
#size-cells = <0>;
interrupt-map = </*Status*/ 0 &UIC0 18 4
/*Wake*/ 1 &UIC1 1d 4>;
reg = <ef600e00 70>;
local-mac-address = [000000000000];
mal-device = <&MAL0>;
mal-tx-channel = <0>;
mal-rx-channel = <0>;
cell-index = <0>;
max-frame-size = <5dc>;
rx-fifo-size = <1000>;
tx-fifo-size = <800>;
phy-mode = "rmii";
phy-map = <00000000>;
zmii-device = <&ZMII0>;
zmii-channel = <0>;
};
EMAC1: ethernet@ef600f00 {
linux,network-index = <1>;
device_type = "network";
compatible = "ibm,emac-440epx", "ibm,emac4";
interrupt-parent = <&EMAC1>;
interrupts = <0 1>;
#interrupt-cells = <1>;
#address-cells = <0>;
#size-cells = <0>;
interrupt-map = </*Status*/ 0 &UIC0 19 4
/*Wake*/ 1 &UIC1 1f 4>;
reg = <ef600f00 70>;
local-mac-address = [000000000000];
mal-device = <&MAL0>;
mal-tx-channel = <1>;
mal-rx-channel = <1>;
cell-index = <1>;
max-frame-size = <5dc>;
rx-fifo-size = <1000>;
tx-fifo-size = <800>;
phy-mode = "rmii";
phy-map = <00000000>;
zmii-device = <&ZMII0>;
zmii-channel = <1>;
};
};
};
chosen {
linux,stdout-path = "/plb/opb/serial@ef600300";
bootargs = "console=ttyS0,115200";
};
};

190
arch/powerpc/boot/dts/walnut.dts Normal file
View File

@ -0,0 +1,190 @@
/*
* Device Tree Source for IBM Walnut
*
* Copyright 2007 IBM Corp.
* Josh Boyer <jwboyer@linux.vnet.ibm.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without
* any warranty of any kind, whether express or implied.
*/
/ {
#address-cells = <1>;
#size-cells = <1>;
model = "ibm,walnut";
compatible = "ibm,walnut";
dcr-parent = <&/cpus/PowerPC,405GP@0>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,405GP@0 {
device_type = "cpu";
reg = <0>;
clock-frequency = <bebc200>; /* Filled in by zImage */
timebase-frequency = <0>; /* Filled in by zImage */
i-cache-line-size = <20>;
d-cache-line-size = <20>;
i-cache-size = <4000>;
d-cache-size = <4000>;
dcr-controller;
dcr-access-method = "native";
};
};
memory {
device_type = "memory";
reg = <0 0>; /* Filled in by zImage */
};
UIC0: interrupt-controller {
compatible = "ibm,uic";
interrupt-controller;
cell-index = <0>;
dcr-reg = <0c0 9>;
#address-cells = <0>;
#size-cells = <0>;
#interrupt-cells = <2>;
};
plb {
compatible = "ibm,plb3";
#address-cells = <1>;
#size-cells = <1>;
ranges;
clock-frequency = <0>; /* Filled in by zImage */
SDRAM0: memory-controller {
compatible = "ibm,sdram-405gp";
dcr-reg = <010 2>;
};
MAL: mcmal {
compatible = "ibm,mcmal-405gp", "ibm,mcmal";
dcr-reg = <180 62>;
num-tx-chans = <2>;
num-rx-chans = <1>;
interrupt-parent = <&UIC0>;
interrupts = <a 4 b 4 c 4 d 4 e 4>;
};
POB0: opb {
compatible = "ibm,opb-405gp", "ibm,opb";
#address-cells = <1>;
#size-cells = <1>;
ranges = <ef600000 ef600000 a00000>;
dcr-reg = <0a0 5>;
clock-frequency = <0>; /* Filled in by zImage */
UART0: serial@ef600300 {
device_type = "serial";
compatible = "ns16550";
reg = <ef600300 8>;
virtual-reg = <ef600300>;
clock-frequency = <0>; /* Filled in by zImage */
current-speed = <2580>;
interrupt-parent = <&UIC0>;
interrupts = <0 4>;
};
UART1: serial@ef600400 {
device_type = "serial";
compatible = "ns16550";
reg = <ef600400 8>;
virtual-reg = <ef600400>;
clock-frequency = <0>; /* Filled in by zImage */
current-speed = <2580>;
interrupt-parent = <&UIC0>;
interrupts = <1 4>;
};
IIC: i2c@ef600500 {
compatible = "ibm,iic-405gp", "ibm,iic";
reg = <ef600500 11>;
interrupt-parent = <&UIC0>;
interrupts = <2 4>;
};
GPIO: gpio@ef600700 {
compatible = "ibm,gpio-405gp";
reg = <ef600700 20>;
};
EMAC: ethernet@ef600800 {
linux,network-index = <0>;
device_type = "network";
compatible = "ibm,emac-405gp", "ibm,emac";
interrupt-parent = <&UIC0>;
interrupts = <9 4 f 4>;
reg = <ef600800 70>;
mal-device = <&MAL>;
mal-tx-channel = <0 1>;
mal-rx-channel = <0>;
cell-index = <0>;
max-frame-size = <5dc>;
rx-fifo-size = <1000>;
tx-fifo-size = <800>;
phy-mode = "rmii";
phy-map = <00000001>;
};
};
EBC0: ebc {
compatible = "ibm,ebc-405gp", "ibm,ebc";
dcr-reg = <012 2>;
#address-cells = <2>;
#size-cells = <1>;
/* The ranges property is supplied by the bootwrapper
* and is based on the firmware's configuration of the
* EBC bridge
*/
clock-frequency = <0>; /* Filled in by zImage */
sram@0,0 {
reg = <0 0 80000>;
};
flash@0,80000 {
compatible = "jedec-flash";
bank-width = <1>;
reg = <0 80000 80000>;
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "OpenBIOS";
reg = <0 80000>;
read-only;
};
};
ds1743@1,0 {
/* NVRAM and RTC */
compatible = "ds1743";
reg = <1 0 2000>;
};
keyboard@2,0 {
compatible = "intel,82C42PC";
reg = <2 0 2>;
};
ir@3,0 {
compatible = "ti,TIR2000PAG";
reg = <3 0 10>;
};
fpga@7,0 {
compatible = "Walnut-FPGA";
reg = <7 0 10>;
virtual-reg = <f0300005>;
};
};
};
chosen {
linux,stdout-path = "/plb/opb/serial@ef600300";
};
};

45
arch/powerpc/boot/ebony.c
View File

@ -24,12 +24,11 @@
#include "page.h"
#include "ops.h"
#include "reg.h"
#include "io.h"
#include "dcr.h"
#include "4xx.h"
#include "44x.h"
extern char _dtb_start[];
extern char _dtb_end[];
static u8 *ebony_mac0, *ebony_mac1;
/* Calculate 440GP clocks */
@ -92,15 +91,53 @@ void ibm440gp_fixup_clocks(unsigned int sysclk, unsigned int ser_clk)
dt_fixup_clock("/plb/opb/serial@40000300", uart1);
}
#define EBONY_FPGA_PATH "/plb/opb/ebc/fpga"
#define EBONY_FPGA_FLASH_SEL 0x01
#define EBONY_SMALL_FLASH_PATH "/plb/opb/ebc/small-flash"
static void ebony_flashsel_fixup(void)
{
void *devp;
u32 reg[3] = {0x0, 0x0, 0x80000};
u8 *fpga;
u8 fpga_reg0 = 0x0;
devp = finddevice(EBONY_FPGA_PATH);
if (!devp)
fatal("Couldn't locate FPGA node %s\n\r", EBONY_FPGA_PATH);
if (getprop(devp, "virtual-reg", &fpga, sizeof(fpga)) != sizeof(fpga))
fatal("%s has missing or invalid virtual-reg property\n\r",
EBONY_FPGA_PATH);
fpga_reg0 = in_8(fpga);
devp = finddevice(EBONY_SMALL_FLASH_PATH);
if (!devp)
fatal("Couldn't locate small flash node %s\n\r",
EBONY_SMALL_FLASH_PATH);
if (getprop(devp, "reg", reg, sizeof(reg)) != sizeof(reg))
fatal("%s has reg property of unexpected size\n\r",
EBONY_SMALL_FLASH_PATH);
/* Invert address bit 14 (IBM-endian) if FLASH_SEL fpga bit is set */
if (fpga_reg0 & EBONY_FPGA_FLASH_SEL)
reg[1] ^= 0x80000;
setprop(devp, "reg", reg, sizeof(reg));
}
static void ebony_fixups(void)
{
// FIXME: sysclk should be derived by reading the FPGA registers
unsigned long sysclk = 33000000;
ibm440gp_fixup_clocks(sysclk, 6 * 1843200);
ibm44x_fixup_memsize();
ibm4xx_fixup_memsize();
dt_fixup_mac_addresses(ebony_mac0, ebony_mac1);
ibm4xx_fixup_ebc_ranges("/plb/opb/ebc");
ebony_flashsel_fixup();
}
void ebony_init(void *mac0, void *mac1)

54
arch/powerpc/boot/ep88xc.c Normal file
View File

@ -0,0 +1,54 @@
/*
* Embedded Planet EP88xC with PlanetCore firmware
*
* Author: Scott Wood <scottwood@freescale.com>
*
* Copyright (c) 2007 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#include "ops.h"
#include "stdio.h"
#include "planetcore.h"
#include "mpc8xx.h"
static char *table;
static u64 mem_size;
static void platform_fixups(void)
{
u64 val;
dt_fixup_memory(0, mem_size);
planetcore_set_mac_addrs(table);
if (!planetcore_get_decimal(table, PLANETCORE_KEY_CRYSTAL_HZ, &val)) {
printf("No PlanetCore crystal frequency key.\r\n");
return;
}
mpc885_fixup_clocks(val);
}
void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
unsigned long r6, unsigned long r7)
{
table = (char *)r3;
planetcore_prepare_table(table);
if (!planetcore_get_decimal(table, PLANETCORE_KEY_MB_RAM, &mem_size))
return;
mem_size *= 1024 * 1024;
simple_alloc_init(_end, mem_size - (unsigned long)_end, 32, 64);
ft_init(_dtb_start, _dtb_end - _dtb_start, 32);
planetcore_set_stdout_path(table);
serial_console_init();
platform_ops.fixups = platform_fixups;
}

4
arch/powerpc/boot/fixed-head.S Normal file
View File

@ -0,0 +1,4 @@
.text
.global _zimage_start
_zimage_start:
b _zimage_start_lib

100
arch/powerpc/boot/flatdevtree.c
View File

@ -354,16 +354,21 @@ static void ft_put_bin(struct ft_cxt *cxt, const void *data, unsigned int sz)
cxt->p += sza;
}
int ft_begin_node(struct ft_cxt *cxt, const char *name)
char *ft_begin_node(struct ft_cxt *cxt, const char *name)
{
unsigned long nlen = strlen(name) + 1;
unsigned long len = 8 + _ALIGN(nlen, 4);
char *ret;
if (!ft_make_space(cxt, &cxt->p, FT_STRUCT, len))
return -1;
return NULL;
ret = cxt->p;
ft_put_word(cxt, OF_DT_BEGIN_NODE);
ft_put_bin(cxt, name, strlen(name) + 1);
return 0;
return ret;
}
void ft_end_node(struct ft_cxt *cxt)
@ -625,25 +630,17 @@ void ft_end_tree(struct ft_cxt *cxt)
bph->dt_strings_size = cpu_to_be32(ssize);
}
void *ft_find_device(struct ft_cxt *cxt, const char *srch_path)
void *ft_find_device(struct ft_cxt *cxt, const void *top, const char *srch_path)
{
char *node;
/* require absolute path */
if (srch_path[0] != '/')
return NULL;
node = ft_find_descendent(cxt, ft_root_node(cxt), srch_path);
return ft_get_phandle(cxt, node);
}
void *ft_find_device_rel(struct ft_cxt *cxt, const void *top,
const char *srch_path)
{
char *node;
node = ft_node_ph2node(cxt, top);
if (node == NULL)
return NULL;
if (top) {
node = ft_node_ph2node(cxt, top);
if (node == NULL)
return NULL;
} else {
node = ft_root_node(cxt);
}
node = ft_find_descendent(cxt, node, srch_path);
return ft_get_phandle(cxt, node);
@ -945,7 +942,7 @@ int ft_del_prop(struct ft_cxt *cxt, const void *phandle, const char *propname)
void *ft_create_node(struct ft_cxt *cxt, const void *parent, const char *name)
{
struct ft_atom atom;
char *p, *next;
char *p, *next, *ret;
int depth = 0;
if (parent) {
@ -970,11 +967,70 @@ void *ft_create_node(struct ft_cxt *cxt, const void *parent, const char *name)
break;
/* end of node, insert here */
cxt->p = p;
ft_begin_node(cxt, name);
ret = ft_begin_node(cxt, name);
ft_end_node(cxt);
return p;
return ft_get_phandle(cxt, ret);
}
p = next;
}
return NULL;
}
/* Returns the start of the path within the provided buffer, or NULL on
* error.
*/
char *ft_get_path(struct ft_cxt *cxt, const void *phandle,
char *buf, int len)
{
const char *path_comp[FT_MAX_DEPTH];
struct ft_atom atom;
char *p, *next, *pos;
int depth = 0, i;
void *node;
node = ft_node_ph2node(cxt, phandle);
if (node == NULL)
return NULL;
p = ft_root_node(cxt);
while ((next = ft_next(cxt, p, &atom)) != NULL) {
switch (atom.tag) {
case OF_DT_BEGIN_NODE:
path_comp[depth++] = atom.name;
if (p == node)
goto found;
break;
case OF_DT_END_NODE:
if (--depth == 0)
return NULL;
}
p = next;
}
found:
pos = buf;
for (i = 1; i < depth; i++) {
int this_len;
if (len <= 1)
return NULL;
*pos++ = '/';
len--;
strncpy(pos, path_comp[i], len);
if (pos[len - 1] != 0)
return NULL;
this_len = strlen(pos);
len -= this_len;
pos += this_len;
}
return buf;
}

8
arch/powerpc/boot/flatdevtree.h
View File

@ -76,7 +76,7 @@ struct ft_cxt {
unsigned int nodes_used;
};
int ft_begin_node(struct ft_cxt *cxt, const char *name);
char *ft_begin_node(struct ft_cxt *cxt, const char *name);
void ft_end_node(struct ft_cxt *cxt);
void ft_begin_tree(struct ft_cxt *cxt);
@ -96,9 +96,8 @@ int ft_add_rsvmap(struct ft_cxt *cxt, u64 physaddr, u64 size);
void ft_dump_blob(const void *bphp);
void ft_merge_blob(struct ft_cxt *cxt, void *blob);
void *ft_find_device(struct ft_cxt *cxt, const char *srch_path);
void *ft_find_device_rel(struct ft_cxt *cxt, const void *top,
const char *srch_path);
void *ft_find_device(struct ft_cxt *cxt, const void *top,
const char *srch_path);
void *ft_find_descendent(struct ft_cxt *cxt, void *top, const char *srch_path);
int ft_get_prop(struct ft_cxt *cxt, const void *phandle, const char *propname,
void *buf, const unsigned int buflen);
@ -109,5 +108,6 @@ void *ft_find_node_by_prop_value(struct ft_cxt *cxt, const void *prev,
const char *propname, const char *propval,
int proplen);
void *ft_create_node(struct ft_cxt *cxt, const void *parent, const char *name);
char *ft_get_path(struct ft_cxt *cxt, const void *phandle, char *buf, int len);
#endif /* FLATDEVTREE_H */

20
arch/powerpc/boot/flatdevtree_env.h
View File

@ -24,24 +24,4 @@
#define be64_to_cpu(x) (x)
#define cpu_to_be64(x) (x)
static inline int strncmp(const char *cs, const char *ct, size_t count)
{
signed char __res = 0;
while (count) {
if ((__res = *cs - *ct++) != 0 || !*cs++)
break;
count--;
}
return __res;
}
static inline char *strchr(const char *s, int c)
{
for (; *s != (char)c; ++s)
if (*s == '\0')
return NULL;
return (char *)s;
}
#endif /* _PPC_BOOT_FLATDEVTREE_ENV_H_ */

8
arch/powerpc/boot/flatdevtree_misc.c
View File

@ -18,7 +18,7 @@ static struct ft_cxt cxt;
static void *fdtm_finddevice(const char *name)
{
return ft_find_device(&cxt, name);
return ft_find_device(&cxt, NULL, name);
}
static int fdtm_getprop(const void *phandle, const char *propname,
@ -58,6 +58,11 @@ static unsigned long fdtm_finalize(void)
return (unsigned long)cxt.bph;
}
static char *fdtm_get_path(const void *phandle, char *buf, int len)
{
return ft_get_path(&cxt, phandle, buf, len);
}
int ft_init(void *dt_blob, unsigned int max_size, unsigned int max_find_device)
{
dt_ops.finddevice = fdtm_finddevice;
@ -67,6 +72,7 @@ int ft_init(void *dt_blob, unsigned int max_size, unsigned int max_find_device)
dt_ops.create_node = fdtm_create_node;
dt_ops.find_node_by_prop_value = fdtm_find_node_by_prop_value;
dt_ops.finalize = fdtm_finalize;
dt_ops.get_path = fdtm_get_path;
return ft_open(&cxt, dt_blob, max_size, max_find_device,
platform_ops.realloc);

57
arch/powerpc/boot/fsl-soc.c Normal file
View File

@ -0,0 +1,57 @@
/*
* Freescale SOC support functions
*
* Author: Scott Wood <scottwood@freescale.com>
*
* Copyright (c) 2007 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#include "ops.h"
#include "types.h"
#include "fsl-soc.h"
#include "stdio.h"
static u32 prop_buf[MAX_PROP_LEN / 4];
u32 *fsl_get_immr(void)
{
void *soc;
unsigned long ret = 0;
soc = find_node_by_devtype(NULL, "soc");
if (soc) {
int size;
u32 naddr;
size = getprop(soc, "#address-cells", prop_buf, MAX_PROP_LEN);
if (size == 4)
naddr = prop_buf[0];
else
naddr = 2;
if (naddr != 1 && naddr != 2)
goto err;
size = getprop(soc, "ranges", prop_buf, MAX_PROP_LEN);
if (size < 12)
goto err;
if (prop_buf[0] != 0)
goto err;
if (naddr == 2 && prop_buf[1] != 0)
goto err;
if (!dt_xlate_addr(soc, prop_buf + naddr, 8, &ret))
ret = 0;
}
err:
if (!ret)
printf("fsl_get_immr: Failed to find immr base\r\n");
return (u32 *)ret;
}

8
arch/powerpc/boot/fsl-soc.h Normal file
View File

@ -0,0 +1,8 @@
#ifndef _PPC_BOOT_FSL_SOC_H_
#define _PPC_BOOT_FSL_SOC_H_
#include "types.h"
u32 *fsl_get_immr(void);
#endif

8
arch/powerpc/boot/gunzip_util.c
View File

@ -78,6 +78,7 @@ void gunzip_start(struct gunzip_state *state, void *src, int srclen)
fatal("inflateInit2 returned %d\n\r", r);
}
state->s.total_in = hdrlen;
state->s.next_in = src + hdrlen;
state->s.avail_in = srclen - hdrlen;
}
@ -193,13 +194,10 @@ int gunzip_finish(struct gunzip_state *state, void *dst, int dstlen)
{
int len;
len = gunzip_partial(state, dst, dstlen);
if (state->s.workspace) {
len = gunzip_partial(state, dst, dstlen);
zlib_inflateEnd(&state->s);
} else {
/* uncompressed image */
len = min(state->s.avail_in, (unsigned)dstlen);
memcpy(dst, state->s.next_in, len);
}
return len;

5
arch/powerpc/boot/holly.c
View File

@ -21,11 +21,6 @@
#include "ops.h"
#include "io.h"
extern char _start[];
extern char _end[];
extern char _dtb_start[];
extern char _dtb_end[];
BSS_STACK(4096);
void platform_init(unsigned long r3, unsigned long r4, unsigned long r5)

49
arch/powerpc/boot/io.h
View File

@ -1,5 +1,8 @@
#ifndef _IO_H
#define __IO_H
#include "types.h"
/*
* Low-level I/O routines.
*
@ -20,6 +23,37 @@ static inline void out_8(volatile unsigned char *addr, int val)
: "=m" (*addr) : "r" (val));
}
static inline unsigned in_le16(const volatile u16 *addr)
{
unsigned ret;
__asm__ __volatile__("lhbrx %0,0,%1; twi 0,%0,0; isync"
: "=r" (ret) : "r" (addr), "m" (*addr));
return ret;
}
static inline unsigned in_be16(const volatile u16 *addr)
{
unsigned ret;
__asm__ __volatile__("lhz%U1%X1 %0,%1; twi 0,%0,0; isync"
: "=r" (ret) : "m" (*addr));
return ret;
}
static inline void out_le16(volatile u16 *addr, int val)
{
__asm__ __volatile__("sthbrx %1,0,%2; sync" : "=m" (*addr)
: "r" (val), "r" (addr));
}
static inline void out_be16(volatile u16 *addr, int val)
{
__asm__ __volatile__("sth%U0%X0 %1,%0; sync"
: "=m" (*addr) : "r" (val));
}
static inline unsigned in_le32(const volatile unsigned *addr)
{
unsigned ret;
@ -50,4 +84,19 @@ static inline void out_be32(volatile unsigned *addr, int val)
: "=m" (*addr) : "r" (val));
}
static inline void sync(void)
{
asm volatile("sync" : : : "memory");
}
static inline void eieio(void)
{
asm volatile("eieio" : : : "memory");
}
static inline void barrier(void)
{
asm volatile("" : : : "memory");
}
#endif /* _IO_H */

10
arch/powerpc/boot/main.c
View File

@ -19,16 +19,6 @@
#include "flatdevtree.h"
#include "reg.h"
extern char _start[];
extern char __bss_start[];
extern char _end[];
extern char _vmlinux_start[];
extern char _vmlinux_end[];
extern char _initrd_start[];
extern char _initrd_end[];
extern char _dtb_start[];
extern char _dtb_end[];
static struct gunzip_state gzstate;
struct addr_range {

69
arch/powerpc/boot/mpc52xx-psc.c Normal file
View File

@ -0,0 +1,69 @@
/*
* MPC5200 PSC serial console support.
*
* Author: Grant Likely <grant.likely@secretlab.ca>
*
* Copyright (c) 2007 Secret Lab Technologies Ltd.
* Copyright (c) 2007 Freescale Semiconductor, Inc.
*
* It is assumed that the firmware (or the platform file) has already set
* up the port.
*/
#include "types.h"
#include "io.h"
#include "ops.h"
/* Programmable Serial Controller (PSC) status register bits */
#define MPC52xx_PSC_SR 0x04
#define MPC52xx_PSC_SR_RXRDY 0x0100
#define MPC52xx_PSC_SR_RXFULL 0x0200
#define MPC52xx_PSC_SR_TXRDY 0x0400
#define MPC52xx_PSC_SR_TXEMP 0x0800
#define MPC52xx_PSC_BUFFER 0x0C
static void *psc;
static int psc_open(void)
{
/* Assume the firmware has already configured the PSC into
* uart mode */
return 0;
}
static void psc_putc(unsigned char c)
{
while (!(in_be16(psc + MPC52xx_PSC_SR) & MPC52xx_PSC_SR_TXRDY)) ;
out_8(psc + MPC52xx_PSC_BUFFER, c);
}
static unsigned char psc_tstc(void)
{
return (in_be16(psc + MPC52xx_PSC_SR) & MPC52xx_PSC_SR_RXRDY) != 0;
}
static unsigned char psc_getc(void)
{
while (!(in_be16(psc + MPC52xx_PSC_SR) & MPC52xx_PSC_SR_RXRDY)) ;
return in_8(psc + MPC52xx_PSC_BUFFER);
}
int mpc5200_psc_console_init(void *devp, struct serial_console_data *scdp)
{
int n;
/* Get the base address of the psc registers */
n = getprop(devp, "virtual-reg", &psc, sizeof(psc));
if (n != sizeof(psc)) {
if (!dt_xlate_reg(devp, 0, (void *)&psc, NULL))
return -1;
}
scdp->open = psc_open;
scdp->putc = psc_putc;
scdp->getc = psc_getc;
scdp->tstc = psc_tstc;
return 0;
}

82
arch/powerpc/boot/mpc8xx.c Normal file
View File

@ -0,0 +1,82 @@
/*
* MPC8xx support functions
*
* Author: Scott Wood <scottwood@freescale.com>
*
* Copyright (c) 2007 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#include "ops.h"
#include "types.h"
#include "fsl-soc.h"
#include "mpc8xx.h"
#include "stdio.h"
#include "io.h"
#define MPC8XX_PLPRCR (0x284/4) /* PLL and Reset Control Register */
/* Return system clock from crystal frequency */
u32 mpc885_get_clock(u32 crystal)
{
u32 *immr;
u32 plprcr;
int mfi, mfn, mfd, pdf, div;
u32 ret;
immr = fsl_get_immr();
if (!immr) {
printf("mpc885_get_clock: Couldn't get IMMR base.\r\n");
return 0;
}
plprcr = in_be32(&immr[MPC8XX_PLPRCR]);
mfi = (plprcr >> 16) & 15;
if (mfi < 5) {
printf("Warning: PLPRCR[MFI] value of %d out-of-bounds\r\n",
mfi);
mfi = 5;
}
pdf = (plprcr >> 1) & 0xf;
div = (plprcr >> 20) & 3;
mfd = (plprcr >> 22) & 0x1f;
mfn = (plprcr >> 27) & 0x1f;
ret = crystal * mfi;
if (mfn != 0)
ret += crystal * mfn / (mfd + 1);
return ret / (pdf + 1);
}
/* Set common device tree fields based on the given clock frequencies. */
void mpc8xx_set_clocks(u32 sysclk)
{
void *node;
dt_fixup_cpu_clocks(sysclk, sysclk / 16, sysclk);
node = finddevice("/soc/cpm");
if (node)
setprop(node, "clock-frequency", &sysclk, 4);
node = finddevice("/soc/cpm/brg");
if (node)
setprop(node, "clock-frequency", &sysclk, 4);
}
int mpc885_fixup_clocks(u32 crystal)
{
u32 sysclk = mpc885_get_clock(crystal);
if (!sysclk)
return 0;
mpc8xx_set_clocks(sysclk);
return 1;
}

11
arch/powerpc/boot/mpc8xx.h Normal file
View File

@ -0,0 +1,11 @@
#ifndef _PPC_BOOT_MPC8xx_H_
#define _PPC_BOOT_MPC8xx_H_
#include "types.h"
void mpc8xx_set_clocks(u32 sysclk);
u32 mpc885_get_clock(u32 crystal);
int mpc885_fixup_clocks(u32 crystal);
#endif

1
arch/powerpc/boot/mpsc.c
View File

@ -17,7 +17,6 @@
#include "io.h"
#include "ops.h"
extern void udelay(long delay);
#define MPSC_CHR_1 0x000c

2
arch/powerpc/boot/mv64x60_i2c.c
View File

@ -21,8 +21,6 @@
#include "ops.h"
#include "mv64x60.h"
extern void udelay(long);
/* Register defines */
#define MV64x60_I2C_REG_SLAVE_ADDR 0x00
#define MV64x60_I2C_REG_DATA 0x04

2
arch/powerpc/boot/of.c
View File

@ -17,8 +17,6 @@
#include "of.h"
extern char _end[];
/* Value picked to match that used by yaboot */
#define PROG_START 0x01400000 /* only used on 64-bit systems */
#define RAM_END (512<<20) /* Fixme: use OF */

36
arch/powerpc/boot/ops.h
View File

@ -47,6 +47,7 @@ struct dt_ops {
const char *propname,
const char *propval, int proplen);
unsigned long (*finalize)(void);
char *(*get_path)(const void *phandle, char *buf, int len);
};
extern struct dt_ops dt_ops;
@ -82,11 +83,16 @@ int ft_init(void *dt_blob, unsigned int max_size, unsigned int max_find_device);
int serial_console_init(void);
int ns16550_console_init(void *devp, struct serial_console_data *scdp);
int mpsc_console_init(void *devp, struct serial_console_data *scdp);
int cpm_console_init(void *devp, struct serial_console_data *scdp);
int mpc5200_psc_console_init(void *devp, struct serial_console_data *scdp);
int uartlite_console_init(void *devp, struct serial_console_data *scdp);
void *simple_alloc_init(char *base, unsigned long heap_size,
unsigned long granularity, unsigned long max_allocs);
extern void flush_cache(void *, unsigned long);
int dt_xlate_reg(void *node, int res, unsigned long *addr, unsigned long *size);
int dt_xlate_addr(void *node, u32 *buf, int buflen, unsigned long *xlated_addr);
int dt_is_compatible(void *node, const char *compat);
void dt_get_reg_format(void *node, u32 *naddr, u32 *nsize);
static inline void *finddevice(const char *name)
{
@ -156,6 +162,7 @@ static inline void *find_node_by_devtype(const void *prev,
void dt_fixup_memory(u64 start, u64 size);
void dt_fixup_cpu_clocks(u32 cpufreq, u32 tbfreq, u32 busfreq);
void dt_fixup_clock(const char *path, u32 freq);
void dt_fixup_mac_address(u32 index, const u8 *addr);
void __dt_fixup_mac_addresses(u32 startindex, ...);
#define dt_fixup_mac_addresses(...) \
__dt_fixup_mac_addresses(0, __VA_ARGS__, NULL)
@ -167,6 +174,14 @@ static inline void *find_node_by_linuxphandle(const u32 linuxphandle)
(char *)&linuxphandle, sizeof(u32));
}
static inline char *get_path(const void *phandle, char *buf, int len)
{
if (dt_ops.get_path)
return dt_ops.get_path(phandle, buf, len);
return NULL;
}
static inline void *malloc(unsigned long size)
{
return (platform_ops.malloc) ? platform_ops.malloc(size) : NULL;
@ -191,4 +206,25 @@ static inline void exit(void)
static char _bss_stack[size]; \
void *_platform_stack_top = _bss_stack + sizeof(_bss_stack);
extern unsigned long timebase_period_ns;
void udelay(long delay);
extern char _start[];
extern char __bss_start[];
extern char _end[];
extern char _vmlinux_start[];
extern char _vmlinux_end[];
extern char _initrd_start[];
extern char _initrd_end[];
extern char _dtb_start[];
extern char _dtb_end[];
static inline __attribute__((const))
int __ilog2_u32(u32 n)
{
int bit;
asm ("cntlzw %0,%1" : "=r" (bit) : "r" (n));
return 31 - bit;
}
#endif /* _PPC_BOOT_OPS_H_ */

166
arch/powerpc/boot/planetcore.c Normal file
View File

@ -0,0 +1,166 @@
/*
* PlanetCore configuration data support functions
*
* Author: Scott Wood <scottwood@freescale.com>
*
* Copyright (c) 2007 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#include "stdio.h"
#include "stdlib.h"
#include "ops.h"
#include "planetcore.h"
#include "io.h"
/* PlanetCore passes information to the OS in the form of
* a table of key=value strings, separated by newlines.
*
* The list is terminated by an empty string (i.e. two
* consecutive newlines).
*
* To make it easier to parse, we first convert all the
* newlines into null bytes.
*/
void planetcore_prepare_table(char *table)
{
do {
if (*table == '\n')
*table = 0;
table++;
} while (*(table - 1) || *table != '\n');
*table = 0;
}
const char *planetcore_get_key(const char *table, const char *key)
{
int keylen = strlen(key);
do {
if (!strncmp(table, key, keylen) && table[keylen] == '=')
return table + keylen + 1;
table += strlen(table) + 1;
} while (strlen(table) != 0);
return NULL;
}
int planetcore_get_decimal(const char *table, const char *key, u64 *val)
{
const char *str = planetcore_get_key(table, key);
if (!str)
return 0;
*val = strtoull(str, NULL, 10);
return 1;
}
int planetcore_get_hex(const char *table, const char *key, u64 *val)
{
const char *str = planetcore_get_key(table, key);
if (!str)
return 0;
*val = strtoull(str, NULL, 16);
return 1;
}
static u64 mac_table[4] = {
0x000000000000,
0x000000800000,
0x000000400000,
0x000000c00000,
};
void planetcore_set_mac_addrs(const char *table)
{
u8 addr[4][6];
u64 int_addr;
u32 i;
int j;
if (!planetcore_get_hex(table, PLANETCORE_KEY_MAC_ADDR, &int_addr))
return;
for (i = 0; i < 4; i++) {
u64 this_dev_addr = (int_addr & ~0x000000c00000) |
mac_table[i];
for (j = 5; j >= 0; j--) {
addr[i][j] = this_dev_addr & 0xff;
this_dev_addr >>= 8;
}
dt_fixup_mac_address(i, addr[i]);
}
}
static char prop_buf[MAX_PROP_LEN];
void planetcore_set_stdout_path(const char *table)
{
char *path;
const char *label;
void *node, *chosen;
label = planetcore_get_key(table, PLANETCORE_KEY_SERIAL_PORT);
if (!label)
return;
node = find_node_by_prop_value_str(NULL, "linux,planetcore-label",
label);
if (!node)
return;
path = get_path(node, prop_buf, MAX_PROP_LEN);
if (!path)
return;
chosen = finddevice("/chosen");
if (!chosen)
chosen = create_node(NULL, "chosen");
if (!chosen)
return;
setprop_str(chosen, "linux,stdout-path", path);
}
void planetcore_set_serial_speed(const char *table)
{
void *chosen, *stdout;
u64 baud;
u32 baud32;
int len;
chosen = finddevice("/chosen");
if (!chosen)
return;
len = getprop(chosen, "linux,stdout-path", prop_buf, MAX_PROP_LEN);
if (len <= 0)
return;
stdout = finddevice(prop_buf);
if (!stdout) {
printf("planetcore_set_serial_speed: "
"Bad /chosen/linux,stdout-path.\r\n");
return;
}
if (!planetcore_get_decimal(table, PLANETCORE_KEY_SERIAL_BAUD,
&baud)) {
printf("planetcore_set_serial_speed: No SB tag.\r\n");
return;
}
baud32 = baud;
setprop(stdout, "current-speed", &baud32, 4);
}

49
arch/powerpc/boot/planetcore.h Normal file
View File

@ -0,0 +1,49 @@
#ifndef _PPC_BOOT_PLANETCORE_H_
#define _PPC_BOOT_PLANETCORE_H_
#include "types.h"
#define PLANETCORE_KEY_BOARD_TYPE "BO"
#define PLANETCORE_KEY_BOARD_REV "BR"
#define PLANETCORE_KEY_MB_RAM "D1"
#define PLANETCORE_KEY_MAC_ADDR "EA"
#define PLANETCORE_KEY_FLASH_SPEED "FS"
#define PLANETCORE_KEY_IP_ADDR "IP"
#define PLANETCORE_KEY_KB_NVRAM "NV"
#define PLANETCORE_KEY_PROCESSOR "PR"
#define PLANETCORE_KEY_PROC_VARIANT "PV"
#define PLANETCORE_KEY_SERIAL_BAUD "SB"
#define PLANETCORE_KEY_SERIAL_PORT "SP"
#define PLANETCORE_KEY_SWITCH "SW"
#define PLANETCORE_KEY_TEMP_OFFSET "TC"
#define PLANETCORE_KEY_TARGET_IP "TIP"
#define PLANETCORE_KEY_CRYSTAL_HZ "XT"
/* Prepare the table for processing, by turning all newlines
* into NULL bytes.
*/
void planetcore_prepare_table(char *table);
/* Return the value associated with a given key in text,
* decimal, or hex format.
*
* Returns zero/NULL on failure, non-zero on success.
*/
const char *planetcore_get_key(const char *table, const char *key);
int planetcore_get_decimal(const char *table, const char *key, u64 *val);
int planetcore_get_hex(const char *table, const char *key, u64 *val);
/* Updates the device tree local-mac-address properties based
* on the EA tag.
*/
void planetcore_set_mac_addrs(const char *table);
/* Sets the linux,stdout-path in the /chosen node. This requires the
* linux,planetcore-label property in each serial node.
*/
void planetcore_set_stdout_path(const char *table);
/* Sets the current-speed property in the serial node. */
void planetcore_set_serial_speed(const char *table);
#endif

7
arch/powerpc/boot/ppcboot.h
View File

@ -78,17 +78,18 @@ typedef struct bd_info {
hymod_conf_t bi_hymod_conf; /* hymod configuration information */
#endif
#if defined(TARGET_EVB64260) || defined(TARGET_405EP) || defined(TARGET_44x) || \
defined(TARGET_85xx) || defined(TARGET_83xx)
defined(TARGET_85xx) || defined(TARGET_83xx) || defined(TARGET_HAS_ETH1)
/* second onboard ethernet port */
unsigned char bi_enet1addr[6];
#define HAVE_ENET1ADDR
#endif
#if defined(TARGET_EVB64260) || defined(TARGET_440GX) || defined(TARGET_85xx)
#if defined(TARGET_EVB64260) || defined(TARGET_440GX) || \
defined(TARGET_85xx) || defined(TARGET_HAS_ETH2)
/* third onboard ethernet ports */
unsigned char bi_enet2addr[6];
#define HAVE_ENET2ADDR
#endif
#if defined(TARGET_440GX)
#if defined(TARGET_440GX) || defined(TARGET_HAS_ETH3)
/* fourth onboard ethernet ports */
unsigned char bi_enet3addr[6];
#define HAVE_ENET3ADDR

102
arch/powerpc/boot/pq2.c Normal file
View File

@ -0,0 +1,102 @@
/*
* PowerQUICC II support functions
*
* Author: Scott Wood <scottwood@freescale.com>
*
* Copyright (c) 2007 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#include "ops.h"
#include "types.h"
#include "fsl-soc.h"
#include "pq2.h"
#include "stdio.h"
#include "io.h"
#define PQ2_SCCR (0x10c80/4) /* System Clock Configuration Register */
#define PQ2_SCMR (0x10c88/4) /* System Clock Mode Register */
static int pq2_corecnf_map[] = {
3, 2, 2, 2, 4, 4, 5, 9, 6, 11, 8, 10, 3, 12, 7, -1,
6, 5, 13, 2, 14, 4, 15, 9, 0, 11, 8, 10, 16, 12, 7, -1
};
/* Get various clocks from crystal frequency.
* Returns zero on failure and non-zero on success.
*/
int pq2_get_clocks(u32 crystal, u32 *sysfreq, u32 *corefreq,
u32 *timebase, u32 *brgfreq)
{
u32 *immr;
u32 sccr, scmr, mainclk, busclk;
int corecnf, busdf, plldf, pllmf, dfbrg;
immr = fsl_get_immr();
if (!immr) {
printf("pq2_get_clocks: Couldn't get IMMR base.\r\n");
return 0;
}
sccr = in_be32(&immr[PQ2_SCCR]);
scmr = in_be32(&immr[PQ2_SCMR]);
dfbrg = sccr & 3;
corecnf = (scmr >> 24) & 0x1f;
busdf = (scmr >> 20) & 0xf;
plldf = (scmr >> 12) & 1;
pllmf = scmr & 0xfff;
mainclk = crystal * (pllmf + 1) / (plldf + 1);
busclk = mainclk / (busdf + 1);
if (sysfreq)
*sysfreq = mainclk / 2;
if (timebase)
*timebase = busclk / 4;
if (brgfreq)
*brgfreq = mainclk / (1 << ((dfbrg + 1) * 2));
if (corefreq) {
int coremult = pq2_corecnf_map[corecnf];
if (coremult < 0)
*corefreq = mainclk / 2;
else if (coremult == 0)
return 0;
else
*corefreq = busclk * coremult / 2;
}
return 1;
}
/* Set common device tree fields based on the given clock frequencies. */
void pq2_set_clocks(u32 sysfreq, u32 corefreq, u32 timebase, u32 brgfreq)
{
void *node;
dt_fixup_cpu_clocks(corefreq, timebase, sysfreq);
node = finddevice("/soc/cpm");
if (node)
setprop(node, "clock-frequency", &sysfreq, 4);
node = finddevice("/soc/cpm/brg");
if (node)
setprop(node, "clock-frequency", &brgfreq, 4);
}
int pq2_fixup_clocks(u32 crystal)
{
u32 sysfreq, corefreq, timebase, brgfreq;
if (!pq2_get_clocks(crystal, &sysfreq, &corefreq, &timebase, &brgfreq))
return 0;
pq2_set_clocks(sysfreq, corefreq, timebase, brgfreq);
return 1;
}

11
arch/powerpc/boot/pq2.h Normal file
View File

@ -0,0 +1,11 @@
#ifndef _PPC_BOOT_PQ2_H_
#define _PPC_BOOT_PQ2_H_
#include "types.h"
int pq2_get_clocks(u32 crystal, u32 *sysfreq, u32 *corefreq,
u32 *timebase, u32 *brgfreq);
void pq2_set_clocks(u32 sysfreq, u32 corefreq, u32 timebase, u32 brgfreq);
int pq2_fixup_clocks(u32 crystal);
#endif

6
arch/powerpc/boot/prpmc2800.c
View File

@ -21,12 +21,6 @@
#include "gunzip_util.h"
#include "mv64x60.h"
extern char _end[];
extern char _vmlinux_start[], _vmlinux_end[];
extern char _dtb_start[], _dtb_end[];
extern void udelay(long delay);
#define KB 1024U
#define MB (KB*KB)
#define GB (KB*MB)

4
arch/powerpc/boot/ps3.c
View File

@ -120,10 +120,6 @@ void ps3_copy_vectors(void)
void platform_init(void)
{
extern char _end[];
extern char _dtb_start[];
extern char _initrd_start[];
extern char _initrd_end[];
const u32 heapsize = 0x1000000 - (u32)_end; /* 16MiB */
void *chosen;
unsigned long ft_addr;

23
arch/powerpc/boot/serial.c
View File

@ -19,8 +19,6 @@
#include "io.h"
#include "ops.h"
extern void udelay(long delay);
static int serial_open(void)
{
struct serial_console_data *scdp = console_ops.data;
@ -114,29 +112,36 @@ int serial_console_init(void)
{
void *devp;
int rc = -1;
char compat[MAX_PROP_LEN];
devp = serial_get_stdout_devp();
if (devp == NULL)
goto err_out;
if (getprop(devp, "compatible", compat, sizeof(compat)) < 0)
goto err_out;
if (!strcmp(compat, "ns16550"))
if (dt_is_compatible(devp, "ns16550"))
rc = ns16550_console_init(devp, &serial_cd);
else if (!strcmp(compat, "marvell,mpsc"))
else if (dt_is_compatible(devp, "marvell,mpsc"))
rc = mpsc_console_init(devp, &serial_cd);
else if (dt_is_compatible(devp, "fsl,cpm1-scc-uart") ||
dt_is_compatible(devp, "fsl,cpm1-smc-uart") ||
dt_is_compatible(devp, "fsl,cpm2-scc-uart") ||
dt_is_compatible(devp, "fsl,cpm2-smc-uart"))
rc = cpm_console_init(devp, &serial_cd);
else if (dt_is_compatible(devp, "mpc5200-psc-uart"))
rc = mpc5200_psc_console_init(devp, &serial_cd);
else if (dt_is_compatible(devp, "xilinx,uartlite"))
rc = uartlite_console_init(devp, &serial_cd);
/* Add other serial console driver calls here */
if (!rc) {
console_ops.open = serial_open;
console_ops.write = serial_write;
console_ops.edit_cmdline = serial_edit_cmdline;
console_ops.close = serial_close;
console_ops.data = &serial_cd;
if (serial_cd.getc)
console_ops.edit_cmdline = serial_edit_cmdline;
return 0;
}
err_out:

45
arch/powerpc/boot/stdlib.c Normal file
View File

@ -0,0 +1,45 @@
/*
* stdlib functions
*
* Author: Scott Wood <scottwood@freescale.com>
*
* Copyright (c) 2007 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#include "stdlib.h"
/* Not currently supported: leading whitespace, sign, 0x prefix, zero base */
unsigned long long int strtoull(const char *ptr, char **end, int base)
{
unsigned long long ret = 0;
if (base > 36)
goto out;
while (*ptr) {
int digit;
if (*ptr >= '0' && *ptr <= '9' && *ptr < '0' + base)
digit = *ptr - '0';
else if (*ptr >= 'A' && *ptr < 'A' + base - 10)
digit = *ptr - 'A' + 10;
else if (*ptr >= 'a' && *ptr < 'a' + base - 10)
digit = *ptr - 'a' + 10;
else
break;
ret *= base;
ret += digit;
ptr++;
}
out:
if (end)
*end = (char *)ptr;
return ret;
}

6
arch/powerpc/boot/stdlib.h Normal file
View File

@ -0,0 +1,6 @@
#ifndef _PPC_BOOT_STDLIB_H_
#define _PPC_BOOT_STDLIB_H_
unsigned long long int strtoull(const char *ptr, char **end, int base);
#endif

37
arch/powerpc/boot/string.S
View File

@ -49,6 +49,17 @@ strcat:
bne 1b
blr
.globl strchr
strchr:
addi r3,r3,-1
1: lbzu r0,1(r3)
cmpw 0,r0,r4
beqlr
cmpwi 0,r0,0
bne 1b
li r3,0
blr
.globl strcmp
strcmp:
addi r5,r3,-1
@ -61,6 +72,19 @@ strcmp:
beq 1b
blr
.globl strncmp
strncmp:
mtctr r5
addi r5,r3,-1
addi r4,r4,-1
1: lbzu r3,1(r5)
cmpwi 1,r3,0
lbzu r0,1(r4)
subf. r3,r0,r3
beqlr 1
bdnzt eq,1b
blr
.globl strlen
strlen:
addi r4,r3,-1
@ -195,6 +219,19 @@ backwards_memcpy:
mtctr r7
b 1b
.globl memchr
memchr:
cmpwi 0,r5,0
blelr
mtctr r5
addi r3,r3,-1
1: lbzu r0,1(r3)
cmpw r0,r4
beqlr
bdnz 1b
li r3,0
blr
.globl memcmp
memcmp:
cmpwi 0,r5,0

3
arch/powerpc/boot/string.h
View File

@ -5,13 +5,16 @@
extern char *strcpy(char *dest, const char *src);
extern char *strncpy(char *dest, const char *src, size_t n);
extern char *strcat(char *dest, const char *src);
extern char *strchr(const char *s, int c);
extern int strcmp(const char *s1, const char *s2);
extern int strncmp(const char *s1, const char *s2, size_t n);
extern size_t strlen(const char *s);
extern size_t strnlen(const char *s, size_t count);
extern void *memset(void *s, int c, size_t n);
extern void *memmove(void *dest, const void *src, unsigned long n);
extern void *memcpy(void *dest, const void *src, unsigned long n);
extern void *memchr(const void *s, int c, size_t n);
extern int memcmp(const void *s1, const void *s2, size_t n);
#endif /* _PPC_BOOT_STRING_H_ */

43
arch/powerpc/boot/treeboot-bamboo.c Normal file
View File

@ -0,0 +1,43 @@
/*
* Copyright IBM Corporation, 2007
* Josh Boyer <jwboyer@linux.vnet.ibm.com>
*
* Based on ebony wrapper:
* Copyright 2007 David Gibson, IBM Corporation.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; version 2 of the License
*/
#include "ops.h"
#include "stdio.h"
#include "44x.h"
#include "stdlib.h"
BSS_STACK(4096);
#define PIBS_MAC0 0xfffc0400
#define PIBS_MAC1 0xfffc0500
char pibs_mac0[6];
char pibs_mac1[6];
static void read_pibs_mac(void)
{
unsigned long long mac64;
mac64 = strtoull((char *)PIBS_MAC0, 0, 16);
memcpy(&pibs_mac0, (char *)&mac64+2, 6);
mac64 = strtoull((char *)PIBS_MAC1, 0, 16);
memcpy(&pibs_mac1, (char *)&mac64+2, 6);
}
void platform_init(void)
{
unsigned long end_of_ram = 0x8000000;
unsigned long avail_ram = end_of_ram - (unsigned long)_end;
simple_alloc_init(_end, avail_ram, 32, 64);
read_pibs_mac();
bamboo_init((u8 *)&pibs_mac0, (u8 *)&pibs_mac1);
}

2
arch/powerpc/boot/treeboot-ebony.c
View File

@ -16,8 +16,6 @@
#include "stdio.h"
#include "44x.h"
extern char _end[];
BSS_STACK(4096);
#define OPENBIOS_MAC_BASE 0xfffffe0c

131
arch/powerpc/boot/treeboot-walnut.c Normal file
View File

@ -0,0 +1,131 @@
/*
* Old U-boot compatibility for Walnut
*
* Author: Josh Boyer <jwboyer@linux.vnet.ibm.com>
*
* Copyright 2007 IBM Corporation
* Based on cuboot-83xx.c, which is:
* Copyright (c) 2007 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#include "ops.h"
#include "stdio.h"
#include "dcr.h"
#include "4xx.h"
#include "io.h"
BSS_STACK(4096);
void ibm405gp_fixup_clocks(unsigned int sysclk, unsigned int ser_clk)
{
u32 pllmr = mfdcr(DCRN_CPC0_PLLMR);
u32 cpc0_cr0 = mfdcr(DCRN_405_CPC0_CR0);
u32 cpc0_cr1 = mfdcr(DCRN_405_CPC0_CR1);
u32 cpu, plb, opb, ebc, tb, uart0, uart1, m;
u32 fwdv, fbdv, cbdv, opdv, epdv, udiv;
fwdv = (8 - ((pllmr & 0xe0000000) >> 29));
fbdv = (pllmr & 0x1e000000) >> 25;
cbdv = ((pllmr & 0x00060000) >> 17) + 1;
opdv = ((pllmr & 0x00018000) >> 15) + 1;
epdv = ((pllmr & 0x00001800) >> 13) + 2;
udiv = ((cpc0_cr0 & 0x3e) >> 1) + 1;
m = fwdv * fbdv * cbdv;
cpu = sysclk * m / fwdv;
plb = cpu / cbdv;
opb = plb / opdv;
ebc = plb / epdv;
if (cpc0_cr0 & 0x80) {
/* uart0 uses the external clock */
uart0 = ser_clk;
} else {
uart0 = cpu / udiv;
}
if (cpc0_cr0 & 0x40) {
/* uart1 uses the external clock */
uart1 = ser_clk;
} else {
uart1 = cpu / udiv;
}
/* setup the timebase clock to tick at the cpu frequency */
cpc0_cr1 = cpc0_cr1 & ~ 0x00800000;
mtdcr(DCRN_CPC0_CR1, cpc0_cr1);
tb = cpu;
dt_fixup_cpu_clocks(cpu, tb, 0);
dt_fixup_clock("/plb", plb);
dt_fixup_clock("/plb/opb", opb);
dt_fixup_clock("/plb/ebc", ebc);
dt_fixup_clock("/plb/opb/serial@ef600300", uart0);
dt_fixup_clock("/plb/opb/serial@ef600400", uart1);
}
static void walnut_flashsel_fixup(void)
{
void *devp, *sram;
u32 reg_flash[3] = {0x0, 0x0, 0x80000};
u32 reg_sram[3] = {0x0, 0x0, 0x80000};
u8 *fpga;
u8 fpga_brds1 = 0x0;
devp = finddevice("/plb/ebc/fpga");
if (!devp)
fatal("Couldn't locate FPGA node\n\r");
if (getprop(devp, "virtual-reg", &fpga, sizeof(fpga)) != sizeof(fpga))
fatal("no virtual-reg property\n\r");
fpga_brds1 = in_8(fpga);
devp = finddevice("/plb/ebc/flash");
if (!devp)
fatal("Couldn't locate flash node\n\r");
if (getprop(devp, "reg", reg_flash, sizeof(reg_flash)) != sizeof(reg_flash))
fatal("flash reg property has unexpected size\n\r");
sram = finddevice("/plb/ebc/sram");
if (!sram)
fatal("Couldn't locate sram node\n\r");
if (getprop(sram, "reg", reg_sram, sizeof(reg_sram)) != sizeof(reg_sram))
fatal("sram reg property has unexpected size\n\r");
if (fpga_brds1 & 0x1) {
reg_flash[1] ^= 0x80000;
reg_sram[1] ^= 0x80000;
}
setprop(devp, "reg", reg_flash, sizeof(reg_flash));
setprop(sram, "reg", reg_sram, sizeof(reg_sram));
}
static void walnut_fixups(void)
{
ibm4xx_fixup_memsize();
ibm405gp_fixup_clocks(33330000, 0xa8c000);
ibm4xx_quiesce_eth((u32 *)0xef600800, NULL);
ibm4xx_fixup_ebc_ranges("/plb/ebc");
walnut_flashsel_fixup();
}
void platform_init(void)
{
unsigned long end_of_ram = 0x2000000;
unsigned long avail_ram = end_of_ram - (unsigned long) _end;
simple_alloc_init(_end, avail_ram, 32, 32);
platform_ops.fixups = walnut_fixups;
platform_ops.exit = ibm40x_dbcr_reset;
ft_init(_dtb_start, _dtb_end - _dtb_start, 32);
serial_console_init();
}

79
arch/powerpc/boot/uartlite.c Normal file
View File

@ -0,0 +1,79 @@
/*
* Xilinx UARTLITE bootloader driver
*
* Copyright (C) 2007 Secret Lab Technologies Ltd.
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
#include <stdarg.h>
#include <stddef.h>
#include "types.h"
#include "string.h"
#include "stdio.h"
#include "io.h"
#include "ops.h"
#define ULITE_RX 0x00
#define ULITE_TX 0x04
#define ULITE_STATUS 0x08
#define ULITE_CONTROL 0x0c
#define ULITE_STATUS_RXVALID 0x01
#define ULITE_STATUS_TXFULL 0x08
#define ULITE_CONTROL_RST_RX 0x02
static void * reg_base;
static int uartlite_open(void)
{
/* Clear the RX FIFO */
out_be32(reg_base + ULITE_CONTROL, ULITE_CONTROL_RST_RX);
return 0;
}
static void uartlite_putc(unsigned char c)
{
u32 reg = ULITE_STATUS_TXFULL;
while (reg & ULITE_STATUS_TXFULL) /* spin on TXFULL bit */
reg = in_be32(reg_base + ULITE_STATUS);
out_be32(reg_base + ULITE_TX, c);
}
static unsigned char uartlite_getc(void)
{
u32 reg = 0;
while (!(reg & ULITE_STATUS_RXVALID)) /* spin waiting for RXVALID bit */
reg = in_be32(reg_base + ULITE_STATUS);
return in_be32(reg_base + ULITE_RX);
}
static u8 uartlite_tstc(void)
{
u32 reg = in_be32(reg_base + ULITE_STATUS);
return reg & ULITE_STATUS_RXVALID;
}
int uartlite_console_init(void *devp, struct serial_console_data *scdp)
{
int n;
unsigned long reg_phys;
n = getprop(devp, "virtual-reg", &reg_base, sizeof(reg_base));
if (n != sizeof(reg_base)) {
if (!dt_xlate_reg(devp, 0, &reg_phys, NULL))
return -1;
reg_base = (void *)reg_phys;
}
scdp->open = uartlite_open;
scdp->putc = uartlite_putc;
scdp->getc = uartlite_getc;
scdp->tstc = uartlite_tstc;
scdp->close = NULL;
return 0;
}

20
arch/powerpc/boot/wrapper
View File

@ -29,6 +29,7 @@ initrd=
dtb=
dts=
cacheit=
binary=
gzip=.gz
# cross-compilation prefix
@ -142,17 +143,23 @@ miboot|uboot)
isection=initrd
;;
cuboot*)
binary=y
gzip=
;;
ps3)
platformo="$object/ps3-head.o $object/ps3-hvcall.o $object/ps3.o"
lds=$object/zImage.ps3.lds
binary=y
gzip=
ext=bin
objflags="-O binary --set-section-flags=.bss=contents,alloc,load,data"
ksection=.kernel:vmlinux.bin
isection=.kernel:initrd
;;
ep88xc)
platformo="$object/fixed-head.o $object/$platform.o"
binary=y
;;
esac
vmz="$tmpdir/`basename \"$kernel\"`.$ext"
@ -224,6 +231,11 @@ fi
base=0x`${CROSS}nm "$ofile" | grep ' _start$' | cut -d' ' -f1`
entry=`${CROSS}objdump -f "$ofile" | grep '^start address ' | cut -d' ' -f3`
if [ -n "$binary" ]; then
mv "$ofile" "$ofile".elf
${CROSS}objcopy -O binary "$ofile".elf "$ofile".bin
fi
# post-processing needed for some platforms
case "$platform" in
pseries|chrp)
@ -234,8 +246,6 @@ coff)
$object/hack-coff "$ofile"
;;
cuboot*)
mv "$ofile" "$ofile".elf
${CROSS}objcopy -O binary "$ofile".elf "$ofile".bin
gzip -f -9 "$ofile".bin
mkimage -A ppc -O linux -T kernel -C gzip -a "$base" -e "$entry" \
$uboot_version -d "$ofile".bin.gz "$ofile"
@ -259,11 +269,11 @@ ps3)
# then copied to offset 0x100. At runtime the bootwrapper program
# copies the 0x100 bytes at __system_reset_kernel to addr 0x100.
system_reset_overlay=0x`${CROSS}nm "$ofile" \
system_reset_overlay=0x`${CROSS}nm "$ofile".elf \
| grep ' __system_reset_overlay$' \
| cut -d' ' -f1`
system_reset_overlay=`printf "%d" $system_reset_overlay`
system_reset_kernel=0x`${CROSS}nm "$ofile" \
system_reset_kernel=0x`${CROSS}nm "$ofile".elf \
| grep ' __system_reset_kernel$' \
| cut -d' ' -f1`
system_reset_kernel=`printf "%d" $system_reset_kernel`
@ -272,8 +282,6 @@ ps3)
rm -f "$object/otheros.bld"
${CROSS}objcopy -O binary "$ofile" "$ofile.bin"
msg=$(dd if="$ofile.bin" of="$ofile.bin" conv=notrunc \
skip=$overlay_dest seek=$system_reset_kernel \
count=$overlay_size bs=1 2>&1)

775
arch/powerpc/configs/bamboo_defconfig Normal file
View File

@ -0,0 +1,775 @@
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.23-rc1
# Fri Aug 3 10:46:53 2007
#
# CONFIG_PPC64 is not set
#
# Processor support
#
# CONFIG_6xx is not set
# CONFIG_PPC_85xx is not set
# CONFIG_PPC_8xx is not set
# CONFIG_40x is not set
CONFIG_44x=y
# CONFIG_E200 is not set
CONFIG_PPC_FPU=y
CONFIG_4xx=y
CONFIG_BOOKE=y
CONFIG_PTE_64BIT=y
CONFIG_PHYS_64BIT=y
# CONFIG_PPC_MM_SLICES is not set
CONFIG_NOT_COHERENT_CACHE=y
CONFIG_PPC32=y
CONFIG_PPC_MERGE=y
CONFIG_MMU=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_IRQ_PER_CPU=y
CONFIG_RWSEM_XCHGADD_ALGORITHM=y
CONFIG_ARCH_HAS_ILOG2_U32=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_GENERIC_FIND_NEXT_BIT=y
# CONFIG_ARCH_NO_VIRT_TO_BUS is not set
CONFIG_PPC=y
CONFIG_EARLY_PRINTK=y
CONFIG_GENERIC_NVRAM=y
CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
CONFIG_ARCH_MAY_HAVE_PC_FDC=y
CONFIG_PPC_OF=y
CONFIG_OF=y
CONFIG_PPC_UDBG_16550=y
# CONFIG_GENERIC_TBSYNC is not set
CONFIG_AUDIT_ARCH=y
CONFIG_GENERIC_BUG=y
# CONFIG_DEFAULT_UIMAGE is not set
CONFIG_PPC_DCR_NATIVE=y
# CONFIG_PPC_DCR_MMIO is not set
CONFIG_PPC_DCR=y
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
#
# General setup
#
CONFIG_EXPERIMENTAL=y
CONFIG_BROKEN_ON_SMP=y
CONFIG_INIT_ENV_ARG_LIMIT=32
CONFIG_LOCALVERSION=""
CONFIG_LOCALVERSION_AUTO=y
CONFIG_SWAP=y
CONFIG_SYSVIPC=y
CONFIG_SYSVIPC_SYSCTL=y
CONFIG_POSIX_MQUEUE=y
# CONFIG_BSD_PROCESS_ACCT is not set
# CONFIG_TASKSTATS is not set
# CONFIG_USER_NS is not set
# CONFIG_AUDIT is not set
# CONFIG_IKCONFIG is not set
CONFIG_LOG_BUF_SHIFT=14
CONFIG_SYSFS_DEPRECATED=y
# CONFIG_RELAY is not set
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_SYSCTL=y
CONFIG_EMBEDDED=y
CONFIG_SYSCTL_SYSCALL=y
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_ALL is not set
# CONFIG_KALLSYMS_EXTRA_PASS is not set
CONFIG_HOTPLUG=y
CONFIG_PRINTK=y
CONFIG_BUG=y
CONFIG_ELF_CORE=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_ANON_INODES=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
CONFIG_SHMEM=y
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_SLAB=y
# CONFIG_SLUB is not set
# CONFIG_SLOB is not set
CONFIG_RT_MUTEXES=y
# CONFIG_TINY_SHMEM is not set
CONFIG_BASE_SMALL=0
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_MODULE_FORCE_UNLOAD is not set
# CONFIG_MODVERSIONS is not set
# CONFIG_MODULE_SRCVERSION_ALL is not set
CONFIG_KMOD=y
CONFIG_BLOCK=y
CONFIG_LBD=y
# CONFIG_BLK_DEV_IO_TRACE is not set
# CONFIG_LSF is not set
# CONFIG_BLK_DEV_BSG is not set
#
# IO Schedulers
#
CONFIG_IOSCHED_NOOP=y
CONFIG_IOSCHED_AS=y
CONFIG_IOSCHED_DEADLINE=y
CONFIG_IOSCHED_CFQ=y
CONFIG_DEFAULT_AS=y
# CONFIG_DEFAULT_DEADLINE is not set
# CONFIG_DEFAULT_CFQ is not set
# CONFIG_DEFAULT_NOOP is not set
CONFIG_DEFAULT_IOSCHED="anticipatory"
#
# Platform support
#
# CONFIG_PPC_MPC52xx is not set
# CONFIG_PPC_MPC5200 is not set
# CONFIG_PPC_CELL is not set
# CONFIG_PPC_CELL_NATIVE is not set
# CONFIG_PQ2ADS is not set
CONFIG_BAMBOO=y
# CONFIG_EBONY is not set
CONFIG_440EP=y
CONFIG_IBM440EP_ERR42=y
# CONFIG_MPIC is not set
# CONFIG_MPIC_WEIRD is not set
# CONFIG_PPC_I8259 is not set
# CONFIG_PPC_RTAS is not set
# CONFIG_MMIO_NVRAM is not set
# CONFIG_PPC_MPC106 is not set
# CONFIG_PPC_970_NAP is not set
# CONFIG_PPC_INDIRECT_IO is not set
# CONFIG_GENERIC_IOMAP is not set
# CONFIG_CPU_FREQ is not set
# CONFIG_CPM2 is not set
#
# Kernel options
#
# CONFIG_HIGHMEM is not set
# CONFIG_HZ_100 is not set
CONFIG_HZ_250=y
# CONFIG_HZ_300 is not set
# CONFIG_HZ_1000 is not set
CONFIG_HZ=250
CONFIG_PREEMPT_NONE=y
# CONFIG_PREEMPT_VOLUNTARY is not set
# CONFIG_PREEMPT is not set
CONFIG_BINFMT_ELF=y
# CONFIG_BINFMT_MISC is not set
# CONFIG_MATH_EMULATION is not set
CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
CONFIG_ARCH_FLATMEM_ENABLE=y
CONFIG_ARCH_POPULATES_NODE_MAP=y
CONFIG_SELECT_MEMORY_MODEL=y
CONFIG_FLATMEM_MANUAL=y
# CONFIG_DISCONTIGMEM_MANUAL is not set
# CONFIG_SPARSEMEM_MANUAL is not set
CONFIG_FLATMEM=y
CONFIG_FLAT_NODE_MEM_MAP=y
# CONFIG_SPARSEMEM_STATIC is not set
CONFIG_SPLIT_PTLOCK_CPUS=4
CONFIG_RESOURCES_64BIT=y
CONFIG_ZONE_DMA_FLAG=1
CONFIG_BOUNCE=y
CONFIG_VIRT_TO_BUS=y
CONFIG_PROC_DEVICETREE=y
CONFIG_CMDLINE_BOOL=y
CONFIG_CMDLINE=""
CONFIG_SECCOMP=y
CONFIG_WANT_DEVICE_TREE=y
CONFIG_DEVICE_TREE="bamboo.dts"
CONFIG_ISA_DMA_API=y
#
# Bus options
#
CONFIG_ZONE_DMA=y
CONFIG_PPC_INDIRECT_PCI=y
CONFIG_PCI=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_SYSCALL=y
# CONFIG_PCIEPORTBUS is not set
CONFIG_ARCH_SUPPORTS_MSI=y
# CONFIG_PCI_MSI is not set
# CONFIG_PCI_DEBUG is not set
#
# PCCARD (PCMCIA/CardBus) support
#
# CONFIG_PCCARD is not set
# CONFIG_HOTPLUG_PCI is not set
#
# Advanced setup
#
# CONFIG_ADVANCED_OPTIONS is not set
#
# Default settings for advanced configuration options are used
#
CONFIG_HIGHMEM_START=0xfe000000
CONFIG_LOWMEM_SIZE=0x30000000
CONFIG_KERNEL_START=0xc0000000
CONFIG_TASK_SIZE=0x80000000
CONFIG_CONSISTENT_START=0xff100000
CONFIG_CONSISTENT_SIZE=0x00200000
CONFIG_BOOT_LOAD=0x01000000
#
# Networking
#
CONFIG_NET=y
#
# Networking options
#
CONFIG_PACKET=y
# CONFIG_PACKET_MMAP is not set
CONFIG_UNIX=y
# CONFIG_NET_KEY is not set
CONFIG_INET=y
# CONFIG_IP_MULTICAST is not set
# CONFIG_IP_ADVANCED_ROUTER is not set
CONFIG_IP_FIB_HASH=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
# CONFIG_IP_PNP_RARP is not set
# CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE is not set
# CONFIG_ARPD is not set
# CONFIG_SYN_COOKIES is not set
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
# CONFIG_INET_XFRM_TUNNEL is not set
# CONFIG_INET_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
CONFIG_INET_DIAG=y
CONFIG_INET_TCP_DIAG=y
# CONFIG_TCP_CONG_ADVANCED is not set
CONFIG_TCP_CONG_CUBIC=y
CONFIG_DEFAULT_TCP_CONG="cubic"
# CONFIG_TCP_MD5SIG is not set
# CONFIG_IPV6 is not set
# CONFIG_INET6_XFRM_TUNNEL is not set
# CONFIG_INET6_TUNNEL is not set
# CONFIG_NETWORK_SECMARK is not set
# CONFIG_NETFILTER is not set
# CONFIG_IP_DCCP is not set
# CONFIG_IP_SCTP is not set
# CONFIG_TIPC is not set
# CONFIG_ATM is not set
# CONFIG_BRIDGE is not set
# CONFIG_VLAN_8021Q is not set
# CONFIG_DECNET is not set
# CONFIG_LLC2 is not set
# CONFIG_IPX is not set
# CONFIG_ATALK is not set
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_ECONET is not set
# CONFIG_WAN_ROUTER is not set
#
# QoS and/or fair queueing
#
# CONFIG_NET_SCHED is not set
#
# Network testing
#
# CONFIG_NET_PKTGEN is not set
# CONFIG_HAMRADIO is not set
# CONFIG_IRDA is not set
# CONFIG_BT is not set
# CONFIG_AF_RXRPC is not set
#
# Wireless
#
# CONFIG_CFG80211 is not set
# CONFIG_WIRELESS_EXT is not set
# CONFIG_MAC80211 is not set
# CONFIG_IEEE80211 is not set
# CONFIG_RFKILL is not set
# CONFIG_NET_9P is not set
#
# Device Drivers
#
#
# Generic Driver Options
#
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y
CONFIG_FW_LOADER=y
# CONFIG_DEBUG_DRIVER is not set
# CONFIG_DEBUG_DEVRES is not set
# CONFIG_SYS_HYPERVISOR is not set
CONFIG_CONNECTOR=y
CONFIG_PROC_EVENTS=y
# CONFIG_MTD is not set
CONFIG_OF_DEVICE=y
# CONFIG_PARPORT is not set
CONFIG_BLK_DEV=y
# CONFIG_BLK_DEV_FD is not set
# CONFIG_BLK_CPQ_DA is not set
# CONFIG_BLK_CPQ_CISS_DA is not set
# CONFIG_BLK_DEV_DAC960 is not set
# CONFIG_BLK_DEV_UMEM is not set
# CONFIG_BLK_DEV_COW_COMMON is not set
# CONFIG_BLK_DEV_LOOP is not set
# CONFIG_BLK_DEV_NBD is not set
# CONFIG_BLK_DEV_SX8 is not set
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=16
CONFIG_BLK_DEV_RAM_SIZE=35000
CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
# CONFIG_CDROM_PKTCDVD is not set
# CONFIG_ATA_OVER_ETH is not set
# CONFIG_XILINX_SYSACE is not set
CONFIG_MISC_DEVICES=y
# CONFIG_PHANTOM is not set
# CONFIG_EEPROM_93CX6 is not set
# CONFIG_SGI_IOC4 is not set
# CONFIG_TIFM_CORE is not set
# CONFIG_IDE is not set
#
# SCSI device support
#
# CONFIG_RAID_ATTRS is not set
# CONFIG_SCSI is not set
# CONFIG_SCSI_DMA is not set
# CONFIG_SCSI_NETLINK is not set
# CONFIG_ATA is not set
# CONFIG_MD is not set
#
# Fusion MPT device support
#
# CONFIG_FUSION is not set
#
# IEEE 1394 (FireWire) support
#
# CONFIG_FIREWIRE is not set
# CONFIG_IEEE1394 is not set
# CONFIG_I2O is not set
CONFIG_MACINTOSH_DRIVERS=y
# CONFIG_MAC_EMUMOUSEBTN is not set
# CONFIG_WINDFARM is not set
CONFIG_NETDEVICES=y
# CONFIG_NETDEVICES_MULTIQUEUE is not set
# CONFIG_DUMMY is not set
# CONFIG_BONDING is not set
# CONFIG_MACVLAN is not set
# CONFIG_EQUALIZER is not set
# CONFIG_TUN is not set
# CONFIG_ARCNET is not set
# CONFIG_NET_ETHERNET is not set
CONFIG_NETDEV_1000=y
# CONFIG_ACENIC is not set
# CONFIG_DL2K is not set
# CONFIG_E1000 is not set
# CONFIG_NS83820 is not set
# CONFIG_HAMACHI is not set
# CONFIG_YELLOWFIN is not set
# CONFIG_R8169 is not set
# CONFIG_SIS190 is not set
# CONFIG_SKGE is not set
# CONFIG_SKY2 is not set
# CONFIG_VIA_VELOCITY is not set
# CONFIG_TIGON3 is not set
# CONFIG_BNX2 is not set
# CONFIG_QLA3XXX is not set
# CONFIG_ATL1 is not set
CONFIG_NETDEV_10000=y
# CONFIG_CHELSIO_T1 is not set
# CONFIG_CHELSIO_T3 is not set
# CONFIG_IXGB is not set
# CONFIG_S2IO is not set
# CONFIG_MYRI10GE is not set
# CONFIG_NETXEN_NIC is not set
# CONFIG_MLX4_CORE is not set
# CONFIG_TR is not set
#
# Wireless LAN
#
# CONFIG_WLAN_PRE80211 is not set
# CONFIG_WLAN_80211 is not set
# CONFIG_WAN is not set
# CONFIG_FDDI is not set
# CONFIG_HIPPI is not set
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
# CONFIG_SHAPER is not set
# CONFIG_NETCONSOLE is not set
# CONFIG_NETPOLL is not set
# CONFIG_NET_POLL_CONTROLLER is not set
# CONFIG_ISDN is not set
# CONFIG_PHONE is not set
#
# Input device support
#
# CONFIG_INPUT is not set
#
# Hardware I/O ports
#
# CONFIG_SERIO is not set
# CONFIG_GAMEPORT is not set
#
# Character devices
#
# CONFIG_VT is not set
# CONFIG_SERIAL_NONSTANDARD is not set
#
# Serial drivers
#
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
# CONFIG_SERIAL_8250_PCI is not set
CONFIG_SERIAL_8250_NR_UARTS=4
CONFIG_SERIAL_8250_RUNTIME_UARTS=4
CONFIG_SERIAL_8250_EXTENDED=y
# CONFIG_SERIAL_8250_MANY_PORTS is not set
CONFIG_SERIAL_8250_SHARE_IRQ=y
# CONFIG_SERIAL_8250_DETECT_IRQ is not set
# CONFIG_SERIAL_8250_RSA is not set
#
# Non-8250 serial port support
#
# CONFIG_SERIAL_UARTLITE is not set
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
# CONFIG_SERIAL_JSM is not set
CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_UNIX98_PTYS=y
CONFIG_LEGACY_PTYS=y
CONFIG_LEGACY_PTY_COUNT=256
# CONFIG_IPMI_HANDLER is not set
# CONFIG_WATCHDOG is not set
# CONFIG_HW_RANDOM is not set
# CONFIG_NVRAM is not set
# CONFIG_GEN_RTC is not set
# CONFIG_R3964 is not set
# CONFIG_APPLICOM is not set
# CONFIG_AGP is not set
# CONFIG_DRM is not set
# CONFIG_RAW_DRIVER is not set
# CONFIG_TCG_TPM is not set
CONFIG_DEVPORT=y
# CONFIG_I2C is not set
#
# SPI support
#
# CONFIG_SPI is not set
# CONFIG_SPI_MASTER is not set
# CONFIG_W1 is not set
# CONFIG_POWER_SUPPLY is not set
# CONFIG_HWMON is not set
#
# Multifunction device drivers
#
# CONFIG_MFD_SM501 is not set
#
# Multimedia devices
#
# CONFIG_VIDEO_DEV is not set
# CONFIG_DVB_CORE is not set
CONFIG_DAB=y
#
# Graphics support
#
# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
#
# Display device support
#
# CONFIG_DISPLAY_SUPPORT is not set
# CONFIG_VGASTATE is not set
CONFIG_VIDEO_OUTPUT_CONTROL=m
# CONFIG_FB is not set
# CONFIG_FB_IBM_GXT4500 is not set
#
# Sound
#
# CONFIG_SOUND is not set
CONFIG_USB_SUPPORT=y
CONFIG_USB_ARCH_HAS_HCD=y
CONFIG_USB_ARCH_HAS_OHCI=y
CONFIG_USB_ARCH_HAS_EHCI=y
# CONFIG_USB is not set
#
# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
#
#
# USB Gadget Support
#
# CONFIG_USB_GADGET is not set
# CONFIG_MMC is not set
# CONFIG_NEW_LEDS is not set
# CONFIG_INFINIBAND is not set
# CONFIG_EDAC is not set
# CONFIG_RTC_CLASS is not set
#
# DMA Engine support
#
# CONFIG_DMA_ENGINE is not set
#
# DMA Clients
#
#
# DMA Devices
#
#
# Userspace I/O
#
# CONFIG_UIO is not set
#
# File systems
#
CONFIG_EXT2_FS=y
# CONFIG_EXT2_FS_XATTR is not set
# CONFIG_EXT2_FS_XIP is not set
# CONFIG_EXT3_FS is not set
# CONFIG_EXT4DEV_FS is not set
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
# CONFIG_FS_POSIX_ACL is not set
# CONFIG_XFS_FS is not set
# CONFIG_GFS2_FS is not set
# CONFIG_OCFS2_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_ROMFS_FS is not set
CONFIG_INOTIFY=y
CONFIG_INOTIFY_USER=y
# CONFIG_QUOTA is not set
CONFIG_DNOTIFY=y
# CONFIG_AUTOFS_FS is not set
# CONFIG_AUTOFS4_FS is not set
# CONFIG_FUSE_FS is not set
#
# CD-ROM/DVD Filesystems
#
# CONFIG_ISO9660_FS is not set
# CONFIG_UDF_FS is not set
#
# DOS/FAT/NT Filesystems
#
# CONFIG_MSDOS_FS is not set
# CONFIG_VFAT_FS is not set
# CONFIG_NTFS_FS is not set
#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
CONFIG_PROC_KCORE=y
CONFIG_PROC_SYSCTL=y
CONFIG_SYSFS=y
CONFIG_TMPFS=y
# CONFIG_TMPFS_POSIX_ACL is not set
# CONFIG_HUGETLB_PAGE is not set
CONFIG_RAMFS=y
# CONFIG_CONFIGFS_FS is not set
#
# Miscellaneous filesystems
#
# CONFIG_ADFS_FS is not set
# CONFIG_AFFS_FS is not set
# CONFIG_HFS_FS is not set
# CONFIG_HFSPLUS_FS is not set
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
CONFIG_CRAMFS=y
# CONFIG_VXFS_FS is not set
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
#
# Network File Systems
#
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
# CONFIG_NFS_V3_ACL is not set
# CONFIG_NFS_V4 is not set
# CONFIG_NFS_DIRECTIO is not set
# CONFIG_NFSD is not set
CONFIG_ROOT_NFS=y
CONFIG_LOCKD=y
CONFIG_LOCKD_V4=y
CONFIG_NFS_COMMON=y
CONFIG_SUNRPC=y
# CONFIG_SUNRPC_BIND34 is not set
# CONFIG_RPCSEC_GSS_KRB5 is not set
# CONFIG_RPCSEC_GSS_SPKM3 is not set
# CONFIG_SMB_FS is not set
# CONFIG_CIFS is not set
# CONFIG_NCP_FS is not set
# CONFIG_CODA_FS is not set
# CONFIG_AFS_FS is not set
#
# Partition Types
#
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_MSDOS_PARTITION=y
#
# Native Language Support
#
# CONFIG_NLS is not set
#
# Distributed Lock Manager
#
# CONFIG_DLM is not set
# CONFIG_UCC_SLOW is not set
#
# Library routines
#
CONFIG_BITREVERSE=y
# CONFIG_CRC_CCITT is not set
# CONFIG_CRC16 is not set
# CONFIG_CRC_ITU_T is not set
CONFIG_CRC32=y
# CONFIG_CRC7 is not set
# CONFIG_LIBCRC32C is not set
CONFIG_ZLIB_INFLATE=y
CONFIG_PLIST=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_DMA=y
#
# Instrumentation Support
#
# CONFIG_PROFILING is not set
#
# Kernel hacking
#
# CONFIG_PRINTK_TIME is not set
CONFIG_ENABLE_MUST_CHECK=y
CONFIG_MAGIC_SYSRQ=y
# CONFIG_UNUSED_SYMBOLS is not set
# CONFIG_DEBUG_FS is not set
# CONFIG_HEADERS_CHECK is not set
CONFIG_DEBUG_KERNEL=y
# CONFIG_DEBUG_SHIRQ is not set
CONFIG_DETECT_SOFTLOCKUP=y
CONFIG_SCHED_DEBUG=y
# CONFIG_SCHEDSTATS is not set
# CONFIG_TIMER_STATS is not set
# CONFIG_DEBUG_SLAB is not set
# CONFIG_DEBUG_RT_MUTEXES is not set
# CONFIG_RT_MUTEX_TESTER is not set
# CONFIG_DEBUG_SPINLOCK is not set
# CONFIG_DEBUG_MUTEXES is not set
# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
# CONFIG_DEBUG_KOBJECT is not set
# CONFIG_DEBUG_BUGVERBOSE is not set
# CONFIG_DEBUG_INFO is not set
# CONFIG_DEBUG_VM is not set
# CONFIG_DEBUG_LIST is not set
CONFIG_FORCED_INLINING=y
# CONFIG_RCU_TORTURE_TEST is not set
# CONFIG_FAULT_INJECTION is not set
# CONFIG_DEBUG_STACKOVERFLOW is not set
# CONFIG_DEBUG_STACK_USAGE is not set
# CONFIG_DEBUG_PAGEALLOC is not set
CONFIG_DEBUGGER=y
# CONFIG_KGDB is not set
# CONFIG_XMON is not set
# CONFIG_BDI_SWITCH is not set
CONFIG_PPC_EARLY_DEBUG=y
# CONFIG_PPC_EARLY_DEBUG_LPAR is not set
# CONFIG_PPC_EARLY_DEBUG_G5 is not set
# CONFIG_PPC_EARLY_DEBUG_RTAS_PANEL is not set
# CONFIG_PPC_EARLY_DEBUG_RTAS_CONSOLE is not set
# CONFIG_PPC_EARLY_DEBUG_MAPLE is not set
# CONFIG_PPC_EARLY_DEBUG_ISERIES is not set
# CONFIG_PPC_EARLY_DEBUG_PAS_REALMODE is not set
# CONFIG_PPC_EARLY_DEBUG_BEAT is not set
CONFIG_PPC_EARLY_DEBUG_44x=y
CONFIG_PPC_EARLY_DEBUG_44x_PHYSLOW=0xef600300
CONFIG_PPC_EARLY_DEBUG_44x_PHYSHIGH=0x0
#
# Security options
#
# CONFIG_KEYS is not set
# CONFIG_SECURITY is not set
CONFIG_CRYPTO=y
CONFIG_CRYPTO_ALGAPI=y
CONFIG_CRYPTO_BLKCIPHER=y
CONFIG_CRYPTO_MANAGER=y
# CONFIG_CRYPTO_HMAC is not set
# CONFIG_CRYPTO_XCBC is not set
# CONFIG_CRYPTO_NULL is not set
# CONFIG_CRYPTO_MD4 is not set
CONFIG_CRYPTO_MD5=y
# CONFIG_CRYPTO_SHA1 is not set
# CONFIG_CRYPTO_SHA256 is not set
# CONFIG_CRYPTO_SHA512 is not set
# CONFIG_CRYPTO_WP512 is not set
# CONFIG_CRYPTO_TGR192 is not set
# CONFIG_CRYPTO_GF128MUL is not set
CONFIG_CRYPTO_ECB=y
CONFIG_CRYPTO_CBC=y
CONFIG_CRYPTO_PCBC=y
# CONFIG_CRYPTO_LRW is not set
# CONFIG_CRYPTO_CRYPTD is not set
CONFIG_CRYPTO_DES=y
# CONFIG_CRYPTO_FCRYPT is not set
# CONFIG_CRYPTO_BLOWFISH is not set
# CONFIG_CRYPTO_TWOFISH is not set
# CONFIG_CRYPTO_SERPENT is not set
# CONFIG_CRYPTO_AES is not set
# CONFIG_CRYPTO_CAST5 is not set
# CONFIG_CRYPTO_CAST6 is not set
# CONFIG_CRYPTO_TEA is not set
# CONFIG_CRYPTO_ARC4 is not set
# CONFIG_CRYPTO_KHAZAD is not set
# CONFIG_CRYPTO_ANUBIS is not set
# CONFIG_CRYPTO_DEFLATE is not set
# CONFIG_CRYPTO_MICHAEL_MIC is not set
# CONFIG_CRYPTO_CRC32C is not set
# CONFIG_CRYPTO_CAMELLIA is not set
# CONFIG_CRYPTO_TEST is not set
CONFIG_CRYPTO_HW=y

85
arch/powerpc/configs/ebony_defconfig
View File

@ -313,7 +313,80 @@ CONFIG_FW_LOADER=y
# CONFIG_SYS_HYPERVISOR is not set
CONFIG_CONNECTOR=y
CONFIG_PROC_EVENTS=y
# CONFIG_MTD is not set
CONFIG_MTD=y
# CONFIG_MTD_DEBUG is not set
# CONFIG_MTD_CONCAT is not set
CONFIG_MTD_PARTITIONS=y
# CONFIG_MTD_REDBOOT_PARTS is not set
# CONFIG_MTD_CMDLINE_PARTS is not set
#
# User Modules And Translation Layers
#
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLKDEVS=y
CONFIG_MTD_BLOCK=y
# CONFIG_FTL is not set
# CONFIG_NFTL is not set
# CONFIG_INFTL is not set
# CONFIG_RFD_FTL is not set
# CONFIG_SSFDC is not set
#
# RAM/ROM/Flash chip drivers
#
CONFIG_MTD_CFI=y
CONFIG_MTD_JEDECPROBE=y
CONFIG_MTD_GEN_PROBE=y
# CONFIG_MTD_CFI_ADV_OPTIONS is not set
CONFIG_MTD_MAP_BANK_WIDTH_1=y
CONFIG_MTD_MAP_BANK_WIDTH_2=y
CONFIG_MTD_MAP_BANK_WIDTH_4=y
# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
CONFIG_MTD_CFI_I1=y
CONFIG_MTD_CFI_I2=y
# CONFIG_MTD_CFI_I4 is not set
# CONFIG_MTD_CFI_I8 is not set
# CONFIG_MTD_CFI_INTELEXT is not set
CONFIG_MTD_CFI_AMDSTD=y
# CONFIG_MTD_CFI_STAA is not set
CONFIG_MTD_CFI_UTIL=y
# CONFIG_MTD_RAM is not set
# CONFIG_MTD_ROM is not set
# CONFIG_MTD_ABSENT is not set
#
# Mapping drivers for chip access
#
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
# CONFIG_MTD_PHYSMAP is not set
CONFIG_MTD_PHYSMAP_OF=y
# CONFIG_MTD_PLATRAM is not set
#
# Self-contained MTD device drivers
#
# CONFIG_MTD_PMC551 is not set
# CONFIG_MTD_SLRAM is not set
# CONFIG_MTD_PHRAM is not set
# CONFIG_MTD_MTDRAM is not set
# CONFIG_MTD_BLOCK2MTD is not set
#
# Disk-On-Chip Device Drivers
#
# CONFIG_MTD_DOC2000 is not set
# CONFIG_MTD_DOC2001 is not set
# CONFIG_MTD_DOC2001PLUS is not set
# CONFIG_MTD_NAND is not set
# CONFIG_MTD_ONENAND is not set
#
# UBI - Unsorted block images
#
# CONFIG_MTD_UBI is not set
CONFIG_OF_DEVICE=y
# CONFIG_PARPORT is not set
CONFIG_BLK_DEV=y
@ -607,6 +680,15 @@ CONFIG_RAMFS=y
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
CONFIG_JFFS2_FS=y
CONFIG_JFFS2_FS_DEBUG=0
CONFIG_JFFS2_FS_WRITEBUFFER=y
# CONFIG_JFFS2_SUMMARY is not set
# CONFIG_JFFS2_FS_XATTR is not set
# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
CONFIG_JFFS2_ZLIB=y
CONFIG_JFFS2_RTIME=y
# CONFIG_JFFS2_RUBIN is not set
CONFIG_CRAMFS=y
# CONFIG_VXFS_FS is not set
# CONFIG_HPFS_FS is not set
@ -665,6 +747,7 @@ CONFIG_CRC32=y
# CONFIG_CRC7 is not set
# CONFIG_LIBCRC32C is not set
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=y
CONFIG_PLIST=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y

751
arch/powerpc/configs/ep88xc_defconfig Normal file
View File

@ -0,0 +1,751 @@
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.23-rc6
# Fri Sep 14 14:59:56 2007
#
# CONFIG_PPC64 is not set
#
# Processor support
#
# CONFIG_6xx is not set
# CONFIG_PPC_85xx is not set
CONFIG_PPC_8xx=y
# CONFIG_40x is not set
# CONFIG_44x is not set
# CONFIG_E200 is not set
CONFIG_8xx=y
# CONFIG_PPC_MM_SLICES is not set
CONFIG_NOT_COHERENT_CACHE=y
CONFIG_PPC32=y
CONFIG_PPC_MERGE=y
CONFIG_MMU=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_IRQ_PER_CPU=y
CONFIG_RWSEM_XCHGADD_ALGORITHM=y
CONFIG_ARCH_HAS_ILOG2_U32=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_GENERIC_FIND_NEXT_BIT=y
# CONFIG_ARCH_NO_VIRT_TO_BUS is not set
CONFIG_PPC=y
CONFIG_EARLY_PRINTK=y
CONFIG_GENERIC_NVRAM=y
CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
CONFIG_ARCH_MAY_HAVE_PC_FDC=y
CONFIG_PPC_OF=y
CONFIG_OF=y
# CONFIG_PPC_UDBG_16550 is not set
# CONFIG_GENERIC_TBSYNC is not set
CONFIG_AUDIT_ARCH=y
CONFIG_GENERIC_BUG=y
# CONFIG_DEFAULT_UIMAGE is not set
# CONFIG_PPC_DCR_NATIVE is not set
# CONFIG_PPC_DCR_MMIO is not set
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
#
# General setup
#
CONFIG_EXPERIMENTAL=y
CONFIG_BROKEN_ON_SMP=y
CONFIG_INIT_ENV_ARG_LIMIT=32
CONFIG_LOCALVERSION=""
CONFIG_LOCALVERSION_AUTO=y
# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
CONFIG_SYSVIPC_SYSCTL=y
# CONFIG_POSIX_MQUEUE is not set
# CONFIG_BSD_PROCESS_ACCT is not set
# CONFIG_TASKSTATS is not set
# CONFIG_USER_NS is not set
# CONFIG_AUDIT is not set
# CONFIG_IKCONFIG is not set
CONFIG_LOG_BUF_SHIFT=14
CONFIG_SYSFS_DEPRECATED=y
# CONFIG_RELAY is not set
# CONFIG_BLK_DEV_INITRD is not set
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_SYSCTL=y
CONFIG_EMBEDDED=y
# CONFIG_SYSCTL_SYSCALL is not set
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_ALL is not set
# CONFIG_KALLSYMS_EXTRA_PASS is not set
CONFIG_HOTPLUG=y
CONFIG_PRINTK=y
CONFIG_BUG=y
# CONFIG_ELF_CORE is not set
# CONFIG_BASE_FULL is not set
# CONFIG_FUTEX is not set
CONFIG_ANON_INODES=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
CONFIG_SHMEM=y
# CONFIG_VM_EVENT_COUNTERS is not set
CONFIG_SLUB_DEBUG=y
# CONFIG_SLAB is not set
CONFIG_SLUB=y
# CONFIG_SLOB is not set
# CONFIG_TINY_SHMEM is not set
CONFIG_BASE_SMALL=1
# CONFIG_MODULES is not set
CONFIG_BLOCK=y
# CONFIG_LBD is not set
# CONFIG_BLK_DEV_IO_TRACE is not set
# CONFIG_LSF is not set
# CONFIG_BLK_DEV_BSG is not set
#
# IO Schedulers
#
CONFIG_IOSCHED_NOOP=y
# CONFIG_IOSCHED_AS is not set
CONFIG_IOSCHED_DEADLINE=y
# CONFIG_IOSCHED_CFQ is not set
# CONFIG_DEFAULT_AS is not set
CONFIG_DEFAULT_DEADLINE=y
# CONFIG_DEFAULT_CFQ is not set
# CONFIG_DEFAULT_NOOP is not set
CONFIG_DEFAULT_IOSCHED="deadline"
#
# Platform support
#
# CONFIG_PPC_MPC52xx is not set
# CONFIG_PPC_MPC5200 is not set
# CONFIG_PPC_CELL is not set
# CONFIG_PPC_CELL_NATIVE is not set
CONFIG_CPM1=y
# CONFIG_MPC8XXFADS is not set
# CONFIG_MPC86XADS is not set
# CONFIG_MPC885ADS is not set
CONFIG_PPC_EP88XC=y
#
# MPC8xx CPM Options
#
#
# Generic MPC8xx Options
#
CONFIG_8xx_COPYBACK=y
# CONFIG_8xx_CPU6 is not set
CONFIG_8xx_CPU15=y
CONFIG_NO_UCODE_PATCH=y
# CONFIG_USB_SOF_UCODE_PATCH is not set
# CONFIG_I2C_SPI_UCODE_PATCH is not set
# CONFIG_I2C_SPI_SMC1_UCODE_PATCH is not set
# CONFIG_PQ2ADS is not set
# CONFIG_MPIC is not set
# CONFIG_MPIC_WEIRD is not set
# CONFIG_PPC_I8259 is not set
# CONFIG_PPC_RTAS is not set
# CONFIG_MMIO_NVRAM is not set
# CONFIG_PPC_MPC106 is not set
# CONFIG_PPC_970_NAP is not set
# CONFIG_PPC_INDIRECT_IO is not set
# CONFIG_GENERIC_IOMAP is not set
# CONFIG_CPU_FREQ is not set
# CONFIG_CPM2 is not set
CONFIG_PPC_CPM_NEW_BINDING=y
# CONFIG_FSL_ULI1575 is not set
CONFIG_CPM=y
#
# Kernel options
#
# CONFIG_HIGHMEM is not set
CONFIG_HZ_100=y
# CONFIG_HZ_250 is not set
# CONFIG_HZ_300 is not set
# CONFIG_HZ_1000 is not set
CONFIG_HZ=100
CONFIG_PREEMPT_NONE=y
# CONFIG_PREEMPT_VOLUNTARY is not set
# CONFIG_PREEMPT is not set
CONFIG_BINFMT_ELF=y
# CONFIG_BINFMT_MISC is not set
# CONFIG_MATH_EMULATION is not set
CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
CONFIG_ARCH_FLATMEM_ENABLE=y
CONFIG_ARCH_POPULATES_NODE_MAP=y
CONFIG_SELECT_MEMORY_MODEL=y
CONFIG_FLATMEM_MANUAL=y
# CONFIG_DISCONTIGMEM_MANUAL is not set
# CONFIG_SPARSEMEM_MANUAL is not set
CONFIG_FLATMEM=y
CONFIG_FLAT_NODE_MEM_MAP=y
# CONFIG_SPARSEMEM_STATIC is not set
CONFIG_SPLIT_PTLOCK_CPUS=4
# CONFIG_RESOURCES_64BIT is not set
CONFIG_ZONE_DMA_FLAG=1
CONFIG_BOUNCE=y
CONFIG_VIRT_TO_BUS=y
CONFIG_PROC_DEVICETREE=y
# CONFIG_CMDLINE_BOOL is not set
# CONFIG_PM is not set
CONFIG_SUSPEND_UP_POSSIBLE=y
CONFIG_HIBERNATION_UP_POSSIBLE=y
# CONFIG_SECCOMP is not set
CONFIG_WANT_DEVICE_TREE=y
CONFIG_DEVICE_TREE="ep88xc.dts"
CONFIG_ISA_DMA_API=y
#
# Bus options
#
CONFIG_ZONE_DMA=y
CONFIG_FSL_SOC=y
# CONFIG_PCI is not set
# CONFIG_PCI_DOMAINS is not set
# CONFIG_PCI_SYSCALL is not set
# CONFIG_PCI_QSPAN is not set
# CONFIG_ARCH_SUPPORTS_MSI is not set
#
# PCCARD (PCMCIA/CardBus) support
#
# CONFIG_PCCARD is not set
#
# Advanced setup
#
# CONFIG_ADVANCED_OPTIONS is not set
#
# Default settings for advanced configuration options are used
#
CONFIG_HIGHMEM_START=0xfe000000
CONFIG_LOWMEM_SIZE=0x30000000
CONFIG_KERNEL_START=0xc0000000
CONFIG_TASK_SIZE=0x80000000
CONFIG_CONSISTENT_START=0xfd000000
CONFIG_CONSISTENT_SIZE=0x00200000
CONFIG_BOOT_LOAD=0x00400000
#
# Networking
#
CONFIG_NET=y
#
# Networking options
#
CONFIG_PACKET=y
# CONFIG_PACKET_MMAP is not set
CONFIG_UNIX=y
# CONFIG_NET_KEY is not set
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
# CONFIG_IP_ADVANCED_ROUTER is not set
CONFIG_IP_FIB_HASH=y
CONFIG_IP_PNP=y
# CONFIG_IP_PNP_DHCP is not set
# CONFIG_IP_PNP_BOOTP is not set
# CONFIG_IP_PNP_RARP is not set
# CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE is not set
# CONFIG_IP_MROUTE is not set
# CONFIG_ARPD is not set
CONFIG_SYN_COOKIES=y
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
# CONFIG_INET_XFRM_TUNNEL is not set
# CONFIG_INET_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
CONFIG_INET_DIAG=y
CONFIG_INET_TCP_DIAG=y
# CONFIG_TCP_CONG_ADVANCED is not set
CONFIG_TCP_CONG_CUBIC=y
CONFIG_DEFAULT_TCP_CONG="cubic"
# CONFIG_TCP_MD5SIG is not set
# CONFIG_IPV6 is not set
# CONFIG_INET6_XFRM_TUNNEL is not set
# CONFIG_INET6_TUNNEL is not set
# CONFIG_NETWORK_SECMARK is not set
# CONFIG_NETFILTER is not set
# CONFIG_IP_DCCP is not set
# CONFIG_IP_SCTP is not set
# CONFIG_TIPC is not set
# CONFIG_ATM is not set
# CONFIG_BRIDGE is not set
# CONFIG_VLAN_8021Q is not set
# CONFIG_DECNET is not set
# CONFIG_LLC2 is not set
# CONFIG_IPX is not set
# CONFIG_ATALK is not set
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_ECONET is not set
# CONFIG_WAN_ROUTER is not set
#
# QoS and/or fair queueing
#
# CONFIG_NET_SCHED is not set
#
# Network testing
#
# CONFIG_NET_PKTGEN is not set
# CONFIG_HAMRADIO is not set
# CONFIG_IRDA is not set
# CONFIG_BT is not set
# CONFIG_AF_RXRPC is not set
#
# Wireless
#
# CONFIG_CFG80211 is not set
# CONFIG_WIRELESS_EXT is not set
# CONFIG_MAC80211 is not set
# CONFIG_IEEE80211 is not set
# CONFIG_RFKILL is not set
# CONFIG_NET_9P is not set
#
# Device Drivers
#
#
# Generic Driver Options
#
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y
# CONFIG_FW_LOADER is not set
# CONFIG_DEBUG_DRIVER is not set
# CONFIG_DEBUG_DEVRES is not set
# CONFIG_SYS_HYPERVISOR is not set
# CONFIG_CONNECTOR is not set
CONFIG_MTD=y
# CONFIG_MTD_DEBUG is not set
# CONFIG_MTD_CONCAT is not set
# CONFIG_MTD_PARTITIONS is not set
#
# User Modules And Translation Layers
#
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLKDEVS=y
CONFIG_MTD_BLOCK=y
# CONFIG_FTL is not set
# CONFIG_NFTL is not set
# CONFIG_INFTL is not set
# CONFIG_RFD_FTL is not set
# CONFIG_SSFDC is not set
#
# RAM/ROM/Flash chip drivers
#
CONFIG_MTD_CFI=y
# CONFIG_MTD_JEDECPROBE is not set
CONFIG_MTD_GEN_PROBE=y
# CONFIG_MTD_CFI_ADV_OPTIONS is not set
CONFIG_MTD_MAP_BANK_WIDTH_1=y
CONFIG_MTD_MAP_BANK_WIDTH_2=y
CONFIG_MTD_MAP_BANK_WIDTH_4=y
# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
CONFIG_MTD_CFI_I1=y
CONFIG_MTD_CFI_I2=y
# CONFIG_MTD_CFI_I4 is not set
# CONFIG_MTD_CFI_I8 is not set
# CONFIG_MTD_CFI_INTELEXT is not set
CONFIG_MTD_CFI_AMDSTD=y
# CONFIG_MTD_CFI_STAA is not set
CONFIG_MTD_CFI_UTIL=y
# CONFIG_MTD_RAM is not set
# CONFIG_MTD_ROM is not set
# CONFIG_MTD_ABSENT is not set
#
# Mapping drivers for chip access
#
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
# CONFIG_MTD_PHYSMAP is not set
CONFIG_MTD_PHYSMAP_OF=y
# CONFIG_MTD_CFI_FLAGADM is not set
# CONFIG_MTD_PLATRAM is not set
#
# Self-contained MTD device drivers
#
# CONFIG_MTD_SLRAM is not set
# CONFIG_MTD_PHRAM is not set
# CONFIG_MTD_MTDRAM is not set
# CONFIG_MTD_BLOCK2MTD is not set
#
# Disk-On-Chip Device Drivers
#
# CONFIG_MTD_DOC2000 is not set
# CONFIG_MTD_DOC2001 is not set
# CONFIG_MTD_DOC2001PLUS is not set
# CONFIG_MTD_NAND is not set
# CONFIG_MTD_ONENAND is not set
#
# UBI - Unsorted block images
#
# CONFIG_MTD_UBI is not set
CONFIG_OF_DEVICE=y
# CONFIG_PARPORT is not set
# CONFIG_BLK_DEV is not set
# CONFIG_MISC_DEVICES is not set
# CONFIG_IDE is not set
#
# SCSI device support
#
# CONFIG_RAID_ATTRS is not set
# CONFIG_SCSI is not set
# CONFIG_SCSI_DMA is not set
# CONFIG_SCSI_NETLINK is not set
# CONFIG_ATA is not set
# CONFIG_MD is not set
# CONFIG_MACINTOSH_DRIVERS is not set
CONFIG_NETDEVICES=y
# CONFIG_NETDEVICES_MULTIQUEUE is not set
# CONFIG_DUMMY is not set
# CONFIG_BONDING is not set
# CONFIG_MACVLAN is not set
# CONFIG_EQUALIZER is not set
# CONFIG_TUN is not set
CONFIG_PHYLIB=y
#
# MII PHY device drivers
#
# CONFIG_MARVELL_PHY is not set
# CONFIG_DAVICOM_PHY is not set
# CONFIG_QSEMI_PHY is not set
CONFIG_LXT_PHY=y
# CONFIG_CICADA_PHY is not set
# CONFIG_VITESSE_PHY is not set
# CONFIG_SMSC_PHY is not set
# CONFIG_BROADCOM_PHY is not set
# CONFIG_ICPLUS_PHY is not set
# CONFIG_FIXED_PHY is not set
# CONFIG_MDIO_BITBANG is not set
CONFIG_NET_ETHERNET=y
CONFIG_MII=y
CONFIG_FS_ENET=y
# CONFIG_FS_ENET_HAS_SCC is not set
CONFIG_FS_ENET_HAS_FEC=y
# CONFIG_NETDEV_1000 is not set
# CONFIG_NETDEV_10000 is not set
#
# Wireless LAN
#
# CONFIG_WLAN_PRE80211 is not set
# CONFIG_WLAN_80211 is not set
# CONFIG_WAN is not set
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
# CONFIG_SHAPER is not set
# CONFIG_NETCONSOLE is not set
# CONFIG_NETPOLL is not set
# CONFIG_NET_POLL_CONTROLLER is not set
# CONFIG_ISDN is not set
# CONFIG_PHONE is not set
#
# Input device support
#
# CONFIG_INPUT is not set
#
# Hardware I/O ports
#
# CONFIG_SERIO is not set
# CONFIG_GAMEPORT is not set
#
# Character devices
#
# CONFIG_VT is not set
# CONFIG_SERIAL_NONSTANDARD is not set
#
# Serial drivers
#
# CONFIG_SERIAL_8250 is not set
#
# Non-8250 serial port support
#
# CONFIG_SERIAL_UARTLITE is not set
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
CONFIG_SERIAL_CPM=y
CONFIG_SERIAL_CPM_CONSOLE=y
# CONFIG_SERIAL_CPM_SCC1 is not set
# CONFIG_SERIAL_CPM_SCC2 is not set
# CONFIG_SERIAL_CPM_SCC3 is not set
# CONFIG_SERIAL_CPM_SCC4 is not set
CONFIG_SERIAL_CPM_SMC1=y
CONFIG_SERIAL_CPM_SMC2=y
CONFIG_UNIX98_PTYS=y
# CONFIG_LEGACY_PTYS is not set
# CONFIG_IPMI_HANDLER is not set
# CONFIG_WATCHDOG is not set
CONFIG_HW_RANDOM=y
# CONFIG_NVRAM is not set
CONFIG_GEN_RTC=y
# CONFIG_GEN_RTC_X is not set
# CONFIG_R3964 is not set
# CONFIG_RAW_DRIVER is not set
# CONFIG_TCG_TPM is not set
# CONFIG_I2C is not set
#
# SPI support
#
# CONFIG_SPI is not set
# CONFIG_SPI_MASTER is not set
# CONFIG_W1 is not set
# CONFIG_POWER_SUPPLY is not set
# CONFIG_HWMON is not set
#
# Multifunction device drivers
#
# CONFIG_MFD_SM501 is not set
#
# Multimedia devices
#
# CONFIG_VIDEO_DEV is not set
# CONFIG_DVB_CORE is not set
CONFIG_DAB=y
#
# Graphics support
#
# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
#
# Display device support
#
# CONFIG_DISPLAY_SUPPORT is not set
# CONFIG_VGASTATE is not set
# CONFIG_VIDEO_OUTPUT_CONTROL is not set
# CONFIG_FB is not set
# CONFIG_FB_IBM_GXT4500 is not set
#
# Sound
#
# CONFIG_SOUND is not set
# CONFIG_USB_SUPPORT is not set
# CONFIG_MMC is not set
# CONFIG_NEW_LEDS is not set
# CONFIG_EDAC is not set
# CONFIG_RTC_CLASS is not set
#
# DMA Engine support
#
# CONFIG_DMA_ENGINE is not set
#
# DMA Clients
#
#
# DMA Devices
#
#
# Userspace I/O
#
# CONFIG_UIO is not set
#
# File systems
#
# CONFIG_EXT2_FS is not set
# CONFIG_EXT3_FS is not set
# CONFIG_EXT4DEV_FS is not set
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
# CONFIG_FS_POSIX_ACL is not set
# CONFIG_XFS_FS is not set
# CONFIG_GFS2_FS is not set
# CONFIG_OCFS2_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_ROMFS_FS is not set
# CONFIG_INOTIFY is not set
# CONFIG_QUOTA is not set
# CONFIG_DNOTIFY is not set
# CONFIG_AUTOFS_FS is not set
# CONFIG_AUTOFS4_FS is not set
# CONFIG_FUSE_FS is not set
#
# CD-ROM/DVD Filesystems
#
# CONFIG_ISO9660_FS is not set
# CONFIG_UDF_FS is not set
#
# DOS/FAT/NT Filesystems
#
# CONFIG_MSDOS_FS is not set
# CONFIG_VFAT_FS is not set
# CONFIG_NTFS_FS is not set
#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
# CONFIG_PROC_KCORE is not set
CONFIG_PROC_SYSCTL=y
CONFIG_SYSFS=y
CONFIG_TMPFS=y
# CONFIG_TMPFS_POSIX_ACL is not set
# CONFIG_HUGETLB_PAGE is not set
CONFIG_RAMFS=y
# CONFIG_CONFIGFS_FS is not set
#
# Miscellaneous filesystems
#
# CONFIG_ADFS_FS is not set
# CONFIG_AFFS_FS is not set
# CONFIG_HFS_FS is not set
# CONFIG_HFSPLUS_FS is not set
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
# CONFIG_JFFS2_FS is not set
CONFIG_CRAMFS=y
# CONFIG_VXFS_FS is not set
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
#
# Network File Systems
#
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
# CONFIG_NFS_V3_ACL is not set
# CONFIG_NFS_V4 is not set
# CONFIG_NFS_DIRECTIO is not set
# CONFIG_NFSD is not set
CONFIG_ROOT_NFS=y
CONFIG_LOCKD=y
CONFIG_LOCKD_V4=y
CONFIG_NFS_COMMON=y
CONFIG_SUNRPC=y
# CONFIG_SUNRPC_BIND34 is not set
# CONFIG_RPCSEC_GSS_KRB5 is not set
# CONFIG_RPCSEC_GSS_SPKM3 is not set
# CONFIG_SMB_FS is not set
# CONFIG_CIFS is not set
# CONFIG_NCP_FS is not set
# CONFIG_CODA_FS is not set
# CONFIG_AFS_FS is not set
#
# Partition Types
#
CONFIG_PARTITION_ADVANCED=y
# CONFIG_ACORN_PARTITION is not set
# CONFIG_OSF_PARTITION is not set
# CONFIG_AMIGA_PARTITION is not set
# CONFIG_ATARI_PARTITION is not set
# CONFIG_MAC_PARTITION is not set
CONFIG_MSDOS_PARTITION=y
# CONFIG_BSD_DISKLABEL is not set
# CONFIG_MINIX_SUBPARTITION is not set
# CONFIG_SOLARIS_X86_PARTITION is not set
# CONFIG_UNIXWARE_DISKLABEL is not set
# CONFIG_LDM_PARTITION is not set
# CONFIG_SGI_PARTITION is not set
# CONFIG_ULTRIX_PARTITION is not set
# CONFIG_SUN_PARTITION is not set
# CONFIG_KARMA_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
# CONFIG_SYSV68_PARTITION is not set
#
# Native Language Support
#
# CONFIG_NLS is not set
#
# Distributed Lock Manager
#
# CONFIG_DLM is not set
# CONFIG_UCC_SLOW is not set
#
# Library routines
#
# CONFIG_CRC_CCITT is not set
# CONFIG_CRC16 is not set
# CONFIG_CRC_ITU_T is not set
# CONFIG_CRC32 is not set
# CONFIG_CRC7 is not set
# CONFIG_LIBCRC32C is not set
CONFIG_ZLIB_INFLATE=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_DMA=y
#
# Instrumentation Support
#
# CONFIG_PROFILING is not set
#
# Kernel hacking
#
# CONFIG_PRINTK_TIME is not set
CONFIG_ENABLE_MUST_CHECK=y
CONFIG_MAGIC_SYSRQ=y
# CONFIG_UNUSED_SYMBOLS is not set
# CONFIG_DEBUG_FS is not set
# CONFIG_HEADERS_CHECK is not set
CONFIG_DEBUG_KERNEL=y
# CONFIG_DEBUG_SHIRQ is not set
CONFIG_DETECT_SOFTLOCKUP=y
CONFIG_SCHED_DEBUG=y
# CONFIG_SCHEDSTATS is not set
# CONFIG_TIMER_STATS is not set
# CONFIG_SLUB_DEBUG_ON is not set
# CONFIG_DEBUG_SPINLOCK is not set
# CONFIG_DEBUG_MUTEXES is not set
# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
# CONFIG_DEBUG_KOBJECT is not set
CONFIG_DEBUG_BUGVERBOSE=y
CONFIG_DEBUG_INFO=y
# CONFIG_DEBUG_VM is not set
# CONFIG_DEBUG_LIST is not set
CONFIG_FORCED_INLINING=y
# CONFIG_FAULT_INJECTION is not set
# CONFIG_DEBUG_STACKOVERFLOW is not set
# CONFIG_DEBUG_STACK_USAGE is not set
# CONFIG_DEBUG_PAGEALLOC is not set
# CONFIG_DEBUGGER is not set
# CONFIG_BDI_SWITCH is not set
# CONFIG_PPC_EARLY_DEBUG is not set
#
# Security options
#
# CONFIG_KEYS is not set
# CONFIG_SECURITY is not set
# CONFIG_CRYPTO is not set

768
arch/powerpc/configs/kilauea_defconfig Normal file
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@ -0,0 +1,768 @@
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.23-rc9
# Thu Oct 11 19:05:15 2007
#
# CONFIG_PPC64 is not set
#
# Processor support
#
# CONFIG_6xx is not set
# CONFIG_PPC_85xx is not set
# CONFIG_PPC_8xx is not set
CONFIG_40x=y
# CONFIG_44x is not set
# CONFIG_E200 is not set
CONFIG_4xx=y
# CONFIG_PPC_MM_SLICES is not set
CONFIG_NOT_COHERENT_CACHE=y
CONFIG_PPC32=y
CONFIG_WORD_SIZE=32
CONFIG_PPC_MERGE=y
CONFIG_MMU=y
CONFIG_GENERIC_CMOS_UPDATE=y
CONFIG_GENERIC_TIME=y
CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_IRQ_PER_CPU=y
CONFIG_RWSEM_XCHGADD_ALGORITHM=y
CONFIG_ARCH_HAS_ILOG2_U32=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_GENERIC_FIND_NEXT_BIT=y
# CONFIG_ARCH_NO_VIRT_TO_BUS is not set
CONFIG_PPC=y
CONFIG_EARLY_PRINTK=y
CONFIG_GENERIC_NVRAM=y
CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
CONFIG_ARCH_MAY_HAVE_PC_FDC=y
CONFIG_PPC_OF=y
CONFIG_OF=y
# CONFIG_PPC_UDBG_16550 is not set
# CONFIG_GENERIC_TBSYNC is not set
CONFIG_AUDIT_ARCH=y
CONFIG_GENERIC_BUG=y
# CONFIG_DEFAULT_UIMAGE is not set
CONFIG_PPC_DCR_NATIVE=y
# CONFIG_PPC_DCR_MMIO is not set
CONFIG_PPC_DCR=y
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
#
# General setup
#
CONFIG_EXPERIMENTAL=y
CONFIG_BROKEN_ON_SMP=y
CONFIG_INIT_ENV_ARG_LIMIT=32
CONFIG_LOCALVERSION=""
CONFIG_LOCALVERSION_AUTO=y
CONFIG_SWAP=y
CONFIG_SYSVIPC=y
CONFIG_SYSVIPC_SYSCTL=y
CONFIG_POSIX_MQUEUE=y
# CONFIG_BSD_PROCESS_ACCT is not set
# CONFIG_TASKSTATS is not set
# CONFIG_USER_NS is not set
# CONFIG_AUDIT is not set
# CONFIG_IKCONFIG is not set
CONFIG_LOG_BUF_SHIFT=14
CONFIG_SYSFS_DEPRECATED=y
# CONFIG_RELAY is not set
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_SYSCTL=y
CONFIG_EMBEDDED=y
CONFIG_SYSCTL_SYSCALL=y
CONFIG_KALLSYMS=y
CONFIG_KALLSYMS_ALL=y
CONFIG_KALLSYMS_EXTRA_PASS=y
CONFIG_HOTPLUG=y
CONFIG_PRINTK=y
CONFIG_BUG=y
CONFIG_ELF_CORE=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_ANON_INODES=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_EVENTFD=y
CONFIG_SHMEM=y
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_SLAB=y
# CONFIG_SLUB is not set
# CONFIG_SLOB is not set
CONFIG_RT_MUTEXES=y
# CONFIG_TINY_SHMEM is not set
CONFIG_BASE_SMALL=0
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_MODULE_FORCE_UNLOAD is not set
# CONFIG_MODVERSIONS is not set
# CONFIG_MODULE_SRCVERSION_ALL is not set
CONFIG_KMOD=y
CONFIG_BLOCK=y
CONFIG_LBD=y
# CONFIG_BLK_DEV_IO_TRACE is not set
# CONFIG_LSF is not set
# CONFIG_BLK_DEV_BSG is not set
#
# IO Schedulers
#
CONFIG_IOSCHED_NOOP=y
CONFIG_IOSCHED_AS=y
CONFIG_IOSCHED_DEADLINE=y
CONFIG_IOSCHED_CFQ=y
CONFIG_DEFAULT_AS=y
# CONFIG_DEFAULT_DEADLINE is not set
# CONFIG_DEFAULT_CFQ is not set
# CONFIG_DEFAULT_NOOP is not set
CONFIG_DEFAULT_IOSCHED="anticipatory"
#
# Platform support
#
# CONFIG_PPC_MPC52xx is not set
# CONFIG_PPC_MPC5200 is not set
# CONFIG_PPC_CELL is not set
# CONFIG_PPC_CELL_NATIVE is not set
# CONFIG_PQ2ADS is not set
CONFIG_KILAUEA=y
# CONFIG_WALNUT is not set
# CONFIG_XILINX_VIRTEX_GENERIC_BOARD is not set
# CONFIG_MPIC is not set
# CONFIG_MPIC_WEIRD is not set
# CONFIG_PPC_I8259 is not set
# CONFIG_PPC_RTAS is not set
# CONFIG_MMIO_NVRAM is not set
# CONFIG_PPC_MPC106 is not set
# CONFIG_PPC_970_NAP is not set
# CONFIG_PPC_INDIRECT_IO is not set
# CONFIG_GENERIC_IOMAP is not set
# CONFIG_CPU_FREQ is not set
# CONFIG_CPM2 is not set
# CONFIG_FSL_ULI1575 is not set
#
# Kernel options
#
# CONFIG_HIGHMEM is not set
# CONFIG_TICK_ONESHOT is not set
# CONFIG_NO_HZ is not set
# CONFIG_HIGH_RES_TIMERS is not set
# CONFIG_HZ_100 is not set
CONFIG_HZ_250=y
# CONFIG_HZ_300 is not set
# CONFIG_HZ_1000 is not set
CONFIG_HZ=250
CONFIG_PREEMPT_NONE=y
# CONFIG_PREEMPT_VOLUNTARY is not set
# CONFIG_PREEMPT is not set
CONFIG_BINFMT_ELF=y
# CONFIG_BINFMT_MISC is not set
# CONFIG_MATH_EMULATION is not set
CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
CONFIG_ARCH_FLATMEM_ENABLE=y
CONFIG_ARCH_POPULATES_NODE_MAP=y
CONFIG_SELECT_MEMORY_MODEL=y
CONFIG_FLATMEM_MANUAL=y
# CONFIG_DISCONTIGMEM_MANUAL is not set
# CONFIG_SPARSEMEM_MANUAL is not set
CONFIG_FLATMEM=y
CONFIG_FLAT_NODE_MEM_MAP=y
# CONFIG_SPARSEMEM_STATIC is not set
CONFIG_SPLIT_PTLOCK_CPUS=4
# CONFIG_RESOURCES_64BIT is not set
CONFIG_ZONE_DMA_FLAG=1
CONFIG_BOUNCE=y
CONFIG_VIRT_TO_BUS=y
CONFIG_PROC_DEVICETREE=y
# CONFIG_CMDLINE_BOOL is not set
# CONFIG_PM is not set
CONFIG_SUSPEND_UP_POSSIBLE=y
CONFIG_HIBERNATION_UP_POSSIBLE=y
CONFIG_SECCOMP=y
CONFIG_WANT_DEVICE_TREE=y
CONFIG_DEVICE_TREE="kilauea.dts"
CONFIG_ISA_DMA_API=y
#
# Bus options
#
CONFIG_ZONE_DMA=y
# CONFIG_PCI is not set
# CONFIG_PCI_DOMAINS is not set
# CONFIG_PCI_SYSCALL is not set
# CONFIG_ARCH_SUPPORTS_MSI is not set
#
# PCCARD (PCMCIA/CardBus) support
#
# CONFIG_PCCARD is not set
#
# Advanced setup
#
# CONFIG_ADVANCED_OPTIONS is not set
#
# Default settings for advanced configuration options are used
#
CONFIG_HIGHMEM_START=0xfe000000
CONFIG_LOWMEM_SIZE=0x30000000
CONFIG_KERNEL_START=0xc0000000
CONFIG_TASK_SIZE=0x80000000
CONFIG_CONSISTENT_START=0xff100000
CONFIG_CONSISTENT_SIZE=0x00200000
CONFIG_BOOT_LOAD=0x00400000
#
# Networking
#
CONFIG_NET=y
#
# Networking options
#
CONFIG_PACKET=y
# CONFIG_PACKET_MMAP is not set
CONFIG_UNIX=y
# CONFIG_NET_KEY is not set
CONFIG_INET=y
# CONFIG_IP_MULTICAST is not set
# CONFIG_IP_ADVANCED_ROUTER is not set
CONFIG_IP_FIB_HASH=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
# CONFIG_IP_PNP_RARP is not set
# CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE is not set
# CONFIG_ARPD is not set
# CONFIG_SYN_COOKIES is not set
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
# CONFIG_INET_XFRM_TUNNEL is not set
# CONFIG_INET_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
CONFIG_INET_DIAG=y
CONFIG_INET_TCP_DIAG=y
# CONFIG_TCP_CONG_ADVANCED is not set
CONFIG_TCP_CONG_CUBIC=y
CONFIG_DEFAULT_TCP_CONG="cubic"
# CONFIG_TCP_MD5SIG is not set
# CONFIG_IPV6 is not set
# CONFIG_INET6_XFRM_TUNNEL is not set
# CONFIG_INET6_TUNNEL is not set
# CONFIG_NETWORK_SECMARK is not set
# CONFIG_NETFILTER is not set
# CONFIG_IP_DCCP is not set
# CONFIG_IP_SCTP is not set
# CONFIG_TIPC is not set
# CONFIG_ATM is not set
# CONFIG_BRIDGE is not set
# CONFIG_VLAN_8021Q is not set
# CONFIG_DECNET is not set
# CONFIG_LLC2 is not set
# CONFIG_IPX is not set
# CONFIG_ATALK is not set
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_ECONET is not set
# CONFIG_WAN_ROUTER is not set
#
# QoS and/or fair queueing
#
# CONFIG_NET_SCHED is not set
#
# Network testing
#
# CONFIG_NET_PKTGEN is not set
# CONFIG_HAMRADIO is not set
# CONFIG_IRDA is not set
# CONFIG_BT is not set
# CONFIG_AF_RXRPC is not set
#
# Wireless
#
# CONFIG_CFG80211 is not set
# CONFIG_WIRELESS_EXT is not set
# CONFIG_MAC80211 is not set
# CONFIG_IEEE80211 is not set
# CONFIG_RFKILL is not set
# CONFIG_NET_9P is not set
#
# Device Drivers
#
#
# Generic Driver Options
#
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y
CONFIG_FW_LOADER=y
# CONFIG_DEBUG_DRIVER is not set
# CONFIG_DEBUG_DEVRES is not set
# CONFIG_SYS_HYPERVISOR is not set
CONFIG_CONNECTOR=y
CONFIG_PROC_EVENTS=y
CONFIG_MTD=y
# CONFIG_MTD_DEBUG is not set
# CONFIG_MTD_CONCAT is not set
CONFIG_MTD_PARTITIONS=y
# CONFIG_MTD_REDBOOT_PARTS is not set
CONFIG_MTD_CMDLINE_PARTS=y
#
# User Modules And Translation Layers
#
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLKDEVS=m
CONFIG_MTD_BLOCK=m
# CONFIG_MTD_BLOCK_RO is not set
# CONFIG_FTL is not set
# CONFIG_NFTL is not set
# CONFIG_INFTL is not set
# CONFIG_RFD_FTL is not set
# CONFIG_SSFDC is not set
#
# RAM/ROM/Flash chip drivers
#
CONFIG_MTD_CFI=y
CONFIG_MTD_JEDECPROBE=y
CONFIG_MTD_GEN_PROBE=y
# CONFIG_MTD_CFI_ADV_OPTIONS is not set
CONFIG_MTD_MAP_BANK_WIDTH_1=y
CONFIG_MTD_MAP_BANK_WIDTH_2=y
CONFIG_MTD_MAP_BANK_WIDTH_4=y
# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
CONFIG_MTD_CFI_I1=y
CONFIG_MTD_CFI_I2=y
# CONFIG_MTD_CFI_I4 is not set
# CONFIG_MTD_CFI_I8 is not set
# CONFIG_MTD_CFI_INTELEXT is not set
CONFIG_MTD_CFI_AMDSTD=y
# CONFIG_MTD_CFI_STAA is not set
CONFIG_MTD_CFI_UTIL=y
# CONFIG_MTD_RAM is not set
# CONFIG_MTD_ROM is not set
# CONFIG_MTD_ABSENT is not set
#
# Mapping drivers for chip access
#
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
# CONFIG_MTD_PHYSMAP is not set
CONFIG_MTD_PHYSMAP_OF=y
# CONFIG_MTD_PLATRAM is not set
#
# Self-contained MTD device drivers
#
# CONFIG_MTD_SLRAM is not set
# CONFIG_MTD_PHRAM is not set
# CONFIG_MTD_MTDRAM is not set
# CONFIG_MTD_BLOCK2MTD is not set
#
# Disk-On-Chip Device Drivers
#
# CONFIG_MTD_DOC2000 is not set
# CONFIG_MTD_DOC2001 is not set
# CONFIG_MTD_DOC2001PLUS is not set
# CONFIG_MTD_NAND is not set
# CONFIG_MTD_ONENAND is not set
#
# UBI - Unsorted block images
#
# CONFIG_MTD_UBI is not set
CONFIG_OF_DEVICE=y
# CONFIG_PARPORT is not set
CONFIG_BLK_DEV=y
# CONFIG_BLK_DEV_FD is not set
# CONFIG_BLK_DEV_COW_COMMON is not set
# CONFIG_BLK_DEV_LOOP is not set
# CONFIG_BLK_DEV_NBD is not set
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=16
CONFIG_BLK_DEV_RAM_SIZE=35000
CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
# CONFIG_CDROM_PKTCDVD is not set
# CONFIG_ATA_OVER_ETH is not set
# CONFIG_XILINX_SYSACE is not set
# CONFIG_MISC_DEVICES is not set
# CONFIG_IDE is not set
#
# SCSI device support
#
# CONFIG_RAID_ATTRS is not set
# CONFIG_SCSI is not set
# CONFIG_SCSI_DMA is not set
# CONFIG_SCSI_NETLINK is not set
# CONFIG_ATA is not set
# CONFIG_MD is not set
# CONFIG_MACINTOSH_DRIVERS is not set
CONFIG_NETDEVICES=y
# CONFIG_NETDEVICES_MULTIQUEUE is not set
# CONFIG_DUMMY is not set
# CONFIG_BONDING is not set
# CONFIG_MACVLAN is not set
# CONFIG_EQUALIZER is not set
# CONFIG_TUN is not set
# CONFIG_NET_ETHERNET is not set
# CONFIG_NETDEV_1000 is not set
# CONFIG_NETDEV_10000 is not set
#
# Wireless LAN
#
# CONFIG_WLAN_PRE80211 is not set
# CONFIG_WLAN_80211 is not set
# CONFIG_WAN is not set
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
# CONFIG_SHAPER is not set
# CONFIG_NETCONSOLE is not set
# CONFIG_NETPOLL is not set
# CONFIG_NET_POLL_CONTROLLER is not set
# CONFIG_ISDN is not set
# CONFIG_PHONE is not set
#
# Input device support
#
# CONFIG_INPUT is not set
#
# Hardware I/O ports
#
# CONFIG_SERIO is not set
# CONFIG_GAMEPORT is not set
#
# Character devices
#
# CONFIG_VT is not set
# CONFIG_SERIAL_NONSTANDARD is not set
#
# Serial drivers
#
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_NR_UARTS=4
CONFIG_SERIAL_8250_RUNTIME_UARTS=4
CONFIG_SERIAL_8250_EXTENDED=y
# CONFIG_SERIAL_8250_MANY_PORTS is not set
CONFIG_SERIAL_8250_SHARE_IRQ=y
# CONFIG_SERIAL_8250_DETECT_IRQ is not set
# CONFIG_SERIAL_8250_RSA is not set
#
# Non-8250 serial port support
#
# CONFIG_SERIAL_UARTLITE is not set
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_UNIX98_PTYS=y
CONFIG_LEGACY_PTYS=y
CONFIG_LEGACY_PTY_COUNT=256
# CONFIG_IPMI_HANDLER is not set
# CONFIG_WATCHDOG is not set
# CONFIG_HW_RANDOM is not set
# CONFIG_NVRAM is not set
# CONFIG_GEN_RTC is not set
# CONFIG_R3964 is not set
# CONFIG_RAW_DRIVER is not set
# CONFIG_TCG_TPM is not set
# CONFIG_I2C is not set
#
# SPI support
#
# CONFIG_SPI is not set
# CONFIG_SPI_MASTER is not set
# CONFIG_W1 is not set
# CONFIG_POWER_SUPPLY is not set
# CONFIG_HWMON is not set
#
# Multifunction device drivers
#
# CONFIG_MFD_SM501 is not set
#
# Multimedia devices
#
# CONFIG_VIDEO_DEV is not set
# CONFIG_DVB_CORE is not set
# CONFIG_DAB is not set
#
# Graphics support
#
# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
#
# Display device support
#
# CONFIG_DISPLAY_SUPPORT is not set
# CONFIG_VGASTATE is not set
# CONFIG_VIDEO_OUTPUT_CONTROL is not set
# CONFIG_FB is not set
# CONFIG_FB_IBM_GXT4500 is not set
#
# Sound
#
# CONFIG_SOUND is not set
# CONFIG_USB_SUPPORT is not set
# CONFIG_MMC is not set
# CONFIG_NEW_LEDS is not set
# CONFIG_EDAC is not set
# CONFIG_RTC_CLASS is not set
#
# DMA Engine support
#
# CONFIG_DMA_ENGINE is not set
#
# DMA Clients
#
#
# DMA Devices
#
#
# Userspace I/O
#
# CONFIG_UIO is not set
#
# File systems
#
CONFIG_EXT2_FS=y
# CONFIG_EXT2_FS_XATTR is not set
# CONFIG_EXT2_FS_XIP is not set
# CONFIG_EXT3_FS is not set
# CONFIG_EXT4DEV_FS is not set
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
# CONFIG_FS_POSIX_ACL is not set
# CONFIG_XFS_FS is not set
# CONFIG_GFS2_FS is not set
# CONFIG_OCFS2_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_ROMFS_FS is not set
CONFIG_INOTIFY=y
CONFIG_INOTIFY_USER=y
# CONFIG_QUOTA is not set
CONFIG_DNOTIFY=y
# CONFIG_AUTOFS_FS is not set
# CONFIG_AUTOFS4_FS is not set
# CONFIG_FUSE_FS is not set
#
# CD-ROM/DVD Filesystems
#
# CONFIG_ISO9660_FS is not set
# CONFIG_UDF_FS is not set
#
# DOS/FAT/NT Filesystems
#
# CONFIG_MSDOS_FS is not set
# CONFIG_VFAT_FS is not set
# CONFIG_NTFS_FS is not set
#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
CONFIG_PROC_KCORE=y
CONFIG_PROC_SYSCTL=y
CONFIG_SYSFS=y
CONFIG_TMPFS=y
# CONFIG_TMPFS_POSIX_ACL is not set
# CONFIG_HUGETLB_PAGE is not set
CONFIG_RAMFS=y
# CONFIG_CONFIGFS_FS is not set
#
# Miscellaneous filesystems
#
# CONFIG_ADFS_FS is not set
# CONFIG_AFFS_FS is not set
# CONFIG_HFS_FS is not set
# CONFIG_HFSPLUS_FS is not set
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
# CONFIG_JFFS2_FS is not set
CONFIG_CRAMFS=y
# CONFIG_VXFS_FS is not set
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
#
# Network File Systems
#
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
# CONFIG_NFS_V3_ACL is not set
# CONFIG_NFS_V4 is not set
# CONFIG_NFS_DIRECTIO is not set
# CONFIG_NFSD is not set
CONFIG_ROOT_NFS=y
CONFIG_LOCKD=y
CONFIG_LOCKD_V4=y
CONFIG_NFS_COMMON=y
CONFIG_SUNRPC=y
# CONFIG_SUNRPC_BIND34 is not set
# CONFIG_RPCSEC_GSS_KRB5 is not set
# CONFIG_RPCSEC_GSS_SPKM3 is not set
# CONFIG_SMB_FS is not set
# CONFIG_CIFS is not set
# CONFIG_NCP_FS is not set
# CONFIG_CODA_FS is not set
# CONFIG_AFS_FS is not set
#
# Partition Types
#
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_MSDOS_PARTITION=y
#
# Native Language Support
#
# CONFIG_NLS is not set
#
# Distributed Lock Manager
#
# CONFIG_DLM is not set
# CONFIG_UCC_SLOW is not set
#
# Library routines
#
CONFIG_BITREVERSE=y
# CONFIG_CRC_CCITT is not set
# CONFIG_CRC16 is not set
# CONFIG_CRC_ITU_T is not set
CONFIG_CRC32=y
# CONFIG_CRC7 is not set
# CONFIG_LIBCRC32C is not set
CONFIG_ZLIB_INFLATE=y
CONFIG_PLIST=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_DMA=y
#
# Instrumentation Support
#
# CONFIG_PROFILING is not set
#
# Kernel hacking
#
# CONFIG_PRINTK_TIME is not set
CONFIG_ENABLE_MUST_CHECK=y
CONFIG_MAGIC_SYSRQ=y
# CONFIG_UNUSED_SYMBOLS is not set
# CONFIG_DEBUG_FS is not set
# CONFIG_HEADERS_CHECK is not set
CONFIG_DEBUG_KERNEL=y
# CONFIG_DEBUG_SHIRQ is not set
CONFIG_DETECT_SOFTLOCKUP=y
CONFIG_SCHED_DEBUG=y
# CONFIG_SCHEDSTATS is not set
# CONFIG_TIMER_STATS is not set
# CONFIG_DEBUG_SLAB is not set
# CONFIG_DEBUG_RT_MUTEXES is not set
# CONFIG_RT_MUTEX_TESTER is not set
# CONFIG_DEBUG_SPINLOCK is not set
# CONFIG_DEBUG_MUTEXES is not set
# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
# CONFIG_DEBUG_KOBJECT is not set
CONFIG_DEBUG_BUGVERBOSE=y
# CONFIG_DEBUG_INFO is not set
# CONFIG_DEBUG_VM is not set
# CONFIG_DEBUG_LIST is not set
CONFIG_FORCED_INLINING=y
# CONFIG_RCU_TORTURE_TEST is not set
# CONFIG_FAULT_INJECTION is not set
# CONFIG_DEBUG_STACKOVERFLOW is not set
# CONFIG_DEBUG_STACK_USAGE is not set
# CONFIG_DEBUG_PAGEALLOC is not set
# CONFIG_DEBUGGER is not set
# CONFIG_BDI_SWITCH is not set
# CONFIG_PPC_EARLY_DEBUG is not set
#
# Security options
#
# CONFIG_KEYS is not set
# CONFIG_SECURITY is not set
CONFIG_CRYPTO=y
CONFIG_CRYPTO_ALGAPI=y
CONFIG_CRYPTO_BLKCIPHER=y
CONFIG_CRYPTO_MANAGER=y
# CONFIG_CRYPTO_HMAC is not set
# CONFIG_CRYPTO_XCBC is not set
# CONFIG_CRYPTO_NULL is not set
# CONFIG_CRYPTO_MD4 is not set
CONFIG_CRYPTO_MD5=y
# CONFIG_CRYPTO_SHA1 is not set
# CONFIG_CRYPTO_SHA256 is not set
# CONFIG_CRYPTO_SHA512 is not set
# CONFIG_CRYPTO_WP512 is not set
# CONFIG_CRYPTO_TGR192 is not set
# CONFIG_CRYPTO_GF128MUL is not set
CONFIG_CRYPTO_ECB=y
CONFIG_CRYPTO_CBC=y
CONFIG_CRYPTO_PCBC=y
# CONFIG_CRYPTO_LRW is not set
# CONFIG_CRYPTO_CRYPTD is not set
CONFIG_CRYPTO_DES=y
# CONFIG_CRYPTO_FCRYPT is not set
# CONFIG_CRYPTO_BLOWFISH is not set
# CONFIG_CRYPTO_TWOFISH is not set
# CONFIG_CRYPTO_SERPENT is not set
# CONFIG_CRYPTO_AES is not set
# CONFIG_CRYPTO_CAST5 is not set
# CONFIG_CRYPTO_CAST6 is not set
# CONFIG_CRYPTO_TEA is not set
# CONFIG_CRYPTO_ARC4 is not set
# CONFIG_CRYPTO_KHAZAD is not set
# CONFIG_CRYPTO_ANUBIS is not set
# CONFIG_CRYPTO_DEFLATE is not set
# CONFIG_CRYPTO_MICHAEL_MIC is not set
# CONFIG_CRYPTO_CRC32C is not set
# CONFIG_CRYPTO_CAMELLIA is not set
# CONFIG_CRYPTO_TEST is not set
CONFIG_CRYPTO_HW=y
# CONFIG_PPC_CLOCK is not set

248
arch/powerpc/configs/mpc8272_ads_defconfig
View File

@ -1,7 +1,7 @@
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.23-rc4
# Tue Aug 28 21:24:39 2007
# Wed Sep 5 12:43:23 2007
#
# CONFIG_PPC64 is not set
@ -52,7 +52,7 @@ CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
# CONFIG_EXPERIMENTAL is not set
CONFIG_BROKEN_ON_SMP=y
CONFIG_INIT_ENV_ARG_LIMIT=32
CONFIG_LOCALVERSION="powerpc8272"
CONFIG_LOCALVERSION=""
CONFIG_LOCALVERSION_AUTO=y
CONFIG_SWAP=y
CONFIG_SYSVIPC=y
@ -71,7 +71,7 @@ CONFIG_EMBEDDED=y
CONFIG_SYSCTL_SYSCALL=y
CONFIG_KALLSYMS=y
CONFIG_KALLSYMS_ALL=y
CONFIG_KALLSYMS_EXTRA_PASS=y
# CONFIG_KALLSYMS_EXTRA_PASS is not set
CONFIG_HOTPLUG=y
CONFIG_PRINTK=y
CONFIG_BUG=y
@ -122,10 +122,11 @@ CONFIG_PPC_82xx=y
# CONFIG_PPC_MPC5200 is not set
# CONFIG_PPC_CELL is not set
# CONFIG_PPC_CELL_NATIVE is not set
CONFIG_MPC82xx_ADS=y
CONFIG_MPC8272_ADS=y
CONFIG_PQ2ADS=y
CONFIG_8260=y
CONFIG_8272=y
CONFIG_PQ2_ADS_PCI_PIC=y
# CONFIG_MPIC is not set
# CONFIG_MPIC_WEIRD is not set
# CONFIG_PPC_I8259 is not set
@ -137,7 +138,9 @@ CONFIG_8272=y
# CONFIG_GENERIC_IOMAP is not set
# CONFIG_CPU_FREQ is not set
CONFIG_CPM2=y
CONFIG_PPC_CPM_NEW_BINDING=y
# CONFIG_FSL_ULI1575 is not set
CONFIG_CPM=y
#
# Kernel options
@ -168,18 +171,25 @@ CONFIG_PROC_DEVICETREE=y
# CONFIG_CMDLINE_BOOL is not set
# CONFIG_PM is not set
CONFIG_SECCOMP=y
# CONFIG_WANT_DEVICE_TREE is not set
CONFIG_WANT_DEVICE_TREE=y
# CONFIG_BUILD_RAW_IMAGE is not set
CONFIG_DEVICE_TREE="mpc8272ads.dts"
CONFIG_ISA_DMA_API=y
#
# Bus options
#
CONFIG_ZONE_DMA=y
CONFIG_PPC_INDIRECT_PCI=y
CONFIG_FSL_SOC=y
# CONFIG_PCI is not set
# CONFIG_PCI_DOMAINS is not set
# CONFIG_PCI_SYSCALL is not set
# CONFIG_ARCH_SUPPORTS_MSI is not set
CONFIG_PCI=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_SYSCALL=y
CONFIG_PCI_8260=y
# CONFIG_PCIEPORTBUS is not set
CONFIG_ARCH_SUPPORTS_MSI=y
# CONFIG_PCI_MSI is not set
# CONFIG_PCI_DEBUG is not set
#
# PCCARD (PCMCIA/CardBus) support
@ -313,43 +323,101 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
# CONFIG_DEBUG_DEVRES is not set
# CONFIG_SYS_HYPERVISOR is not set
# CONFIG_CONNECTOR is not set
# CONFIG_MTD is not set
CONFIG_MTD=y
# CONFIG_MTD_DEBUG is not set
# CONFIG_MTD_CONCAT is not set
# CONFIG_MTD_PARTITIONS is not set
#
# User Modules And Translation Layers
#
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLKDEVS=y
CONFIG_MTD_BLOCK=y
# CONFIG_FTL is not set
# CONFIG_NFTL is not set
# CONFIG_INFTL is not set
# CONFIG_RFD_FTL is not set
# CONFIG_SSFDC is not set
#
# RAM/ROM/Flash chip drivers
#
# CONFIG_MTD_CFI is not set
CONFIG_MTD_JEDECPROBE=y
CONFIG_MTD_GEN_PROBE=y
CONFIG_MTD_CFI_ADV_OPTIONS=y
CONFIG_MTD_CFI_NOSWAP=y
# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
CONFIG_MTD_CFI_GEOMETRY=y
# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
# CONFIG_MTD_MAP_BANK_WIDTH_2 is not set
CONFIG_MTD_MAP_BANK_WIDTH_4=y
# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
# CONFIG_MTD_CFI_I1 is not set
# CONFIG_MTD_CFI_I2 is not set
CONFIG_MTD_CFI_I4=y
# CONFIG_MTD_CFI_I8 is not set
# CONFIG_MTD_OTP is not set
CONFIG_MTD_CFI_INTELEXT=y
# CONFIG_MTD_CFI_AMDSTD is not set
# CONFIG_MTD_CFI_STAA is not set
CONFIG_MTD_CFI_UTIL=y
# CONFIG_MTD_RAM is not set
# CONFIG_MTD_ROM is not set
# CONFIG_MTD_ABSENT is not set
#
# Mapping drivers for chip access
#
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
# CONFIG_MTD_PHYSMAP is not set
CONFIG_MTD_PHYSMAP_OF=y
# CONFIG_MTD_SBC8240 is not set
# CONFIG_MTD_PLATRAM is not set
#
# Self-contained MTD device drivers
#
# CONFIG_MTD_PMC551 is not set
# CONFIG_MTD_SLRAM is not set
# CONFIG_MTD_PHRAM is not set
# CONFIG_MTD_MTDRAM is not set
# CONFIG_MTD_BLOCK2MTD is not set
#
# Disk-On-Chip Device Drivers
#
# CONFIG_MTD_DOC2000 is not set
# CONFIG_MTD_DOC2001 is not set
# CONFIG_MTD_DOC2001PLUS is not set
# CONFIG_MTD_NAND is not set
# CONFIG_MTD_ONENAND is not set
#
# UBI - Unsorted block images
#
# CONFIG_MTD_UBI is not set
CONFIG_OF_DEVICE=y
# CONFIG_PARPORT is not set
CONFIG_BLK_DEV=y
# CONFIG_BLK_DEV_FD is not set
# CONFIG_BLK_CPQ_DA is not set
# CONFIG_BLK_CPQ_CISS_DA is not set
# CONFIG_BLK_DEV_DAC960 is not set
# CONFIG_BLK_DEV_COW_COMMON is not set
CONFIG_BLK_DEV_LOOP=y
# CONFIG_BLK_DEV_CRYPTOLOOP is not set
# CONFIG_BLK_DEV_NBD is not set
# CONFIG_BLK_DEV_SX8 is not set
# CONFIG_BLK_DEV_RAM is not set
# CONFIG_CDROM_PKTCDVD is not set
# CONFIG_ATA_OVER_ETH is not set
CONFIG_MISC_DEVICES=y
# CONFIG_EEPROM_93CX6 is not set
CONFIG_IDE=y
CONFIG_IDE_MAX_HWIFS=4
CONFIG_BLK_DEV_IDE=y
#
# Please see Documentation/ide.txt for help/info on IDE drives
#
# CONFIG_BLK_DEV_IDE_SATA is not set
CONFIG_BLK_DEV_IDEDISK=y
# CONFIG_IDEDISK_MULTI_MODE is not set
# CONFIG_BLK_DEV_IDECD is not set
# CONFIG_BLK_DEV_IDEFLOPPY is not set
# CONFIG_IDE_TASK_IOCTL is not set
CONFIG_IDE_PROC_FS=y
#
# IDE chipset support/bugfixes
#
# CONFIG_IDE_GENERIC is not set
# CONFIG_IDEPCI_PCIBUS_ORDER is not set
# CONFIG_IDE_ARM is not set
# CONFIG_BLK_DEV_IDEDMA is not set
# CONFIG_BLK_DEV_HD is not set
# CONFIG_MISC_DEVICES is not set
# CONFIG_IDE is not set
#
# SCSI device support
@ -360,6 +428,21 @@ CONFIG_IDE_PROC_FS=y
# CONFIG_SCSI_NETLINK is not set
# CONFIG_ATA is not set
# CONFIG_MD is not set
#
# Fusion MPT device support
#
# CONFIG_FUSION is not set
#
# IEEE 1394 (FireWire) support
#
#
# An alternative FireWire stack is available with EXPERIMENTAL=y
#
# CONFIG_IEEE1394 is not set
# CONFIG_I2O is not set
# CONFIG_MACINTOSH_DRIVERS is not set
CONFIG_NETDEVICES=y
# CONFIG_NETDEVICES_MULTIQUEUE is not set
@ -367,6 +450,7 @@ CONFIG_NETDEVICES=y
# CONFIG_BONDING is not set
# CONFIG_EQUALIZER is not set
CONFIG_TUN=y
# CONFIG_ARCNET is not set
CONFIG_PHYLIB=y
#
@ -382,13 +466,42 @@ CONFIG_DAVICOM_PHY=y
# CONFIG_BROADCOM_PHY is not set
# CONFIG_ICPLUS_PHY is not set
# CONFIG_FIXED_PHY is not set
CONFIG_MDIO_BITBANG=y
CONFIG_NET_ETHERNET=y
CONFIG_MII=y
# CONFIG_HAPPYMEAL is not set
# CONFIG_SUNGEM is not set
# CONFIG_CASSINI is not set
# CONFIG_NET_VENDOR_3COM is not set
# CONFIG_NET_TULIP is not set
# CONFIG_HP100 is not set
# CONFIG_NET_PCI is not set
CONFIG_FS_ENET=y
# CONFIG_FS_ENET_HAS_SCC is not set
CONFIG_FS_ENET_HAS_FCC=y
CONFIG_NETDEV_1000=y
# CONFIG_ACENIC is not set
# CONFIG_DL2K is not set
# CONFIG_E1000 is not set
# CONFIG_NS83820 is not set
# CONFIG_HAMACHI is not set
# CONFIG_R8169 is not set
# CONFIG_SIS190 is not set
# CONFIG_SKGE is not set
# CONFIG_SKY2 is not set
# CONFIG_VIA_VELOCITY is not set
# CONFIG_TIGON3 is not set
# CONFIG_BNX2 is not set
# CONFIG_QLA3XXX is not set
CONFIG_NETDEV_10000=y
# CONFIG_CHELSIO_T1 is not set
# CONFIG_CHELSIO_T3 is not set
# CONFIG_IXGB is not set
# CONFIG_S2IO is not set
# CONFIG_MYRI10GE is not set
# CONFIG_NETXEN_NIC is not set
# CONFIG_MLX4_CORE is not set
# CONFIG_TR is not set
#
# Wireless LAN
@ -396,6 +509,7 @@ CONFIG_NETDEV_10000=y
# CONFIG_WLAN_PRE80211 is not set
# CONFIG_WLAN_80211 is not set
# CONFIG_WAN is not set
# CONFIG_FDDI is not set
CONFIG_PPP=y
# CONFIG_PPP_FILTER is not set
CONFIG_PPP_ASYNC=y
@ -459,6 +573,7 @@ CONFIG_MOUSE_PS2_TRACKPOINT=y
CONFIG_SERIO=y
# CONFIG_SERIO_I8042 is not set
CONFIG_SERIO_SERPORT=y
# CONFIG_SERIO_PCIPS2 is not set
CONFIG_SERIO_LIBPS2=y
# CONFIG_SERIO_RAW is not set
# CONFIG_GAMEPORT is not set
@ -488,6 +603,7 @@ CONFIG_SERIAL_CPM_SCC1=y
CONFIG_SERIAL_CPM_SCC4=y
# CONFIG_SERIAL_CPM_SMC1 is not set
# CONFIG_SERIAL_CPM_SMC2 is not set
# CONFIG_SERIAL_JSM is not set
CONFIG_UNIX98_PTYS=y
CONFIG_LEGACY_PTYS=y
CONFIG_LEGACY_PTY_COUNT=256
@ -497,7 +613,11 @@ CONFIG_HW_RANDOM=y
# CONFIG_NVRAM is not set
# CONFIG_GEN_RTC is not set
# CONFIG_R3964 is not set
# CONFIG_APPLICOM is not set
# CONFIG_AGP is not set
# CONFIG_DRM is not set
# CONFIG_RAW_DRIVER is not set
CONFIG_DEVPORT=y
# CONFIG_I2C is not set
#
@ -531,7 +651,7 @@ CONFIG_DAB=y
#
# CONFIG_DISPLAY_SUPPORT is not set
# CONFIG_VGASTATE is not set
CONFIG_VIDEO_OUTPUT_CONTROL=y
# CONFIG_VIDEO_OUTPUT_CONTROL is not set
# CONFIG_FB is not set
# CONFIG_FB_IBM_GXT4500 is not set
@ -539,45 +659,11 @@ CONFIG_VIDEO_OUTPUT_CONTROL=y
# Sound
#
# CONFIG_SOUND is not set
CONFIG_HID_SUPPORT=y
CONFIG_HID=y
# CONFIG_HID_DEBUG is not set
CONFIG_USB_SUPPORT=y
# CONFIG_USB_ARCH_HAS_HCD is not set
# CONFIG_USB_ARCH_HAS_OHCI is not set
# CONFIG_USB_ARCH_HAS_EHCI is not set
#
# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
#
#
# USB Gadget Support
#
CONFIG_USB_GADGET=y
# CONFIG_USB_GADGET_DEBUG_FILES is not set
CONFIG_USB_GADGET_SELECTED=y
# CONFIG_USB_GADGET_AMD5536UDC is not set
# CONFIG_USB_GADGET_FSL_USB2 is not set
# CONFIG_USB_GADGET_NET2280 is not set
# CONFIG_USB_GADGET_PXA2XX is not set
CONFIG_USB_GADGET_M66592=y
CONFIG_USB_M66592=y
# CONFIG_USB_GADGET_GOKU is not set
# CONFIG_USB_GADGET_LH7A40X is not set
# CONFIG_USB_GADGET_OMAP is not set
# CONFIG_USB_GADGET_S3C2410 is not set
# CONFIG_USB_GADGET_AT91 is not set
# CONFIG_USB_GADGET_DUMMY_HCD is not set
CONFIG_USB_GADGET_DUALSPEED=y
# CONFIG_USB_ZERO is not set
CONFIG_USB_ETH=y
# CONFIG_USB_GADGETFS is not set
# CONFIG_USB_FILE_STORAGE is not set
# CONFIG_USB_G_SERIAL is not set
# CONFIG_USB_MIDI_GADGET is not set
# CONFIG_HID_SUPPORT is not set
# CONFIG_USB_SUPPORT is not set
# CONFIG_MMC is not set
# CONFIG_NEW_LEDS is not set
# CONFIG_INFINIBAND is not set
# CONFIG_RTC_CLASS is not set
#
@ -614,11 +700,7 @@ CONFIG_FS_MBCACHE=y
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
CONFIG_FS_POSIX_ACL=y
CONFIG_XFS_FS=y
# CONFIG_XFS_QUOTA is not set
# CONFIG_XFS_SECURITY is not set
# CONFIG_XFS_POSIX_ACL is not set
# CONFIG_XFS_RT is not set
# CONFIG_XFS_FS is not set
# CONFIG_OCFS2_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_ROMFS_FS is not set
@ -659,6 +741,7 @@ CONFIG_RAMFS=y
# Miscellaneous filesystems
#
# CONFIG_HFSPLUS_FS is not set
# CONFIG_JFFS2_FS is not set
CONFIG_CRAMFS=y
# CONFIG_VXFS_FS is not set
# CONFIG_HPFS_FS is not set
@ -680,8 +763,7 @@ CONFIG_LOCKD_V4=y
CONFIG_NFS_ACL_SUPPORT=y
CONFIG_NFS_COMMON=y
CONFIG_SUNRPC=y
CONFIG_SMB_FS=y
# CONFIG_SMB_NLS_DEFAULT is not set
# CONFIG_SMB_FS is not set
# CONFIG_CIFS is not set
# CONFIG_NCP_FS is not set
# CONFIG_CODA_FS is not set
@ -775,7 +857,7 @@ CONFIG_HAS_DMA=y
#
# CONFIG_PRINTK_TIME is not set
CONFIG_ENABLE_MUST_CHECK=y
# CONFIG_MAGIC_SYSRQ is not set
CONFIG_MAGIC_SYSRQ=y
# CONFIG_UNUSED_SYMBOLS is not set
# CONFIG_DEBUG_FS is not set
# CONFIG_HEADERS_CHECK is not set
@ -793,7 +875,7 @@ CONFIG_SCHED_DEBUG=y
# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
# CONFIG_DEBUG_KOBJECT is not set
# CONFIG_DEBUG_BUGVERBOSE is not set
CONFIG_DEBUG_BUGVERBOSE=y
CONFIG_DEBUG_INFO=y
# CONFIG_DEBUG_VM is not set
# CONFIG_DEBUG_LIST is not set
@ -845,4 +927,4 @@ CONFIG_CRYPTO_DES=y
# CONFIG_CRYPTO_MICHAEL_MIC is not set
# CONFIG_CRYPTO_CRC32C is not set
# CONFIG_CRYPTO_CAMELLIA is not set
CONFIG_CRYPTO_HW=y
# CONFIG_CRYPTO_HW is not set

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