ARM: prima2: move to generic reset controller driver framework
this moves to generic IP module reset framework, and make other drivers use common device_reset() API. Cc: Srinivas Kandagatla <srinivas.kandagatla@st.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Bin Shi <Bin.Shi@csr.com> Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
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Barry Song
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951ec0909c
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e7eda91f63
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@ -0,0 +1,42 @@
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CSR SiRFSoC Reset Controller
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======================================
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Please also refer to reset.txt in this directory for common reset
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controller binding usage.
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Required properties:
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- compatible: Should be "sirf,prima2-rstc" or "sirf,marco-rstc"
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- reg: should be register base and length as documented in the
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datasheet
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- #reset-cells: 1, see below
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example:
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rstc: reset-controller@88010000 {
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compatible = "sirf,prima2-rstc";
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reg = <0x88010000 0x1000>;
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#reset-cells = <1>;
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};
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Specifying reset lines connected to IP modules
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==============================================
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The reset controller(rstc) manages various reset sources. This module provides
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reset signals for most blocks in system. Those device nodes should specify the
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reset line on the rstc in their resets property, containing a phandle to the
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rstc device node and a RESET_INDEX specifying which module to reset, as described
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in reset.txt.
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For SiRFSoC, RESET_INDEX is just reset_bit defined in SW_RST0 and SW_RST1 registers.
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For modules whose rest_bit is in SW_RST0, its RESET_INDEX is 0~31. For modules whose
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rest_bit is in SW_RST1, its RESET_INDEX is 32~63.
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example:
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vpp@90020000 {
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compatible = "sirf,prima2-vpp";
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reg = <0x90020000 0x10000>;
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interrupts = <31>;
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clocks = <&clks 35>;
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resets = <&rstc 6>;
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};
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@ -65,9 +65,10 @@
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#clock-cells = <1>;
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};
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reset-controller@88010000 {
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rstc: reset-controller@88010000 {
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compatible = "sirf,prima2-rstc";
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reg = <0x88010000 0x1000>;
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#reset-cells = <1>;
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};
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rsc-controller@88020000 {
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@ -58,9 +58,10 @@
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#size-cells = <1>;
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ranges = <0xc2000000 0xc2000000 0x1000000>;
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reset-controller@c2000000 {
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rstc: reset-controller@c2000000 {
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compatible = "sirf,marco-rstc";
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reg = <0xc2000000 0x10000>;
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#reset-cells = <1>;
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};
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};
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@ -76,9 +76,10 @@
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#clock-cells = <1>;
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};
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reset-controller@88010000 {
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rstc: reset-controller@88010000 {
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compatible = "sirf,prima2-rstc";
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reg = <0x88010000 0x1000>;
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#reset-cells = <1>;
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};
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rsc-controller@88020000 {
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@ -1,5 +1,6 @@
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config ARCH_SIRF
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bool "CSR SiRF" if ARCH_MULTI_V7
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select ARCH_HAS_RESET_CONTROLLER
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select ARCH_REQUIRE_GPIOLIB
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select GENERIC_CLOCKEVENTS
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select GENERIC_IRQ_CHIP
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@ -13,57 +13,36 @@
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#include <linux/device.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include <linux/reboot.h>
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#include <linux/reset-controller.h>
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#define SIRFSOC_RSTBIT_NUM 64
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void __iomem *sirfsoc_rstc_base;
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static DEFINE_MUTEX(rstc_lock);
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static struct of_device_id rstc_ids[] = {
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{ .compatible = "sirf,prima2-rstc" },
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{ .compatible = "sirf,marco-rstc" },
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{},
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};
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static int __init sirfsoc_of_rstc_init(void)
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static int sirfsoc_reset_module(struct reset_controller_dev *rcdev,
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unsigned long sw_reset_idx)
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{
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struct device_node *np;
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u32 reset_bit = sw_reset_idx;
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np = of_find_matching_node(NULL, rstc_ids);
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if (!np) {
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pr_err("unable to find compatible sirf rstc node in dtb\n");
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return -ENOENT;
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}
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sirfsoc_rstc_base = of_iomap(np, 0);
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if (!sirfsoc_rstc_base)
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panic("unable to map rstc cpu registers\n");
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of_node_put(np);
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return 0;
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}
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early_initcall(sirfsoc_of_rstc_init);
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int sirfsoc_reset_device(struct device *dev)
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{
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u32 reset_bit;
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if (of_property_read_u32(dev->of_node, "reset-bit", &reset_bit))
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if (reset_bit >= SIRFSOC_RSTBIT_NUM)
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return -EINVAL;
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mutex_lock(&rstc_lock);
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if (of_device_is_compatible(dev->of_node, "sirf,prima2-rstc")) {
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if (of_device_is_compatible(rcdev->of_node, "sirf,prima2-rstc")) {
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/*
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* Writing 1 to this bit resets corresponding block. Writing 0 to this
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* bit de-asserts reset signal of the corresponding block.
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* datasheet doesn't require explicit delay between the set and clear
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* of reset bit. it could be shorter if tests pass.
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*/
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writel(readl(sirfsoc_rstc_base + (reset_bit / 32) * 4) | reset_bit,
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writel(readl(sirfsoc_rstc_base + (reset_bit / 32) * 4) | (1 << reset_bit),
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sirfsoc_rstc_base + (reset_bit / 32) * 4);
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msleep(10);
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writel(readl(sirfsoc_rstc_base + (reset_bit / 32) * 4) & ~reset_bit,
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writel(readl(sirfsoc_rstc_base + (reset_bit / 32) * 4) & ~(1 << reset_bit),
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sirfsoc_rstc_base + (reset_bit / 32) * 4);
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} else {
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/*
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@ -73,9 +52,9 @@ int sirfsoc_reset_device(struct device *dev)
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* datasheet doesn't require explicit delay between the set and clear
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* of reset bit. it could be shorter if tests pass.
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*/
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writel(reset_bit, sirfsoc_rstc_base + (reset_bit / 32) * 8);
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writel(1 << reset_bit, sirfsoc_rstc_base + (reset_bit / 32) * 8);
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msleep(10);
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writel(reset_bit, sirfsoc_rstc_base + (reset_bit / 32) * 8 + 4);
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writel(1 << reset_bit, sirfsoc_rstc_base + (reset_bit / 32) * 8 + 4);
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}
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mutex_unlock(&rstc_lock);
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@ -83,6 +62,52 @@ int sirfsoc_reset_device(struct device *dev)
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return 0;
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}
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static struct reset_control_ops sirfsoc_rstc_ops = {
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.reset = sirfsoc_reset_module,
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};
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static struct reset_controller_dev sirfsoc_reset_controller = {
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.ops = &sirfsoc_rstc_ops,
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.nr_resets = SIRFSOC_RSTBIT_NUM,
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};
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static int sirfsoc_rstc_probe(struct platform_device *pdev)
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{
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struct device_node *np = pdev->dev.of_node;
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sirfsoc_rstc_base = of_iomap(np, 0);
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if (!sirfsoc_rstc_base) {
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dev_err(&pdev->dev, "unable to map rstc cpu registers\n");
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return -ENOMEM;
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}
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sirfsoc_reset_controller.of_node = np;
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reset_controller_register(&sirfsoc_reset_controller);
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return 0;
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}
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static const struct of_device_id rstc_ids[] = {
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{ .compatible = "sirf,prima2-rstc" },
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{ .compatible = "sirf,marco-rstc" },
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{},
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};
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static struct platform_driver sirfsoc_rstc_driver = {
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.probe = sirfsoc_rstc_probe,
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.driver = {
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.name = "sirfsoc_rstc",
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.owner = THIS_MODULE,
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.of_match_table = rstc_ids,
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},
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};
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static int __init sirfsoc_rstc_init(void)
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{
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return platform_driver_register(&sirfsoc_rstc_driver);
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}
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subsys_initcall(sirfsoc_rstc_init);
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#define SIRFSOC_SYS_RST_BIT BIT(31)
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void sirfsoc_restart(enum reboot_mode mode, const char *cmd)
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