ARM: clk-imx6qdl: Add clko1 configuration for imx6qdl-sabresd
WM8962 needs 24MHz clock for its MCLK, so choose PLL4 as the parent of clko1. Signed-off-by: Nicolin Chen <b42378@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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@ -550,6 +550,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
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clk_register_clkdev(clk[ahb], "ahb", NULL);
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clk_register_clkdev(clk[cko1], "cko1", NULL);
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clk_register_clkdev(clk[arm], NULL, "cpu0");
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clk_register_clkdev(clk[pll4_post_div], "pll4_post_div", NULL);
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clk_register_clkdev(clk[pll4_audio], "pll4_audio", NULL);
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if (imx6q_revision() != IMX_CHIP_REVISION_1_0) {
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clk_set_parent(clk[ldb_di0_sel], clk[pll5_video_div]);
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@ -146,6 +146,45 @@ static void __init imx6q_sabrelite_init(void)
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imx6q_sabrelite_cko1_setup();
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}
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static void __init imx6q_sabresd_cko1_setup(void)
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{
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struct clk *cko1_sel, *pll4, *pll4_post, *cko1;
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unsigned long rate;
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cko1_sel = clk_get_sys(NULL, "cko1_sel");
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pll4 = clk_get_sys(NULL, "pll4_audio");
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pll4_post = clk_get_sys(NULL, "pll4_post_div");
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cko1 = clk_get_sys(NULL, "cko1");
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if (IS_ERR(cko1_sel) || IS_ERR(pll4)
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|| IS_ERR(pll4_post) || IS_ERR(cko1)) {
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pr_err("cko1 setup failed!\n");
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goto put_clk;
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}
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/*
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* Setting pll4 at 768MHz (24MHz * 32)
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* So its child clock can get 24MHz easily
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*/
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clk_set_rate(pll4, 768000000);
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clk_set_parent(cko1_sel, pll4_post);
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rate = clk_round_rate(cko1, 24000000);
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clk_set_rate(cko1, rate);
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put_clk:
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if (!IS_ERR(cko1_sel))
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clk_put(cko1_sel);
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if (!IS_ERR(pll4_post))
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clk_put(pll4_post);
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if (!IS_ERR(pll4))
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clk_put(pll4);
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if (!IS_ERR(cko1))
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clk_put(cko1);
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}
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static void __init imx6q_sabresd_init(void)
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{
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imx6q_sabresd_cko1_setup();
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}
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static void __init imx6q_1588_init(void)
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{
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struct regmap *gpr;
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@ -166,6 +205,9 @@ static void __init imx6q_init_machine(void)
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{
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if (of_machine_is_compatible("fsl,imx6q-sabrelite"))
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imx6q_sabrelite_init();
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else if (of_machine_is_compatible("fsl,imx6q-sabresd") ||
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of_machine_is_compatible("fsl,imx6dl-sabresd"))
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imx6q_sabresd_init();
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of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
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