powerpc/85xx: Rework MPC8569MDS device tree
Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to a standard 2 #address-cells & #size-cells at top-level * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Removed CPU properties setup by u-boot to match other .dts * Reworked PCIe nodes to allow supportin IRQs for controller (errors) and moved PCI device IRQs down to virtual bridge level * Renamed SDHC node from 'sdhci' to 'sdhc' * Dropping "fsl,mpc8569-IP..." from compatibles for standard blocks Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Kumar Gala
parent
1a23b4a64a
commit
e7a7b329f2
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@ -0,0 +1,292 @@
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/*
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* MPC8569 Silicon/SoC Device Tree Source (post include)
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*
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* Copyright 2011 Freescale Semiconductor Inc.
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*
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* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
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||||
*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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||||
* GNU General Public License ("GPL") as published by the Free Software
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* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
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||||
*
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||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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&lbc {
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#address-cells = <2>;
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#size-cells = <1>;
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compatible = "fsl,mpc8569-elbc", "fsl,elbc", "simple-bus";
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interrupts = <19 2 0 0>;
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sleep = <&pmc 0x08000000>;
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};
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/* controller at 0xa000 */
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&pci1 {
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compatible = "fsl,mpc8548-pcie";
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device_type = "pci";
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#size-cells = <2>;
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#address-cells = <3>;
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bus-range = <0 255>;
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clock-frequency = <33333333>;
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interrupts = <26 2 0 0>;
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sleep = <&pmc 0x20000000>;
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pcie@0 {
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reg = <0 0 0 0 0>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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device_type = "pci";
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interrupts = <26 2 0 0>;
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interrupt-map-mask = <0xf800 0 0 7>;
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interrupt-map = <
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/* IDSEL 0x0 */
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0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
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0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
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0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
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0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
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>;
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};
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};
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&rio {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "fsl,mpc8569-rapidio", "fsl,rapidio-delta";
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interrupts = <48 2 0 0 /* error */
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49 2 0 0 /* bell_outb */
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50 2 0 0 /* bell_inb */
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53 2 0 0 /* msg1_tx */
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54 2 0 0 /* msg1_rx */
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55 2 0 0 /* msg2_tx */
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56 2 0 0 /* msg2_rx */>;
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sleep = <&pmc 0x00080000>;
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};
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&soc {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "soc";
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compatible = "fsl,mpc8569-immr", "simple-bus";
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bus-frequency = <0>; // Filled out by uboot.
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ecm-law@0 {
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compatible = "fsl,ecm-law";
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reg = <0x0 0x1000>;
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fsl,num-laws = <10>;
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};
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ecm@1000 {
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compatible = "fsl,mpc8569-ecm", "fsl,ecm";
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reg = <0x1000 0x1000>;
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interrupts = <17 2 0 0>;
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};
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memory-controller@2000 {
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compatible = "fsl,mpc8569-memory-controller";
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reg = <0x2000 0x1000>;
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interrupts = <18 2 0 0>;
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};
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i2c-sleep-nexus {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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sleep = <&pmc 0x00000004>;
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ranges;
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/include/ "pq3-i2c-0.dtsi"
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/include/ "pq3-i2c-1.dtsi"
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};
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duart-sleep-nexus {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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sleep = <&pmc 0x00000002>;
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ranges;
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/include/ "pq3-duart-0.dtsi"
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};
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L2: l2-cache-controller@20000 {
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compatible = "fsl,mpc8569-l2-cache-controller";
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reg = <0x20000 0x1000>;
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cache-line-size = <32>; // 32 bytes
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cache-size = <0x80000>; // L2, 512K
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interrupts = <16 2 0 0>;
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};
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/include/ "pq3-dma-0.dtsi"
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/include/ "pq3-esdhc-0.dtsi"
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sdhc@2e000 {
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sleep = <&pmc 0x00200000>;
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};
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par_io@e0100 {
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0xe0100 0x100>;
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ranges = <0x0 0xe0100 0x100>;
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device_type = "par_io";
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};
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/include/ "pq3-sec3.1-0.dtsi"
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crypto@30000 {
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sleep = <&pmc 0x01000000>;
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};
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/include/ "pq3-mpic.dtsi"
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global-utilities@e0000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,mpc8569-guts", "fsl,mpc8548-guts";
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reg = <0xe0000 0x1000>;
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ranges = <0 0xe0000 0x1000>;
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fsl,has-rstcr;
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pmc: power@70 {
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compatible = "fsl,mpc8569-pmc",
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"fsl,mpc8548-pmc";
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reg = <0x70 0x20>;
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};
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};
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};
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&qe {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "qe";
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compatible = "fsl,qe";
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sleep = <&pmc 0x00000800>;
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brg-frequency = <0>;
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bus-frequency = <0>;
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fsl,qe-num-riscs = <4>;
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fsl,qe-num-snums = <46>;
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qeic: interrupt-controller@80 {
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interrupt-controller;
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compatible = "fsl,qe-ic";
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#address-cells = <0>;
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#interrupt-cells = <1>;
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reg = <0x80 0x80>;
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interrupts = <46 2 0 0 46 2 0 0>; //high:30 low:30
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interrupt-parent = <&mpic>;
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};
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timer@440 {
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compatible = "fsl,mpc8569-qe-gtm",
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"fsl,qe-gtm", "fsl,gtm";
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reg = <0x440 0x40>;
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interrupts = <12 13 14 15>;
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interrupt-parent = <&qeic>;
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/* Filled in by U-Boot */
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clock-frequency = <0>;
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};
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spi@4c0 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,mpc8569-qe-spi", "fsl,spi";
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reg = <0x4c0 0x40>;
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cell-index = <0>;
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interrupts = <2>;
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interrupt-parent = <&qeic>;
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};
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spi@500 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <1>;
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compatible = "fsl,spi";
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reg = <0x500 0x40>;
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interrupts = <1>;
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interrupt-parent = <&qeic>;
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};
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usb@6c0 {
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compatible = "fsl,mpc8569-qe-usb",
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"fsl,mpc8323-qe-usb";
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reg = <0x6c0 0x40 0x8b00 0x100>;
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interrupts = <11>;
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interrupt-parent = <&qeic>;
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};
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ucc@2000 {
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cell-index = <1>;
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reg = <0x2000 0x200>;
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interrupts = <32>;
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interrupt-parent = <&qeic>;
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};
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ucc@2200 {
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cell-index = <3>;
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reg = <0x2200 0x200>;
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interrupts = <34>;
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interrupt-parent = <&qeic>;
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};
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ucc@3000 {
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cell-index = <2>;
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reg = <0x3000 0x200>;
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interrupts = <33>;
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interrupt-parent = <&qeic>;
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};
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ucc@3200 {
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cell-index = <4>;
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reg = <0x3200 0x200>;
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interrupts = <35>;
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interrupt-parent = <&qeic>;
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};
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ucc@3400 {
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cell-index = <6>;
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reg = <0x3400 0x200>;
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interrupts = <41>;
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interrupt-parent = <&qeic>;
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};
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ucc@3600 {
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cell-index = <8>;
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reg = <0x3600 0x200>;
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interrupts = <43>;
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interrupt-parent = <&qeic>;
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};
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muram@10000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,qe-muram", "fsl,cpm-muram";
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ranges = <0x0 0x10000 0x20000>;
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data-only@0 {
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compatible = "fsl,qe-muram-data",
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"fsl,cpm-muram-data";
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reg = <0x0 0x20000>;
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};
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};
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};
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@ -0,0 +1,64 @@
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/*
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* MPC8569 Silicon/SoC Device Tree Source (pre include)
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*
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* Copyright 2011 Freescale Semiconductor Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
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* * Neither the name of Freescale Semiconductor nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") as published by the Free Software
|
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* Foundation, either version 2 of that License or (at your option) any
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* later version.
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*
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||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/dts-v1/;
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/ {
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compatible = "fsl,MPC8569";
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&mpic>;
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aliases {
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serial0 = &serial0;
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serial1 = &serial1;
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ethernet0 = &enet0;
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ethernet1 = &enet1;
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ethernet2 = &enet2;
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ethernet3 = &enet3;
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pci1 = &pci1;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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PowerPC,8569@0 {
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device_type = "cpu";
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reg = <0x0>;
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next-level-cache = <&L2>;
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sleep = <&pmc 0x00008000 // core
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&pmc 0x00004000>; // timebase
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};
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};
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};
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@ -9,66 +9,36 @@
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* option) any later version.
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*/
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/dts-v1/;
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/include/ "fsl/mpc8569si-pre.dtsi"
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/ {
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model = "MPC8569EMDS";
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compatible = "fsl,MPC8569EMDS";
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#address-cells = <1>;
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#size-cells = <1>;
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&mpic>;
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aliases {
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serial0 = &serial0;
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serial1 = &serial1;
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ethernet0 = &enet0;
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ethernet1 = &enet1;
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ethernet2 = &enet2;
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ethernet3 = &enet3;
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ethernet5 = &enet5;
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ethernet7 = &enet7;
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pci1 = &pci1;
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rapidio0 = &rio0;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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PowerPC,8569@0 {
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device_type = "cpu";
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reg = <0x0>;
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d-cache-line-size = <32>; // 32 bytes
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i-cache-line-size = <32>; // 32 bytes
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d-cache-size = <0x8000>; // L1, 32K
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i-cache-size = <0x8000>; // L1, 32K
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sleep = <&pmc 0x00008000 // core
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&pmc 0x00004000>; // timebase
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timebase-frequency = <0>;
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bus-frequency = <0>;
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clock-frequency = <0>;
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next-level-cache = <&L2>;
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};
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rapidio0 = &rio;
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||||
};
|
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memory {
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device_type = "memory";
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};
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localbus@e0005000 {
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#address-cells = <2>;
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#size-cells = <1>;
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compatible = "fsl,mpc8569-elbc", "fsl,elbc", "simple-bus";
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reg = <0xe0005000 0x1000>;
|
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interrupts = <19 2>;
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interrupt-parent = <&mpic>;
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sleep = <&pmc 0x08000000>;
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lbc: localbus@e0005000 {
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reg = <0x0 0xe0005000 0x0 0x1000>;
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|
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ranges = <0x0 0x0 0xfe000000 0x02000000
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0x1 0x0 0xf8000000 0x00008000
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0x2 0x0 0xf0000000 0x04000000
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0x3 0x0 0xfc000000 0x00008000
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||||
0x4 0x0 0xf8008000 0x00008000
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0x5 0x0 0xf8010000 0x00008000>;
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ranges = <0x0 0x0 0x0 0xfe000000 0x02000000
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0x1 0x0 0x0 0xf8000000 0x00008000
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0x2 0x0 0x0 0xf0000000 0x04000000
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0x3 0x0 0x0 0xfc000000 0x00008000
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0x4 0x0 0x0 0xf8008000 0x00008000
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0x5 0x0 0x0 0xf8010000 0x00008000>;
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||||
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||||
nor@0,0 {
|
||||
#address-cells = <1>;
|
||||
|
|
@ -133,220 +103,25 @@
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|||
};
|
||||
};
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||||
|
||||
soc@e0000000 {
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||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "fsl,mpc8569-immr", "simple-bus";
|
||||
ranges = <0x0 0xe0000000 0x100000>;
|
||||
bus-frequency = <0>;
|
||||
|
||||
ecm-law@0 {
|
||||
compatible = "fsl,ecm-law";
|
||||
reg = <0x0 0x1000>;
|
||||
fsl,num-laws = <10>;
|
||||
};
|
||||
|
||||
ecm@1000 {
|
||||
compatible = "fsl,mpc8569-ecm", "fsl,ecm";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <17 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
memory-controller@2000 {
|
||||
compatible = "fsl,mpc8569-memory-controller";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <18 2>;
|
||||
};
|
||||
soc: soc@e0000000 {
|
||||
ranges = <0x0 0x0 0xe0000000 0x100000>;
|
||||
|
||||
i2c-sleep-nexus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
sleep = <&pmc 0x00000004>;
|
||||
ranges;
|
||||
|
||||
i2c@3000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3000 0x100>;
|
||||
interrupts = <43 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
|
||||
rtc@68 {
|
||||
compatible = "dallas,ds1374";
|
||||
reg = <0x68>;
|
||||
interrupts = <3 1>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <3 1 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@3100 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3100 0x100>;
|
||||
interrupts = <43 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
};
|
||||
};
|
||||
|
||||
duart-sleep-nexus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
sleep = <&pmc 0x00000002>;
|
||||
ranges;
|
||||
|
||||
serial0: serial@4500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4500 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <42 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
serial1: serial@4600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4600 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <42 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
};
|
||||
|
||||
L2: l2-cache-controller@20000 {
|
||||
compatible = "fsl,mpc8569-l2-cache-controller";
|
||||
reg = <0x20000 0x1000>;
|
||||
cache-line-size = <32>; // 32 bytes
|
||||
cache-size = <0x80000>; // L2, 512K
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <16 2>;
|
||||
};
|
||||
|
||||
dma@21300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8569-dma", "fsl,eloplus-dma";
|
||||
reg = <0x21300 0x4>;
|
||||
ranges = <0x0 0x21100 0x200>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,mpc8569-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <20 2>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,mpc8569-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <21 2>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,mpc8569-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <22 2>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,mpc8569-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <23 2>;
|
||||
};
|
||||
};
|
||||
|
||||
sdhci@2e000 {
|
||||
compatible = "fsl,mpc8569-esdhc", "fsl,esdhc";
|
||||
reg = <0x2e000 0x1000>;
|
||||
interrupts = <72 0x8>;
|
||||
interrupt-parent = <&mpic>;
|
||||
sleep = <&pmc 0x00200000>;
|
||||
/* Filled in by U-Boot */
|
||||
clock-frequency = <0>;
|
||||
sdhc@2e000 {
|
||||
status = "disabled";
|
||||
sdhci,1-bit-only;
|
||||
};
|
||||
|
||||
crypto@30000 {
|
||||
compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
|
||||
"fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <45 2 58 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
fsl,num-channels = <4>;
|
||||
fsl,channel-fifo-len = <24>;
|
||||
fsl,exec-units-mask = <0xbfe>;
|
||||
fsl,descriptor-types-mask = <0x3ab0ebf>;
|
||||
sleep = <&pmc 0x01000000>;
|
||||
};
|
||||
|
||||
mpic: pic@40000 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x40000 0x40000>;
|
||||
compatible = "chrp,open-pic";
|
||||
device_type = "open-pic";
|
||||
};
|
||||
|
||||
msi@41600 {
|
||||
compatible = "fsl,mpc8568-msi", "fsl,mpic-msi";
|
||||
reg = <0x41600 0x80>;
|
||||
msi-available-ranges = <0 0x100>;
|
||||
interrupts = <
|
||||
0xe0 0
|
||||
0xe1 0
|
||||
0xe2 0
|
||||
0xe3 0
|
||||
0xe4 0
|
||||
0xe5 0
|
||||
0xe6 0
|
||||
0xe7 0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
global-utilities@e0000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8569-guts", "fsl,mpc8548-guts";
|
||||
reg = <0xe0000 0x1000>;
|
||||
ranges = <0 0xe0000 0x1000>;
|
||||
fsl,has-rstcr;
|
||||
|
||||
pmc: power@70 {
|
||||
compatible = "fsl,mpc8569-pmc",
|
||||
"fsl,mpc8548-pmc";
|
||||
reg = <0x70 0x20>;
|
||||
};
|
||||
};
|
||||
|
||||
par_io@e0100 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xe0100 0x100>;
|
||||
ranges = <0x0 0xe0100 0x100>;
|
||||
device_type = "par_io";
|
||||
num-ports = <7>;
|
||||
|
||||
qe_pio_e: gpio-controller@80 {
|
||||
|
|
@ -447,47 +222,11 @@
|
|||
};
|
||||
};
|
||||
|
||||
qe@e0080000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "qe";
|
||||
compatible = "fsl,qe";
|
||||
ranges = <0x0 0xe0080000 0x40000>;
|
||||
reg = <0xe0080000 0x480>;
|
||||
sleep = <&pmc 0x00000800>;
|
||||
brg-frequency = <0>;
|
||||
bus-frequency = <0>;
|
||||
fsl,qe-num-riscs = <4>;
|
||||
fsl,qe-num-snums = <46>;
|
||||
|
||||
qeic: interrupt-controller@80 {
|
||||
interrupt-controller;
|
||||
compatible = "fsl,qe-ic";
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
reg = <0x80 0x80>;
|
||||
interrupts = <46 2 46 2>; //high:30 low:30
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
timer@440 {
|
||||
compatible = "fsl,mpc8569-qe-gtm",
|
||||
"fsl,qe-gtm", "fsl,gtm";
|
||||
reg = <0x440 0x40>;
|
||||
interrupts = <12 13 14 15>;
|
||||
interrupt-parent = <&qeic>;
|
||||
/* Filled in by U-Boot */
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
qe: qe@e0080000 {
|
||||
ranges = <0x0 0x0 0xe0080000 0x40000>;
|
||||
reg = <0x0 0xe0080000 0x0 0x480>;
|
||||
|
||||
spi@4c0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,mpc8569-qe-spi", "fsl,spi";
|
||||
reg = <0x4c0 0x40>;
|
||||
cell-index = <0>;
|
||||
interrupts = <2>;
|
||||
interrupt-parent = <&qeic>;
|
||||
gpios = <&qe_pio_e 30 0>;
|
||||
mode = "cpu-qe";
|
||||
|
||||
|
|
@ -499,20 +238,10 @@
|
|||
};
|
||||
|
||||
spi@500 {
|
||||
cell-index = <1>;
|
||||
compatible = "fsl,spi";
|
||||
reg = <0x500 0x40>;
|
||||
interrupts = <1>;
|
||||
interrupt-parent = <&qeic>;
|
||||
mode = "cpu";
|
||||
};
|
||||
|
||||
usb@6c0 {
|
||||
compatible = "fsl,mpc8569-qe-usb",
|
||||
"fsl,mpc8323-qe-usb";
|
||||
reg = <0x6c0 0x40 0x8b00 0x100>;
|
||||
interrupts = <11>;
|
||||
interrupt-parent = <&qeic>;
|
||||
fsl,fullspeed-clock = "clk5";
|
||||
fsl,lowspeed-clock = "brg10";
|
||||
gpios = <&qe_pio_f 3 0 /* USBOE */
|
||||
|
|
@ -527,10 +256,6 @@
|
|||
enet0: ucc@2000 {
|
||||
device_type = "network";
|
||||
compatible = "ucc_geth";
|
||||
cell-index = <1>;
|
||||
reg = <0x2000 0x200>;
|
||||
interrupts = <32>;
|
||||
interrupt-parent = <&qeic>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
rx-clock-name = "none";
|
||||
tx-clock-name = "clk12";
|
||||
|
|
@ -548,35 +273,33 @@
|
|||
|
||||
qe_phy0: ethernet-phy@07 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <1 1>;
|
||||
interrupts = <1 1 0 0>;
|
||||
reg = <0x7>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
qe_phy1: ethernet-phy@01 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <2 1>;
|
||||
interrupts = <2 1 0 0>;
|
||||
reg = <0x1>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
qe_phy2: ethernet-phy@02 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <3 1>;
|
||||
interrupts = <3 1 0 0>;
|
||||
reg = <0x2>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
qe_phy3: ethernet-phy@03 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <4 1>;
|
||||
interrupts = <4 1 0 0>;
|
||||
reg = <0x3>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
qe_phy5: ethernet-phy@04 {
|
||||
interrupt-parent = <&mpic>;
|
||||
reg = <0x04>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
qe_phy7: ethernet-phy@06 {
|
||||
interrupt-parent = <&mpic>;
|
||||
reg = <0x6>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
|
|
@ -610,10 +333,6 @@
|
|||
enet2: ucc@2200 {
|
||||
device_type = "network";
|
||||
compatible = "ucc_geth";
|
||||
cell-index = <3>;
|
||||
reg = <0x2200 0x200>;
|
||||
interrupts = <34>;
|
||||
interrupt-parent = <&qeic>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
rx-clock-name = "none";
|
||||
tx-clock-name = "clk12";
|
||||
|
|
@ -637,10 +356,6 @@
|
|||
enet1: ucc@3000 {
|
||||
device_type = "network";
|
||||
compatible = "ucc_geth";
|
||||
cell-index = <2>;
|
||||
reg = <0x3000 0x200>;
|
||||
interrupts = <33>;
|
||||
interrupt-parent = <&qeic>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
rx-clock-name = "none";
|
||||
tx-clock-name = "clk17";
|
||||
|
|
@ -664,10 +379,6 @@
|
|||
enet3: ucc@3200 {
|
||||
device_type = "network";
|
||||
compatible = "ucc_geth";
|
||||
cell-index = <4>;
|
||||
reg = <0x3200 0x200>;
|
||||
interrupts = <35>;
|
||||
interrupt-parent = <&qeic>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
rx-clock-name = "none";
|
||||
tx-clock-name = "clk17";
|
||||
|
|
@ -691,10 +402,6 @@
|
|||
enet5: ucc@3400 {
|
||||
device_type = "network";
|
||||
compatible = "ucc_geth";
|
||||
cell-index = <6>;
|
||||
reg = <0x3400 0x200>;
|
||||
interrupts = <41>;
|
||||
interrupt-parent = <&qeic>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
rx-clock-name = "none";
|
||||
tx-clock-name = "none";
|
||||
|
|
@ -706,10 +413,6 @@
|
|||
enet7: ucc@3600 {
|
||||
device_type = "network";
|
||||
compatible = "ucc_geth";
|
||||
cell-index = <8>;
|
||||
reg = <0x3600 0x200>;
|
||||
interrupts = <43>;
|
||||
interrupt-parent = <&qeic>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
rx-clock-name = "none";
|
||||
tx-clock-name = "none";
|
||||
|
|
@ -717,50 +420,14 @@
|
|||
phy-handle = <&qe_phy7>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
muram@10000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,qe-muram", "fsl,cpm-muram";
|
||||
ranges = <0x0 0x10000 0x20000>;
|
||||
|
||||
data-only@0 {
|
||||
compatible = "fsl,qe-muram-data",
|
||||
"fsl,cpm-muram-data";
|
||||
reg = <0x0 0x20000>;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
/* PCI Express */
|
||||
pci1: pcie@e000a000 {
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0xe000a000 0x1000>;
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 (PEX) */
|
||||
00000 0x0 0x0 0x1 &mpic 0x0 0x1
|
||||
00000 0x0 0x0 0x2 &mpic 0x1 0x1
|
||||
00000 0x0 0x0 0x3 &mpic 0x2 0x1
|
||||
00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
|
||||
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <26 2>;
|
||||
bus-range = <0 255>;
|
||||
ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
|
||||
0x1000000 0x0 0x00000000 0xe2800000 0x0 0x00800000>;
|
||||
sleep = <&pmc 0x20000000>;
|
||||
clock-frequency = <33333333>;
|
||||
reg = <0x0 0xe000a000 0x0 0x1000>;
|
||||
ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x10000000
|
||||
0x1000000 0x0 0x00000000 0 0xe2800000 0x0 0x00800000>;
|
||||
pcie@0 {
|
||||
reg = <0x0 0x0 0x0 0x0 0x0>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
ranges = <0x2000000 0x0 0xa0000000
|
||||
0x2000000 0x0 0xa0000000
|
||||
0x0 0x10000000
|
||||
|
|
@ -771,20 +438,10 @@
|
|||
};
|
||||
};
|
||||
|
||||
rio0: rapidio@e00c00000 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
compatible = "fsl,mpc8569-rapidio", "fsl,rapidio-delta";
|
||||
reg = <0xe00c0000 0x20000>;
|
||||
ranges = <0x0 0x0 0xc0000000 0x0 0x20000000>;
|
||||
interrupts = <48 2 /* error */
|
||||
49 2 /* bell_outb */
|
||||
50 2 /* bell_inb */
|
||||
53 2 /* msg1_tx */
|
||||
54 2 /* msg1_rx */
|
||||
55 2 /* msg2_tx */
|
||||
56 2 /* msg2_rx */>;
|
||||
interrupt-parent = <&mpic>;
|
||||
sleep = <&pmc 0x00080000>;
|
||||
rio: rapidio@e00c00000 {
|
||||
reg = <0x0 0xe00c0000 0x0 0x20000>;
|
||||
ranges = <0x0 0x0 0x0 0xc0000000 0x0 0x20000000>;
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "fsl/mpc8569si-post.dtsi"
|
||||
|
|
|
|||
Loading…
Reference in New Issue