x86: io-apic: IO-APIC MMIO should not fail on resource insertion
If IO-APIC base address is 1K aligned we should not fail on resourse insertion procedure. For this sake we define IO_APIC_SLOT_SIZE constant which should cover all IO-APIC direct accessible registers. An example of a such configuration is there http://marc.info/?l=linux-kernel&m=118114792006520 | | Quoting the message | | IOAPIC[0]: apic_id 2, version 32, address 0xfec00000, GSI 0-23 | IOAPIC[1]: apic_id 3, version 32, address 0xfec80000, GSI 24-47 | IOAPIC[2]: apic_id 4, version 32, address 0xfec80400, GSI 48-71 | IOAPIC[3]: apic_id 5, version 32, address 0xfec84000, GSI 72-95 | IOAPIC[4]: apic_id 8, version 32, address 0xfec84400, GSI 96-119 | Reported-by: "Maciej W. Rozycki" <macro@linux-mips.org> Signed-off-by: Cyrill Gorcunov <gorcunov@openvz.org> Acked-by: Yinghai Lu <yinghai@kernel.org> LKML-Reference: <20091116151426.GC5653@lenovo> Signed-off-by: Ingo Molnar <mingo@elte.hu>
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@ -11,6 +11,12 @@
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#define IO_APIC_DEFAULT_PHYS_BASE 0xfec00000
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#define APIC_DEFAULT_PHYS_BASE 0xfee00000
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/*
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* This is the IO-APIC register space as specified
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* by Intel docs:
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*/
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#define IO_APIC_SLOT_SIZE 1024
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#define APIC_ID 0x20
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#define APIC_LVR 0x30
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@ -4100,18 +4100,17 @@ void __init ioapic_init_mappings(void)
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#ifdef CONFIG_X86_32
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fake_ioapic_page:
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#endif
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ioapic_phys = (unsigned long)
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alloc_bootmem_pages(PAGE_SIZE);
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ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE);
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ioapic_phys = __pa(ioapic_phys);
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}
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set_fixmap_nocache(idx, ioapic_phys);
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apic_printk(APIC_VERBOSE,
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"mapped IOAPIC to %08lx (%08lx)\n",
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__fix_to_virt(idx), ioapic_phys);
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apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n",
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__fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK),
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ioapic_phys);
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idx++;
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ioapic_res->start = ioapic_phys;
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ioapic_res->end = ioapic_phys + PAGE_SIZE-1;
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ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1;
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ioapic_res++;
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}
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}
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