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MIPS: BCM63xx: Add support for the Broadcom BCM63xx family of SOCs. 

Signed-off-by: Maxime Bizon <mbizon@freebox.fr>
Signed-off-by: Florian Fainelli <florian@openwrt.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Maxime Bizon 2009-08-18 13:23:37 +01:00 committed by Ralf Baechle
parent 0de663ef86
commit e7300d04bd
40 changed files with 5896 additions and 0 deletions
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16
arch/mips/Kconfig
View File

@ -80,6 +80,21 @@ config BCM47XX
help help
Support for BCM47XX based boards Support for BCM47XX based boards
config BCM63XX
bool "Broadcom BCM63XX based boards"
select CEVT_R4K
select CSRC_R4K
select DMA_NONCOHERENT
select IRQ_CPU
select SYS_HAS_CPU_MIPS32_R1
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_HAS_EARLY_PRINTK
select SWAP_IO_SPACE
select ARCH_REQUIRE_GPIOLIB
help
Support for BCM63XX based boards
config MIPS_COBALT config MIPS_COBALT
bool "Cobalt Server" bool "Cobalt Server"
select CEVT_R4K select CEVT_R4K
@ -645,6 +660,7 @@ endchoice
source "arch/mips/alchemy/Kconfig" source "arch/mips/alchemy/Kconfig"
source "arch/mips/basler/excite/Kconfig" source "arch/mips/basler/excite/Kconfig"
source "arch/mips/bcm63xx/Kconfig"
source "arch/mips/jazz/Kconfig" source "arch/mips/jazz/Kconfig"
source "arch/mips/lasat/Kconfig" source "arch/mips/lasat/Kconfig"
source "arch/mips/pmc-sierra/Kconfig" source "arch/mips/pmc-sierra/Kconfig"

7
arch/mips/Makefile
View File

@ -564,6 +564,13 @@ core-$(CONFIG_BCM47XX) += arch/mips/bcm47xx/
cflags-$(CONFIG_BCM47XX) += -I$(srctree)/arch/mips/include/asm/mach-bcm47xx cflags-$(CONFIG_BCM47XX) += -I$(srctree)/arch/mips/include/asm/mach-bcm47xx
load-$(CONFIG_BCM47XX) := 0xffffffff80001000 load-$(CONFIG_BCM47XX) := 0xffffffff80001000
#
# Broadcom BCM63XX boards
#
core-$(CONFIG_BCM63XX) += arch/mips/bcm63xx/
cflags-$(CONFIG_BCM63XX) += -I$(srctree)/arch/mips/include/asm/mach-bcm63xx/
load-$(CONFIG_BCM63XX) := 0xffffffff80010000
# #
# SNI RM # SNI RM
# #

25
arch/mips/bcm63xx/Kconfig Normal file
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@ -0,0 +1,25 @@
menu "CPU support"
depends on BCM63XX
config BCM63XX_CPU_6338
bool "support 6338 CPU"
select HW_HAS_PCI
select USB_ARCH_HAS_OHCI
select USB_OHCI_BIG_ENDIAN_DESC
select USB_OHCI_BIG_ENDIAN_MMIO
config BCM63XX_CPU_6345
bool "support 6345 CPU"
select USB_OHCI_BIG_ENDIAN_DESC
select USB_OHCI_BIG_ENDIAN_MMIO
config BCM63XX_CPU_6348
bool "support 6348 CPU"
select HW_HAS_PCI
config BCM63XX_CPU_6358
bool "support 6358 CPU"
select HW_HAS_PCI
endmenu
source "arch/mips/bcm63xx/boards/Kconfig"

7
arch/mips/bcm63xx/Makefile Normal file
View File

@ -0,0 +1,7 @@
obj-y += clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o \
dev-dsp.o
obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
obj-y += boards/
EXTRA_CFLAGS += -Werror

11
arch/mips/bcm63xx/boards/Kconfig Normal file
View File

@ -0,0 +1,11 @@
choice
prompt "Board support"
depends on BCM63XX
default BOARD_BCM963XX
config BOARD_BCM963XX
bool "Generic Broadcom 963xx boards"
select SSB
help
endchoice

3
arch/mips/bcm63xx/boards/Makefile Normal file
View File

@ -0,0 +1,3 @@
obj-$(CONFIG_BOARD_BCM963XX) += board_bcm963xx.o
EXTRA_CFLAGS += -Werror

837
arch/mips/bcm63xx/boards/board_bcm963xx.c Normal file
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@ -0,0 +1,837 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
* Copyright (C) 2008 Florian Fainelli <florian@openwrt.org>
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/platform_device.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/physmap.h>
#include <linux/ssb/ssb.h>
#include <asm/addrspace.h>
#include <bcm63xx_board.h>
#include <bcm63xx_cpu.h>
#include <bcm63xx_regs.h>
#include <bcm63xx_io.h>
#include <bcm63xx_board.h>
#include <bcm63xx_dev_pci.h>
#include <bcm63xx_dev_enet.h>
#include <bcm63xx_dev_dsp.h>
#include <board_bcm963xx.h>
#define PFX "board_bcm963xx: "
static struct bcm963xx_nvram nvram;
static unsigned int mac_addr_used;
static struct board_info board;
/*
* known 6338 boards
*/
#ifdef CONFIG_BCM63XX_CPU_6338
static struct board_info __initdata board_96338gw = {
.name = "96338GW",
.expected_cpu_id = 0x6338,
.has_enet0 = 1,
.enet0 = {
.force_speed_100 = 1,
.force_duplex_full = 1,
},
.has_ohci0 = 1,
.leds = {
{
.name = "adsl",
.gpio = 3,
.active_low = 1,
},
{
.name = "ses",
.gpio = 5,
.active_low = 1,
},
{
.name = "ppp-fail",
.gpio = 4,
.active_low = 1,
},
{
.name = "power",
.gpio = 0,
.active_low = 1,
.default_trigger = "default-on",
},
{
.name = "stop",
.gpio = 1,
.active_low = 1,
}
},
};
static struct board_info __initdata board_96338w = {
.name = "96338W",
.expected_cpu_id = 0x6338,
.has_enet0 = 1,
.enet0 = {
.force_speed_100 = 1,
.force_duplex_full = 1,
},
.leds = {
{
.name = "adsl",
.gpio = 3,
.active_low = 1,
},
{
.name = "ses",
.gpio = 5,
.active_low = 1,
},
{
.name = "ppp-fail",
.gpio = 4,
.active_low = 1,
},
{
.name = "power",
.gpio = 0,
.active_low = 1,
.default_trigger = "default-on",
},
{
.name = "stop",
.gpio = 1,
.active_low = 1,
},
},
};
#endif
/*
* known 6345 boards
*/
#ifdef CONFIG_BCM63XX_CPU_6345
static struct board_info __initdata board_96345gw2 = {
.name = "96345GW2",
.expected_cpu_id = 0x6345,
};
#endif
/*
* known 6348 boards
*/
#ifdef CONFIG_BCM63XX_CPU_6348
static struct board_info __initdata board_96348r = {
.name = "96348R",
.expected_cpu_id = 0x6348,
.has_enet0 = 1,
.has_pci = 1,
.enet0 = {
.has_phy = 1,
.use_internal_phy = 1,
},
.leds = {
{
.name = "adsl-fail",
.gpio = 2,
.active_low = 1,
},
{
.name = "ppp",
.gpio = 3,
.active_low = 1,
},
{
.name = "ppp-fail",
.gpio = 4,
.active_low = 1,
},
{
.name = "power",
.gpio = 0,
.active_low = 1,
.default_trigger = "default-on",
},
{
.name = "stop",
.gpio = 1,
.active_low = 1,
},
},
};
static struct board_info __initdata board_96348gw_10 = {
.name = "96348GW-10",
.expected_cpu_id = 0x6348,
.has_enet0 = 1,
.has_enet1 = 1,
.has_pci = 1,
.enet0 = {
.has_phy = 1,
.use_internal_phy = 1,
},
.enet1 = {
.force_speed_100 = 1,
.force_duplex_full = 1,
},
.has_ohci0 = 1,
.has_pccard = 1,
.has_ehci0 = 1,
.has_dsp = 1,
.dsp = {
.gpio_rst = 6,
.gpio_int = 34,
.cs = 2,
.ext_irq = 2,
},
.leds = {
{
.name = "adsl-fail",
.gpio = 2,
.active_low = 1,
},
{
.name = "ppp",
.gpio = 3,
.active_low = 1,
},
{
.name = "ppp-fail",
.gpio = 4,
.active_low = 1,
},
{
.name = "power",
.gpio = 0,
.active_low = 1,
.default_trigger = "default-on",
},
{
.name = "stop",
.gpio = 1,
.active_low = 1,
},
},
};
static struct board_info __initdata board_96348gw_11 = {
.name = "96348GW-11",
.expected_cpu_id = 0x6348,
.has_enet0 = 1,
.has_enet1 = 1,
.has_pci = 1,
.enet0 = {
.has_phy = 1,
.use_internal_phy = 1,
},
.enet1 = {
.force_speed_100 = 1,
.force_duplex_full = 1,
},
.has_ohci0 = 1,
.has_pccard = 1,
.has_ehci0 = 1,
.leds = {
{
.name = "adsl-fail",
.gpio = 2,
.active_low = 1,
},
{
.name = "ppp",
.gpio = 3,
.active_low = 1,
},
{
.name = "ppp-fail",
.gpio = 4,
.active_low = 1,
},
{
.name = "power",
.gpio = 0,
.active_low = 1,
.default_trigger = "default-on",
},
{
.name = "stop",
.gpio = 1,
.active_low = 1,
},
},
};
static struct board_info __initdata board_96348gw = {
.name = "96348GW",
.expected_cpu_id = 0x6348,
.has_enet0 = 1,
.has_enet1 = 1,
.has_pci = 1,
.enet0 = {
.has_phy = 1,
.use_internal_phy = 1,
},
.enet1 = {
.force_speed_100 = 1,
.force_duplex_full = 1,
},
.has_ohci0 = 1,
.has_dsp = 1,
.dsp = {
.gpio_rst = 6,
.gpio_int = 34,
.ext_irq = 2,
.cs = 2,
},
.leds = {
{
.name = "adsl-fail",
.gpio = 2,
.active_low = 1,
},
{
.name = "ppp",
.gpio = 3,
.active_low = 1,
},
{
.name = "ppp-fail",
.gpio = 4,
.active_low = 1,
},
{
.name = "power",
.gpio = 0,
.active_low = 1,
.default_trigger = "default-on",
},
{
.name = "stop",
.gpio = 1,
.active_low = 1,
},
},
};
static struct board_info __initdata board_FAST2404 = {
.name = "F@ST2404",
.expected_cpu_id = 0x6348,
.has_enet0 = 1,
.has_enet1 = 1,
.has_pci = 1,
.enet0 = {
.has_phy = 1,
.use_internal_phy = 1,
},
.enet1 = {
.force_speed_100 = 1,
.force_duplex_full = 1,
},
.has_ohci0 = 1,
.has_pccard = 1,
.has_ehci0 = 1,
};
static struct board_info __initdata board_DV201AMR = {
.name = "DV201AMR",
.expected_cpu_id = 0x6348,
.has_pci = 1,
.has_ohci0 = 1,
.has_enet0 = 1,
.has_enet1 = 1,
.enet0 = {
.has_phy = 1,
.use_internal_phy = 1,
},
.enet1 = {
.force_speed_100 = 1,
.force_duplex_full = 1,
},
};
static struct board_info __initdata board_96348gw_a = {
.name = "96348GW-A",
.expected_cpu_id = 0x6348,
.has_enet0 = 1,
.has_enet1 = 1,
.has_pci = 1,
.enet0 = {
.has_phy = 1,
.use_internal_phy = 1,
},
.enet1 = {
.force_speed_100 = 1,
.force_duplex_full = 1,
},
.has_ohci0 = 1,
};
#endif
/*
* known 6358 boards
*/
#ifdef CONFIG_BCM63XX_CPU_6358
static struct board_info __initdata board_96358vw = {
.name = "96358VW",
.expected_cpu_id = 0x6358,
.has_enet0 = 1,
.has_enet1 = 1,
.has_pci = 1,
.enet0 = {
.has_phy = 1,
.use_internal_phy = 1,
},
.enet1 = {
.force_speed_100 = 1,
.force_duplex_full = 1,
},
.has_ohci0 = 1,
.has_pccard = 1,
.has_ehci0 = 1,
.leds = {
{
.name = "adsl-fail",
.gpio = 15,
.active_low = 1,
},
{
.name = "ppp",
.gpio = 22,
.active_low = 1,
},
{
.name = "ppp-fail",
.gpio = 23,
.active_low = 1,
},
{
.name = "power",
.gpio = 4,
.default_trigger = "default-on",
},
{
.name = "stop",
.gpio = 5,
},
},
};
static struct board_info __initdata board_96358vw2 = {
.name = "96358VW2",
.expected_cpu_id = 0x6358,
.has_enet0 = 1,
.has_enet1 = 1,
.has_pci = 1,
.enet0 = {
.has_phy = 1,
.use_internal_phy = 1,
},
.enet1 = {
.force_speed_100 = 1,
.force_duplex_full = 1,
},
.has_ohci0 = 1,
.has_pccard = 1,
.has_ehci0 = 1,
.leds = {
{
.name = "adsl",
.gpio = 22,
.active_low = 1,
},
{
.name = "ppp-fail",
.gpio = 23,
},
{
.name = "power",
.gpio = 5,
.active_low = 1,
.default_trigger = "default-on",
},
{
.name = "stop",
.gpio = 4,
.active_low = 1,
},
},
};
static struct board_info __initdata board_AGPFS0 = {
.name = "AGPF-S0",
.expected_cpu_id = 0x6358,
.has_enet0 = 1,
.has_enet1 = 1,
.has_pci = 1,
.enet0 = {
.has_phy = 1,
.use_internal_phy = 1,
},
.enet1 = {
.force_speed_100 = 1,
.force_duplex_full = 1,
},
.has_ohci0 = 1,
.has_ehci0 = 1,
};
#endif
/*
* all boards
*/
static const struct board_info __initdata *bcm963xx_boards[] = {
#ifdef CONFIG_BCM63XX_CPU_6338
&board_96338gw,
&board_96338w,
#endif
#ifdef CONFIG_BCM63XX_CPU_6345
&board_96345gw2,
#endif
#ifdef CONFIG_BCM63XX_CPU_6348
&board_96348r,
&board_96348gw,
&board_96348gw_10,
&board_96348gw_11,
&board_FAST2404,
&board_DV201AMR,
&board_96348gw_a,
#endif
#ifdef CONFIG_BCM63XX_CPU_6358
&board_96358vw,
&board_96358vw2,
&board_AGPFS0,
#endif
};
/*
* early init callback, read nvram data from flash and checksum it
*/
void __init board_prom_init(void)
{
unsigned int check_len, i;
u8 *boot_addr, *cfe, *p;
char cfe_version[32];
u32 val;
/* read base address of boot chip select (0)
* 6345 does not have MPI but boots from standard
* MIPS Flash address */
if (BCMCPU_IS_6345())
val = 0x1fc00000;
else {
val = bcm_mpi_readl(MPI_CSBASE_REG(0));
val &= MPI_CSBASE_BASE_MASK;
}
boot_addr = (u8 *)KSEG1ADDR(val);
/* dump cfe version */
cfe = boot_addr + BCM963XX_CFE_VERSION_OFFSET;
if (!memcmp(cfe, "cfe-v", 5))
snprintf(cfe_version, sizeof(cfe_version), "%u.%u.%u-%u.%u",
cfe[5], cfe[6], cfe[7], cfe[8], cfe[9]);
else
strcpy(cfe_version, "unknown");
printk(KERN_INFO PFX "CFE version: %s\n", cfe_version);
/* extract nvram data */
memcpy(&nvram, boot_addr + BCM963XX_NVRAM_OFFSET, sizeof(nvram));
/* check checksum before using data */
if (nvram.version <= 4)
check_len = offsetof(struct bcm963xx_nvram, checksum_old);
else
check_len = sizeof(nvram);
val = 0;
p = (u8 *)&nvram;
while (check_len--)
val += *p;
if (val) {
printk(KERN_ERR PFX "invalid nvram checksum\n");
return;
}
/* find board by name */
for (i = 0; i < ARRAY_SIZE(bcm963xx_boards); i++) {
if (strncmp(nvram.name, bcm963xx_boards[i]->name,
sizeof(nvram.name)))
continue;
/* copy, board desc array is marked initdata */
memcpy(&board, bcm963xx_boards[i], sizeof(board));
break;
}
/* bail out if board is not found, will complain later */
if (!board.name[0]) {
char name[17];
memcpy(name, nvram.name, 16);
name[16] = 0;
printk(KERN_ERR PFX "unknown bcm963xx board: %s\n",
name);
return;
}
/* setup pin multiplexing depending on board enabled device,
* this has to be done this early since PCI init is done
* inside arch_initcall */
val = 0;
#ifdef CONFIG_PCI
if (board.has_pci) {
bcm63xx_pci_enabled = 1;
if (BCMCPU_IS_6348())
val |= GPIO_MODE_6348_G2_PCI;
}
#endif
if (board.has_pccard) {
if (BCMCPU_IS_6348())
val |= GPIO_MODE_6348_G1_MII_PCCARD;
}
if (board.has_enet0 && !board.enet0.use_internal_phy) {
if (BCMCPU_IS_6348())
val |= GPIO_MODE_6348_G3_EXT_MII |
GPIO_MODE_6348_G0_EXT_MII;
}
if (board.has_enet1 && !board.enet1.use_internal_phy) {
if (BCMCPU_IS_6348())
val |= GPIO_MODE_6348_G3_EXT_MII |
GPIO_MODE_6348_G0_EXT_MII;
}
bcm_gpio_writel(val, GPIO_MODE_REG);
}
/*
* second stage init callback, good time to panic if we couldn't
* identify on which board we're running since early printk is working
*/
void __init board_setup(void)
{
if (!board.name[0])
panic("unable to detect bcm963xx board");
printk(KERN_INFO PFX "board name: %s\n", board.name);
/* make sure we're running on expected cpu */
if (bcm63xx_get_cpu_id() != board.expected_cpu_id)
panic("unexpected CPU for bcm963xx board");
}
/*
* return board name for /proc/cpuinfo
*/
const char *board_get_name(void)
{
return board.name;
}
/*
* register & return a new board mac address
*/
static int board_get_mac_address(u8 *mac)
{
u8 *p;
int count;
if (mac_addr_used >= nvram.mac_addr_count) {
printk(KERN_ERR PFX "not enough mac address\n");
return -ENODEV;
}
memcpy(mac, nvram.mac_addr_base, ETH_ALEN);
p = mac + ETH_ALEN - 1;
count = mac_addr_used;
while (count--) {
do {
(*p)++;
if (*p != 0)
break;
p--;
} while (p != mac);
}
if (p == mac) {
printk(KERN_ERR PFX "unable to fetch mac address\n");
return -ENODEV;
}
mac_addr_used++;
return 0;
}
static struct mtd_partition mtd_partitions[] = {
{
.name = "cfe",
.offset = 0x0,
.size = 0x40000,
}
};
static struct physmap_flash_data flash_data = {
.width = 2,
.nr_parts = ARRAY_SIZE(mtd_partitions),
.parts = mtd_partitions,
};
static struct resource mtd_resources[] = {
{
.start = 0, /* filled at runtime */
.end = 0, /* filled at runtime */
.flags = IORESOURCE_MEM,
}
};
static struct platform_device mtd_dev = {
.name = "physmap-flash",
.resource = mtd_resources,
.num_resources = ARRAY_SIZE(mtd_resources),
.dev = {
.platform_data = &flash_data,
},
};
/*
* Register a sane SPROMv2 to make the on-board
* bcm4318 WLAN work
*/
#ifdef CONFIG_SSB_PCIHOST
static struct ssb_sprom bcm63xx_sprom = {
.revision = 0x02,
.board_rev = 0x17,
.country_code = 0x0,
.ant_available_bg = 0x3,
.pa0b0 = 0x15ae,
.pa0b1 = 0xfa85,
.pa0b2 = 0xfe8d,
.pa1b0 = 0xffff,
.pa1b1 = 0xffff,
.pa1b2 = 0xffff,
.gpio0 = 0xff,
.gpio1 = 0xff,
.gpio2 = 0xff,
.gpio3 = 0xff,
.maxpwr_bg = 0x004c,
.itssi_bg = 0x00,
.boardflags_lo = 0x2848,
.boardflags_hi = 0x0000,
};
#endif
static struct gpio_led_platform_data bcm63xx_led_data;
static struct platform_device bcm63xx_gpio_leds = {
.name = "leds-gpio",
.id = 0,
.dev.platform_data = &bcm63xx_led_data,
};
/*
* third stage init callback, register all board devices.
*/
int __init board_register_devices(void)
{
u32 val;
if (board.has_enet0 &&
!board_get_mac_address(board.enet0.mac_addr))
bcm63xx_enet_register(0, &board.enet0);
if (board.has_enet1 &&
!board_get_mac_address(board.enet1.mac_addr))
bcm63xx_enet_register(1, &board.enet1);
if (board.has_dsp)
bcm63xx_dsp_register(&board.dsp);
/* Generate MAC address for WLAN and
* register our SPROM */
#ifdef CONFIG_SSB_PCIHOST
if (!board_get_mac_address(bcm63xx_sprom.il0mac)) {
memcpy(bcm63xx_sprom.et0mac, bcm63xx_sprom.il0mac, ETH_ALEN);
memcpy(bcm63xx_sprom.et1mac, bcm63xx_sprom.il0mac, ETH_ALEN);
if (ssb_arch_set_fallback_sprom(&bcm63xx_sprom) < 0)
printk(KERN_ERR "failed to register fallback SPROM\n");
}
#endif
/* read base address of boot chip select (0) */
if (BCMCPU_IS_6345())
val = 0x1fc00000;
else {
val = bcm_mpi_readl(MPI_CSBASE_REG(0));
val &= MPI_CSBASE_BASE_MASK;
}
mtd_resources[0].start = val;
mtd_resources[0].end = 0x1FFFFFFF;
platform_device_register(&mtd_dev);
bcm63xx_led_data.num_leds = ARRAY_SIZE(board.leds);
bcm63xx_led_data.leds = board.leds;
platform_device_register(&bcm63xx_gpio_leds);
return 0;
}

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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
*/
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <bcm63xx_cpu.h>
#include <bcm63xx_io.h>
#include <bcm63xx_regs.h>
#include <bcm63xx_clk.h>
static DEFINE_MUTEX(clocks_mutex);
static void clk_enable_unlocked(struct clk *clk)
{
if (clk->set && (clk->usage++) == 0)
clk->set(clk, 1);
}
static void clk_disable_unlocked(struct clk *clk)
{
if (clk->set && (--clk->usage) == 0)
clk->set(clk, 0);
}
static void bcm_hwclock_set(u32 mask, int enable)
{
u32 reg;
reg = bcm_perf_readl(PERF_CKCTL_REG);
if (enable)
reg |= mask;
else
reg &= ~mask;
bcm_perf_writel(reg, PERF_CKCTL_REG);
}
/*
* Ethernet MAC "misc" clock: dma clocks and main clock on 6348
*/
static void enet_misc_set(struct clk *clk, int enable)
{
u32 mask;
if (BCMCPU_IS_6338())
mask = CKCTL_6338_ENET_EN;
else if (BCMCPU_IS_6345())
mask = CKCTL_6345_ENET_EN;
else if (BCMCPU_IS_6348())
mask = CKCTL_6348_ENET_EN;
else
/* BCMCPU_IS_6358 */
mask = CKCTL_6358_EMUSB_EN;
bcm_hwclock_set(mask, enable);
}
static struct clk clk_enet_misc = {
.set = enet_misc_set,
};
/*
* Ethernet MAC clocks: only revelant on 6358, silently enable misc
* clocks
*/
static void enetx_set(struct clk *clk, int enable)
{
if (enable)
clk_enable_unlocked(&clk_enet_misc);
else
clk_disable_unlocked(&clk_enet_misc);
if (BCMCPU_IS_6358()) {
u32 mask;
if (clk->id == 0)
mask = CKCTL_6358_ENET0_EN;
else
mask = CKCTL_6358_ENET1_EN;
bcm_hwclock_set(mask, enable);
}
}
static struct clk clk_enet0 = {
.id = 0,
.set = enetx_set,
};
static struct clk clk_enet1 = {
.id = 1,
.set = enetx_set,
};
/*
* Ethernet PHY clock
*/
static void ephy_set(struct clk *clk, int enable)
{
if (!BCMCPU_IS_6358())
return;
bcm_hwclock_set(CKCTL_6358_EPHY_EN, enable);
}
static struct clk clk_ephy = {
.set = ephy_set,
};
/*
* PCM clock
*/
static void pcm_set(struct clk *clk, int enable)
{
if (!BCMCPU_IS_6358())
return;
bcm_hwclock_set(CKCTL_6358_PCM_EN, enable);
}
static struct clk clk_pcm = {
.set = pcm_set,
};
/*
* USB host clock
*/
static void usbh_set(struct clk *clk, int enable)
{
if (!BCMCPU_IS_6348())
return;
bcm_hwclock_set(CKCTL_6348_USBH_EN, enable);
}
static struct clk clk_usbh = {
.set = usbh_set,
};
/*
* SPI clock
*/
static void spi_set(struct clk *clk, int enable)
{
u32 mask;
if (BCMCPU_IS_6338())
mask = CKCTL_6338_SPI_EN;
else if (BCMCPU_IS_6348())
mask = CKCTL_6348_SPI_EN;
else
/* BCMCPU_IS_6358 */
mask = CKCTL_6358_SPI_EN;
bcm_hwclock_set(mask, enable);
}
static struct clk clk_spi = {
.set = spi_set,
};
/*
* Internal peripheral clock
*/
static struct clk clk_periph = {
.rate = (50 * 1000 * 1000),
};
/*
* Linux clock API implementation
*/
int clk_enable(struct clk *clk)
{
mutex_lock(&clocks_mutex);
clk_enable_unlocked(clk);
mutex_unlock(&clocks_mutex);
return 0;
}
EXPORT_SYMBOL(clk_enable);
void clk_disable(struct clk *clk)
{
mutex_lock(&clocks_mutex);
clk_disable_unlocked(clk);
mutex_unlock(&clocks_mutex);
}
EXPORT_SYMBOL(clk_disable);
unsigned long clk_get_rate(struct clk *clk)
{
return clk->rate;
}
EXPORT_SYMBOL(clk_get_rate);
struct clk *clk_get(struct device *dev, const char *id)
{
if (!strcmp(id, "enet0"))
return &clk_enet0;
if (!strcmp(id, "enet1"))
return &clk_enet1;
if (!strcmp(id, "ephy"))
return &clk_ephy;
if (!strcmp(id, "usbh"))
return &clk_usbh;
if (!strcmp(id, "spi"))
return &clk_spi;
if (!strcmp(id, "periph"))
return &clk_periph;
if (BCMCPU_IS_6358() && !strcmp(id, "pcm"))
return &clk_pcm;
return ERR_PTR(-ENOENT);
}
EXPORT_SYMBOL(clk_get);
void clk_put(struct clk *clk)
{
}
EXPORT_SYMBOL(clk_put);

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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
* Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/cpu.h>
#include <bcm63xx_cpu.h>
#include <bcm63xx_regs.h>
#include <bcm63xx_io.h>
#include <bcm63xx_irq.h>
const unsigned long *bcm63xx_regs_base;
EXPORT_SYMBOL(bcm63xx_regs_base);
const int *bcm63xx_irqs;
EXPORT_SYMBOL(bcm63xx_irqs);
static u16 bcm63xx_cpu_id;
static u16 bcm63xx_cpu_rev;
static unsigned int bcm63xx_cpu_freq;
static unsigned int bcm63xx_memory_size;
/*
* 6338 register sets and irqs
*/
static const unsigned long bcm96338_regs_base[] = {
[RSET_DSL_LMEM] = BCM_6338_DSL_LMEM_BASE,
[RSET_PERF] = BCM_6338_PERF_BASE,
[RSET_TIMER] = BCM_6338_TIMER_BASE,
[RSET_WDT] = BCM_6338_WDT_BASE,
[RSET_UART0] = BCM_6338_UART0_BASE,
[RSET_GPIO] = BCM_6338_GPIO_BASE,
[RSET_SPI] = BCM_6338_SPI_BASE,
[RSET_OHCI0] = BCM_6338_OHCI0_BASE,
[RSET_OHCI_PRIV] = BCM_6338_OHCI_PRIV_BASE,
[RSET_USBH_PRIV] = BCM_6338_USBH_PRIV_BASE,
[RSET_UDC0] = BCM_6338_UDC0_BASE,
[RSET_MPI] = BCM_6338_MPI_BASE,
[RSET_PCMCIA] = BCM_6338_PCMCIA_BASE,
[RSET_SDRAM] = BCM_6338_SDRAM_BASE,
[RSET_DSL] = BCM_6338_DSL_BASE,
[RSET_ENET0] = BCM_6338_ENET0_BASE,
[RSET_ENET1] = BCM_6338_ENET1_BASE,
[RSET_ENETDMA] = BCM_6338_ENETDMA_BASE,
[RSET_MEMC] = BCM_6338_MEMC_BASE,
[RSET_DDR] = BCM_6338_DDR_BASE,
};
static const int bcm96338_irqs[] = {
[IRQ_TIMER] = BCM_6338_TIMER_IRQ,
[IRQ_UART0] = BCM_6338_UART0_IRQ,
[IRQ_DSL] = BCM_6338_DSL_IRQ,
[IRQ_ENET0] = BCM_6338_ENET0_IRQ,
[IRQ_ENET_PHY] = BCM_6338_ENET_PHY_IRQ,
[IRQ_ENET0_RXDMA] = BCM_6338_ENET0_RXDMA_IRQ,
[IRQ_ENET0_TXDMA] = BCM_6338_ENET0_TXDMA_IRQ,
};
/*
* 6345 register sets and irqs
*/
static const unsigned long bcm96345_regs_base[] = {
[RSET_DSL_LMEM] = BCM_6345_DSL_LMEM_BASE,
[RSET_PERF] = BCM_6345_PERF_BASE,
[RSET_TIMER] = BCM_6345_TIMER_BASE,
[RSET_WDT] = BCM_6345_WDT_BASE,
[RSET_UART0] = BCM_6345_UART0_BASE,
[RSET_GPIO] = BCM_6345_GPIO_BASE,
[RSET_SPI] = BCM_6345_SPI_BASE,
[RSET_UDC0] = BCM_6345_UDC0_BASE,
[RSET_OHCI0] = BCM_6345_OHCI0_BASE,
[RSET_OHCI_PRIV] = BCM_6345_OHCI_PRIV_BASE,
[RSET_USBH_PRIV] = BCM_6345_USBH_PRIV_BASE,
[RSET_MPI] = BCM_6345_MPI_BASE,
[RSET_PCMCIA] = BCM_6345_PCMCIA_BASE,
[RSET_DSL] = BCM_6345_DSL_BASE,
[RSET_ENET0] = BCM_6345_ENET0_BASE,
[RSET_ENET1] = BCM_6345_ENET1_BASE,
[RSET_ENETDMA] = BCM_6345_ENETDMA_BASE,
[RSET_EHCI0] = BCM_6345_EHCI0_BASE,
[RSET_SDRAM] = BCM_6345_SDRAM_BASE,
[RSET_MEMC] = BCM_6345_MEMC_BASE,
[RSET_DDR] = BCM_6345_DDR_BASE,
};
static const int bcm96345_irqs[] = {
[IRQ_TIMER] = BCM_6345_TIMER_IRQ,
[IRQ_UART0] = BCM_6345_UART0_IRQ,
[IRQ_DSL] = BCM_6345_DSL_IRQ,
[IRQ_ENET0] = BCM_6345_ENET0_IRQ,
[IRQ_ENET_PHY] = BCM_6345_ENET_PHY_IRQ,
[IRQ_ENET0_RXDMA] = BCM_6345_ENET0_RXDMA_IRQ,
[IRQ_ENET0_TXDMA] = BCM_6345_ENET0_TXDMA_IRQ,
};
/*
* 6348 register sets and irqs
*/
static const unsigned long bcm96348_regs_base[] = {
[RSET_DSL_LMEM] = BCM_6348_DSL_LMEM_BASE,
[RSET_PERF] = BCM_6348_PERF_BASE,
[RSET_TIMER] = BCM_6348_TIMER_BASE,
[RSET_WDT] = BCM_6348_WDT_BASE,
[RSET_UART0] = BCM_6348_UART0_BASE,
[RSET_GPIO] = BCM_6348_GPIO_BASE,
[RSET_SPI] = BCM_6348_SPI_BASE,
[RSET_OHCI0] = BCM_6348_OHCI0_BASE,
[RSET_OHCI_PRIV] = BCM_6348_OHCI_PRIV_BASE,
[RSET_USBH_PRIV] = BCM_6348_USBH_PRIV_BASE,
[RSET_MPI] = BCM_6348_MPI_BASE,
[RSET_PCMCIA] = BCM_6348_PCMCIA_BASE,
[RSET_SDRAM] = BCM_6348_SDRAM_BASE,
[RSET_DSL] = BCM_6348_DSL_BASE,
[RSET_ENET0] = BCM_6348_ENET0_BASE,
[RSET_ENET1] = BCM_6348_ENET1_BASE,
[RSET_ENETDMA] = BCM_6348_ENETDMA_BASE,
[RSET_MEMC] = BCM_6348_MEMC_BASE,
[RSET_DDR] = BCM_6348_DDR_BASE,
};
static const int bcm96348_irqs[] = {
[IRQ_TIMER] = BCM_6348_TIMER_IRQ,
[IRQ_UART0] = BCM_6348_UART0_IRQ,
[IRQ_DSL] = BCM_6348_DSL_IRQ,
[IRQ_ENET0] = BCM_6348_ENET0_IRQ,
[IRQ_ENET1] = BCM_6348_ENET1_IRQ,
[IRQ_ENET_PHY] = BCM_6348_ENET_PHY_IRQ,
[IRQ_OHCI0] = BCM_6348_OHCI0_IRQ,
[IRQ_PCMCIA] = BCM_6348_PCMCIA_IRQ,
[IRQ_ENET0_RXDMA] = BCM_6348_ENET0_RXDMA_IRQ,
[IRQ_ENET0_TXDMA] = BCM_6348_ENET0_TXDMA_IRQ,
[IRQ_ENET1_RXDMA] = BCM_6348_ENET1_RXDMA_IRQ,
[IRQ_ENET1_TXDMA] = BCM_6348_ENET1_TXDMA_IRQ,
[IRQ_PCI] = BCM_6348_PCI_IRQ,
};
/*
* 6358 register sets and irqs
*/
static const unsigned long bcm96358_regs_base[] = {
[RSET_DSL_LMEM] = BCM_6358_DSL_LMEM_BASE,
[RSET_PERF] = BCM_6358_PERF_BASE,
[RSET_TIMER] = BCM_6358_TIMER_BASE,
[RSET_WDT] = BCM_6358_WDT_BASE,
[RSET_UART0] = BCM_6358_UART0_BASE,
[RSET_GPIO] = BCM_6358_GPIO_BASE,
[RSET_SPI] = BCM_6358_SPI_BASE,
[RSET_OHCI0] = BCM_6358_OHCI0_BASE,
[RSET_EHCI0] = BCM_6358_EHCI0_BASE,
[RSET_OHCI_PRIV] = BCM_6358_OHCI_PRIV_BASE,
[RSET_USBH_PRIV] = BCM_6358_USBH_PRIV_BASE,
[RSET_MPI] = BCM_6358_MPI_BASE,
[RSET_PCMCIA] = BCM_6358_PCMCIA_BASE,
[RSET_SDRAM] = BCM_6358_SDRAM_BASE,
[RSET_DSL] = BCM_6358_DSL_BASE,
[RSET_ENET0] = BCM_6358_ENET0_BASE,
[RSET_ENET1] = BCM_6358_ENET1_BASE,
[RSET_ENETDMA] = BCM_6358_ENETDMA_BASE,
[RSET_MEMC] = BCM_6358_MEMC_BASE,
[RSET_DDR] = BCM_6358_DDR_BASE,
};
static const int bcm96358_irqs[] = {
[IRQ_TIMER] = BCM_6358_TIMER_IRQ,
[IRQ_UART0] = BCM_6358_UART0_IRQ,
[IRQ_DSL] = BCM_6358_DSL_IRQ,
[IRQ_ENET0] = BCM_6358_ENET0_IRQ,
[IRQ_ENET1] = BCM_6358_ENET1_IRQ,
[IRQ_ENET_PHY] = BCM_6358_ENET_PHY_IRQ,
[IRQ_OHCI0] = BCM_6358_OHCI0_IRQ,
[IRQ_EHCI0] = BCM_6358_EHCI0_IRQ,
[IRQ_PCMCIA] = BCM_6358_PCMCIA_IRQ,
[IRQ_ENET0_RXDMA] = BCM_6358_ENET0_RXDMA_IRQ,
[IRQ_ENET0_TXDMA] = BCM_6358_ENET0_TXDMA_IRQ,
[IRQ_ENET1_RXDMA] = BCM_6358_ENET1_RXDMA_IRQ,
[IRQ_ENET1_TXDMA] = BCM_6358_ENET1_TXDMA_IRQ,
[IRQ_PCI] = BCM_6358_PCI_IRQ,
};
u16 __bcm63xx_get_cpu_id(void)
{
return bcm63xx_cpu_id;
}
EXPORT_SYMBOL(__bcm63xx_get_cpu_id);
u16 bcm63xx_get_cpu_rev(void)
{
return bcm63xx_cpu_rev;
}
EXPORT_SYMBOL(bcm63xx_get_cpu_rev);
unsigned int bcm63xx_get_cpu_freq(void)
{
return bcm63xx_cpu_freq;
}
unsigned int bcm63xx_get_memory_size(void)
{
return bcm63xx_memory_size;
}
static unsigned int detect_cpu_clock(void)
{
unsigned int tmp, n1 = 0, n2 = 0, m1 = 0;
/* BCM6338 has a fixed 240 Mhz frequency */
if (BCMCPU_IS_6338())
return 240000000;
/* BCM6345 has a fixed 140Mhz frequency */
if (BCMCPU_IS_6345())
return 140000000;
/*
* frequency depends on PLL configuration:
*/
if (BCMCPU_IS_6348()) {
/* 16MHz * (N1 + 1) * (N2 + 2) / (M1_CPU + 1) */
tmp = bcm_perf_readl(PERF_MIPSPLLCTL_REG);
n1 = (tmp & MIPSPLLCTL_N1_MASK) >> MIPSPLLCTL_N1_SHIFT;
n2 = (tmp & MIPSPLLCTL_N2_MASK) >> MIPSPLLCTL_N2_SHIFT;
m1 = (tmp & MIPSPLLCTL_M1CPU_MASK) >> MIPSPLLCTL_M1CPU_SHIFT;
n1 += 1;
n2 += 2;
m1 += 1;
}
if (BCMCPU_IS_6358()) {
/* 16MHz * N1 * N2 / M1_CPU */
tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_REG);
n1 = (tmp & DMIPSPLLCFG_N1_MASK) >> DMIPSPLLCFG_N1_SHIFT;
n2 = (tmp & DMIPSPLLCFG_N2_MASK) >> DMIPSPLLCFG_N2_SHIFT;
m1 = (tmp & DMIPSPLLCFG_M1_MASK) >> DMIPSPLLCFG_M1_SHIFT;
}
return (16 * 1000000 * n1 * n2) / m1;
}
/*
* attempt to detect the amount of memory installed
*/
static unsigned int detect_memory_size(void)
{
unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
u32 val;
if (BCMCPU_IS_6345())
return (8 * 1024 * 1024);
if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) {
val = bcm_sdram_readl(SDRAM_CFG_REG);
rows = (val & SDRAM_CFG_ROW_MASK) >> SDRAM_CFG_ROW_SHIFT;
cols = (val & SDRAM_CFG_COL_MASK) >> SDRAM_CFG_COL_SHIFT;
is_32bits = (val & SDRAM_CFG_32B_MASK) ? 1 : 0;
banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1;
}
if (BCMCPU_IS_6358()) {
val = bcm_memc_readl(MEMC_CFG_REG);
rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT;
cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT;
is_32bits = (val & MEMC_CFG_32B_MASK) ? 0 : 1;
banks = 2;
}
/* 0 => 11 address bits ... 2 => 13 address bits */
rows += 11;
/* 0 => 8 address bits ... 2 => 10 address bits */
cols += 8;
return 1 << (cols + rows + (is_32bits + 1) + banks);
}
void __init bcm63xx_cpu_init(void)
{
unsigned int tmp, expected_cpu_id;
struct cpuinfo_mips *c = &current_cpu_data;
/* soc registers location depends on cpu type */
expected_cpu_id = 0;
switch (c->cputype) {
/*
* BCM6338 as the same PrId as BCM3302 see arch/mips/kernel/cpu-probe.c
*/
case CPU_BCM3302:
expected_cpu_id = BCM6338_CPU_ID;
bcm63xx_regs_base = bcm96338_regs_base;
bcm63xx_irqs = bcm96338_irqs;
break;
case CPU_BCM6345:
expected_cpu_id = BCM6345_CPU_ID;
bcm63xx_regs_base = bcm96345_regs_base;
bcm63xx_irqs = bcm96345_irqs;
break;
case CPU_BCM6348:
expected_cpu_id = BCM6348_CPU_ID;
bcm63xx_regs_base = bcm96348_regs_base;
bcm63xx_irqs = bcm96348_irqs;
break;
case CPU_BCM6358:
expected_cpu_id = BCM6358_CPU_ID;
bcm63xx_regs_base = bcm96358_regs_base;
bcm63xx_irqs = bcm96358_irqs;
break;
}
/*
* really early to panic, but delaying panic would not help since we
* will never get any working console
*/
if (!expected_cpu_id)
panic("unsupported Broadcom CPU");
/*
* bcm63xx_regs_base is set, we can access soc registers
*/
/* double check CPU type */
tmp = bcm_perf_readl(PERF_REV_REG);
bcm63xx_cpu_id = (tmp & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT;
bcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT;
if (bcm63xx_cpu_id != expected_cpu_id)
panic("bcm63xx CPU id mismatch");
bcm63xx_cpu_freq = detect_cpu_clock();
bcm63xx_memory_size = detect_memory_size();
printk(KERN_INFO "Detected Broadcom 0x%04x CPU revision %02x\n",
bcm63xx_cpu_id, bcm63xx_cpu_rev);
printk(KERN_INFO "CPU frequency is %u MHz\n",
bcm63xx_cpu_freq / 1000000);
printk(KERN_INFO "%uMB of RAM installed\n",
bcm63xx_memory_size >> 20);
}

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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/spinlock.h>
#include <linux/log2.h>
#include <bcm63xx_cpu.h>
#include <bcm63xx_io.h>
#include <bcm63xx_regs.h>
#include <bcm63xx_cs.h>
static DEFINE_SPINLOCK(bcm63xx_cs_lock);
/*
* check if given chip select exists
*/
static int is_valid_cs(unsigned int cs)
{
if (cs > 6)
return 0;
return 1;
}
/*
* Configure chipselect base address and size (bytes).
* Size must be a power of two between 8k and 256M.
*/
int bcm63xx_set_cs_base(unsigned int cs, u32 base, unsigned int size)
{
unsigned long flags;
u32 val;
if (!is_valid_cs(cs))
return -EINVAL;
/* sanity check on size */
if (size != roundup_pow_of_two(size))
return -EINVAL;
if (size < 8 * 1024 || size > 256 * 1024 * 1024)
return -EINVAL;
val = (base & MPI_CSBASE_BASE_MASK);
/* 8k => 0 - 256M => 15 */
val |= (ilog2(size) - ilog2(8 * 1024)) << MPI_CSBASE_SIZE_SHIFT;
spin_lock_irqsave(&bcm63xx_cs_lock, flags);
bcm_mpi_writel(val, MPI_CSBASE_REG(cs));
spin_unlock_irqrestore(&bcm63xx_cs_lock, flags);
return 0;
}
EXPORT_SYMBOL(bcm63xx_set_cs_base);
/*
* configure chipselect timing (ns)
*/
int bcm63xx_set_cs_timing(unsigned int cs, unsigned int wait,
unsigned int setup, unsigned int hold)
{
unsigned long flags;
u32 val;
if (!is_valid_cs(cs))
return -EINVAL;
spin_lock_irqsave(&bcm63xx_cs_lock, flags);
val = bcm_mpi_readl(MPI_CSCTL_REG(cs));
val &= ~(MPI_CSCTL_WAIT_MASK);
val &= ~(MPI_CSCTL_SETUP_MASK);
val &= ~(MPI_CSCTL_HOLD_MASK);
val |= wait << MPI_CSCTL_WAIT_SHIFT;
val |= setup << MPI_CSCTL_SETUP_SHIFT;
val |= hold << MPI_CSCTL_HOLD_SHIFT;
bcm_mpi_writel(val, MPI_CSCTL_REG(cs));
spin_unlock_irqrestore(&bcm63xx_cs_lock, flags);
return 0;
}
EXPORT_SYMBOL(bcm63xx_set_cs_timing);
/*
* configure other chipselect parameter (data bus size, ...)
*/
int bcm63xx_set_cs_param(unsigned int cs, u32 params)
{
unsigned long flags;
u32 val;
if (!is_valid_cs(cs))
return -EINVAL;
/* none of this fields apply to pcmcia */
if (cs == MPI_CS_PCMCIA_COMMON ||
cs == MPI_CS_PCMCIA_ATTR ||
cs == MPI_CS_PCMCIA_IO)
return -EINVAL;
spin_lock_irqsave(&bcm63xx_cs_lock, flags);
val = bcm_mpi_readl(MPI_CSCTL_REG(cs));
val &= ~(MPI_CSCTL_DATA16_MASK);
val &= ~(MPI_CSCTL_SYNCMODE_MASK);
val &= ~(MPI_CSCTL_TSIZE_MASK);
val &= ~(MPI_CSCTL_ENDIANSWAP_MASK);
val |= params;
bcm_mpi_writel(val, MPI_CSCTL_REG(cs));
spin_unlock_irqrestore(&bcm63xx_cs_lock, flags);
return 0;
}
EXPORT_SYMBOL(bcm63xx_set_cs_param);
/*
* set cs status (enable/disable)
*/
int bcm63xx_set_cs_status(unsigned int cs, int enable)
{
unsigned long flags;
u32 val;
if (!is_valid_cs(cs))
return -EINVAL;
spin_lock_irqsave(&bcm63xx_cs_lock, flags);
val = bcm_mpi_readl(MPI_CSCTL_REG(cs));
if (enable)
val |= MPI_CSCTL_ENABLE_MASK;
else
val &= ~MPI_CSCTL_ENABLE_MASK;
bcm_mpi_writel(val, MPI_CSCTL_REG(cs));
spin_unlock_irqrestore(&bcm63xx_cs_lock, flags);
return 0;
}
EXPORT_SYMBOL(bcm63xx_set_cs_status);

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arch/mips/bcm63xx/dev-dsp.c Normal file
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/*
* Broadcom BCM63xx VoIP DSP registration
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <bcm63xx_cpu.h>
#include <bcm63xx_dev_dsp.h>
#include <bcm63xx_regs.h>
#include <bcm63xx_io.h>
static struct resource voip_dsp_resources[] = {
{
.start = -1, /* filled at runtime */
.end = -1, /* filled at runtime */
.flags = IORESOURCE_MEM,
},
{
.start = -1, /* filled at runtime */
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device bcm63xx_voip_dsp_device = {
.name = "bcm63xx-voip-dsp",
.id = 0,
.num_resources = ARRAY_SIZE(voip_dsp_resources),
.resource = voip_dsp_resources,
};
int __init bcm63xx_dsp_register(const struct bcm63xx_dsp_platform_data *pd)
{
struct bcm63xx_dsp_platform_data *dpd;
u32 val;
/* Get the memory window */
val = bcm_mpi_readl(MPI_CSBASE_REG(pd->cs - 1));
val &= MPI_CSBASE_BASE_MASK;
voip_dsp_resources[0].start = val;
voip_dsp_resources[0].end = val + 0xFFFFFFF;
voip_dsp_resources[1].start = pd->ext_irq;
/* copy given platform data */
dpd = bcm63xx_voip_dsp_device.dev.platform_data;
memcpy(dpd, pd, sizeof (*pd));
return platform_device_register(&bcm63xx_voip_dsp_device);
}

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arch/mips/bcm63xx/early_printk.c Normal file
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
*/
#include <linux/init.h>
#include <bcm63xx_io.h>
#include <bcm63xx_regs.h>
static void __init wait_xfered(void)
{
unsigned int val;
/* wait for any previous char to be transmitted */
do {
val = bcm_uart0_readl(UART_IR_REG);
if (val & UART_IR_STAT(UART_IR_TXEMPTY))
break;
} while (1);
}
void __init prom_putchar(char c)
{
wait_xfered();
bcm_uart0_writel(c, UART_FIFO_REG);
wait_xfered();
}

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arch/mips/bcm63xx/gpio.c Normal file
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
* Copyright (C) 2008 Florian Fainelli <florian@openwrt.org>
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/spinlock.h>
#include <linux/platform_device.h>
#include <linux/gpio.h>
#include <bcm63xx_cpu.h>
#include <bcm63xx_gpio.h>
#include <bcm63xx_io.h>
#include <bcm63xx_regs.h>
static DEFINE_SPINLOCK(bcm63xx_gpio_lock);
static u32 gpio_out_low, gpio_out_high;
static void bcm63xx_gpio_set(struct gpio_chip *chip,
unsigned gpio, int val)
{
u32 reg;
u32 mask;
u32 *v;
unsigned long flags;
if (gpio >= chip->ngpio)
BUG();
if (gpio < 32) {
reg = GPIO_DATA_LO_REG;
mask = 1 << gpio;
v = &gpio_out_low;
} else {
reg = GPIO_DATA_HI_REG;
mask = 1 << (gpio - 32);
v = &gpio_out_high;
}
spin_lock_irqsave(&bcm63xx_gpio_lock, flags);
if (val)
*v |= mask;
else
*v &= ~mask;
bcm_gpio_writel(*v, reg);
spin_unlock_irqrestore(&bcm63xx_gpio_lock, flags);
}
static int bcm63xx_gpio_get(struct gpio_chip *chip, unsigned gpio)
{
u32 reg;
u32 mask;
if (gpio >= chip->ngpio)
BUG();
if (gpio < 32) {
reg = GPIO_DATA_LO_REG;
mask = 1 << gpio;
} else {
reg = GPIO_DATA_HI_REG;
mask = 1 << (gpio - 32);
}
return !!(bcm_gpio_readl(reg) & mask);
}
static int bcm63xx_gpio_set_direction(struct gpio_chip *chip,
unsigned gpio, int dir)
{
u32 reg;
u32 mask;
u32 tmp;
unsigned long flags;
if (gpio >= chip->ngpio)
BUG();
if (gpio < 32) {
reg = GPIO_CTL_LO_REG;
mask = 1 << gpio;
} else {
reg = GPIO_CTL_HI_REG;
mask = 1 << (gpio - 32);
}
spin_lock_irqsave(&bcm63xx_gpio_lock, flags);
tmp = bcm_gpio_readl(reg);
if (dir == GPIO_DIR_IN)
tmp &= ~mask;
else
tmp |= mask;
bcm_gpio_writel(tmp, reg);
spin_unlock_irqrestore(&bcm63xx_gpio_lock, flags);
return 0;
}
static int bcm63xx_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
{
return bcm63xx_gpio_set_direction(chip, gpio, GPIO_DIR_IN);
}
static int bcm63xx_gpio_direction_output(struct gpio_chip *chip,
unsigned gpio, int value)
{
bcm63xx_gpio_set(chip, gpio, value);
return bcm63xx_gpio_set_direction(chip, gpio, GPIO_DIR_OUT);
}
static struct gpio_chip bcm63xx_gpio_chip = {
.label = "bcm63xx-gpio",
.direction_input = bcm63xx_gpio_direction_input,
.direction_output = bcm63xx_gpio_direction_output,
.get = bcm63xx_gpio_get,
.set = bcm63xx_gpio_set,
.base = 0,
};
int __init bcm63xx_gpio_init(void)
{
bcm63xx_gpio_chip.ngpio = bcm63xx_gpio_count();
pr_info("registering %d GPIOs\n", bcm63xx_gpio_chip.ngpio);
return gpiochip_add(&bcm63xx_gpio_chip);
}
arch_initcall(bcm63xx_gpio_init);

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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
* Copyright (C) 2008 Nicolas Schichan <nschichan@freebox.fr>
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <asm/irq_cpu.h>
#include <asm/mipsregs.h>
#include <bcm63xx_cpu.h>
#include <bcm63xx_regs.h>
#include <bcm63xx_io.h>
#include <bcm63xx_irq.h>
/*
* dispatch internal devices IRQ (uart, enet, watchdog, ...). do not
* prioritize any interrupt relatively to another. the static counter
* will resume the loop where it ended the last time we left this
* function.
*/
static void bcm63xx_irq_dispatch_internal(void)
{
u32 pending;
static int i;
pending = bcm_perf_readl(PERF_IRQMASK_REG) &
bcm_perf_readl(PERF_IRQSTAT_REG);
if (!pending)
return ;
while (1) {
int to_call = i;
i = (i + 1) & 0x1f;
if (pending & (1 << to_call)) {
do_IRQ(to_call + IRQ_INTERNAL_BASE);
break;
}
}
}
asmlinkage void plat_irq_dispatch(void)
{
u32 cause;
do {
cause = read_c0_cause() & read_c0_status() & ST0_IM;
if (!cause)
break;
if (cause & CAUSEF_IP7)
do_IRQ(7);
if (cause & CAUSEF_IP2)
bcm63xx_irq_dispatch_internal();
if (cause & CAUSEF_IP3)
do_IRQ(IRQ_EXT_0);
if (cause & CAUSEF_IP4)
do_IRQ(IRQ_EXT_1);
if (cause & CAUSEF_IP5)
do_IRQ(IRQ_EXT_2);
if (cause & CAUSEF_IP6)
do_IRQ(IRQ_EXT_3);
} while (1);
}
/*
* internal IRQs operations: only mask/unmask on PERF irq mask
* register.
*/
static inline void bcm63xx_internal_irq_mask(unsigned int irq)
{
u32 mask;
irq -= IRQ_INTERNAL_BASE;
mask = bcm_perf_readl(PERF_IRQMASK_REG);
mask &= ~(1 << irq);
bcm_perf_writel(mask, PERF_IRQMASK_REG);
}
static void bcm63xx_internal_irq_unmask(unsigned int irq)
{
u32 mask;
irq -= IRQ_INTERNAL_BASE;
mask = bcm_perf_readl(PERF_IRQMASK_REG);
mask |= (1 << irq);
bcm_perf_writel(mask, PERF_IRQMASK_REG);
}
static unsigned int bcm63xx_internal_irq_startup(unsigned int irq)
{
bcm63xx_internal_irq_unmask(irq);
return 0;
}
/*
* external IRQs operations: mask/unmask and clear on PERF external
* irq control register.
*/
static void bcm63xx_external_irq_mask(unsigned int irq)
{
u32 reg;
irq -= IRQ_EXT_BASE;
reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
reg &= ~EXTIRQ_CFG_MASK(irq);
bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
}
static void bcm63xx_external_irq_unmask(unsigned int irq)
{
u32 reg;
irq -= IRQ_EXT_BASE;
reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
reg |= EXTIRQ_CFG_MASK(irq);
bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
}
static void bcm63xx_external_irq_clear(unsigned int irq)
{
u32 reg;
irq -= IRQ_EXT_BASE;
reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
reg |= EXTIRQ_CFG_CLEAR(irq);
bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
}
static unsigned int bcm63xx_external_irq_startup(unsigned int irq)
{
set_c0_status(0x100 << (irq - IRQ_MIPS_BASE));
irq_enable_hazard();
bcm63xx_external_irq_unmask(irq);
return 0;
}
static void bcm63xx_external_irq_shutdown(unsigned int irq)
{
bcm63xx_external_irq_mask(irq);
clear_c0_status(0x100 << (irq - IRQ_MIPS_BASE));
irq_disable_hazard();
}
static int bcm63xx_external_irq_set_type(unsigned int irq,
unsigned int flow_type)
{
u32 reg;
struct irq_desc *desc = irq_desc + irq;
irq -= IRQ_EXT_BASE;
flow_type &= IRQ_TYPE_SENSE_MASK;
if (flow_type == IRQ_TYPE_NONE)
flow_type = IRQ_TYPE_LEVEL_LOW;
reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
switch (flow_type) {
case IRQ_TYPE_EDGE_BOTH:
reg &= ~EXTIRQ_CFG_LEVELSENSE(irq);
reg |= EXTIRQ_CFG_BOTHEDGE(irq);
break;
case IRQ_TYPE_EDGE_RISING:
reg &= ~EXTIRQ_CFG_LEVELSENSE(irq);
reg |= EXTIRQ_CFG_SENSE(irq);
reg &= ~EXTIRQ_CFG_BOTHEDGE(irq);
break;
case IRQ_TYPE_EDGE_FALLING:
reg &= ~EXTIRQ_CFG_LEVELSENSE(irq);
reg &= ~EXTIRQ_CFG_SENSE(irq);
reg &= ~EXTIRQ_CFG_BOTHEDGE(irq);
break;
case IRQ_TYPE_LEVEL_HIGH:
reg |= EXTIRQ_CFG_LEVELSENSE(irq);
reg |= EXTIRQ_CFG_SENSE(irq);
break;
case IRQ_TYPE_LEVEL_LOW:
reg |= EXTIRQ_CFG_LEVELSENSE(irq);
reg &= ~EXTIRQ_CFG_SENSE(irq);
break;
default:
printk(KERN_ERR "bogus flow type combination given !\n");
return -EINVAL;
}
bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) {
desc->status |= IRQ_LEVEL;
desc->handle_irq = handle_level_irq;
} else {
desc->handle_irq = handle_edge_irq;
}
return 0;
}
static struct irq_chip bcm63xx_internal_irq_chip = {
.name = "bcm63xx_ipic",
.startup = bcm63xx_internal_irq_startup,
.shutdown = bcm63xx_internal_irq_mask,
.mask = bcm63xx_internal_irq_mask,
.mask_ack = bcm63xx_internal_irq_mask,
.unmask = bcm63xx_internal_irq_unmask,
};
static struct irq_chip bcm63xx_external_irq_chip = {
.name = "bcm63xx_epic",
.startup = bcm63xx_external_irq_startup,
.shutdown = bcm63xx_external_irq_shutdown,
.ack = bcm63xx_external_irq_clear,
.mask = bcm63xx_external_irq_mask,
.unmask = bcm63xx_external_irq_unmask,
.set_type = bcm63xx_external_irq_set_type,
};
static struct irqaction cpu_ip2_cascade_action = {
.handler = no_action,
.name = "cascade_ip2",
};
void __init arch_init_irq(void)
{
int i;
mips_cpu_irq_init();
for (i = IRQ_INTERNAL_BASE; i < NR_IRQS; ++i)
set_irq_chip_and_handler(i, &bcm63xx_internal_irq_chip,
handle_level_irq);
for (i = IRQ_EXT_BASE; i < IRQ_EXT_BASE + 4; ++i)
set_irq_chip_and_handler(i, &bcm63xx_external_irq_chip,
handle_edge_irq);
setup_irq(IRQ_MIPS_BASE + 2, &cpu_ip2_cascade_action);
}

55
arch/mips/bcm63xx/prom.c Normal file
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
*/
#include <linux/init.h>
#include <linux/bootmem.h>
#include <asm/bootinfo.h>
#include <bcm63xx_board.h>
#include <bcm63xx_cpu.h>
#include <bcm63xx_io.h>
#include <bcm63xx_regs.h>
#include <bcm63xx_gpio.h>
void __init prom_init(void)
{
u32 reg, mask;
bcm63xx_cpu_init();
/* stop any running watchdog */
bcm_wdt_writel(WDT_STOP_1, WDT_CTL_REG);
bcm_wdt_writel(WDT_STOP_2, WDT_CTL_REG);
/* disable all hardware blocks clock for now */
if (BCMCPU_IS_6338())
mask = CKCTL_6338_ALL_SAFE_EN;
else if (BCMCPU_IS_6345())
mask = CKCTL_6345_ALL_SAFE_EN;
else if (BCMCPU_IS_6348())
mask = CKCTL_6348_ALL_SAFE_EN;
else
/* BCMCPU_IS_6358() */
mask = CKCTL_6358_ALL_SAFE_EN;
reg = bcm_perf_readl(PERF_CKCTL_REG);
reg &= ~mask;
bcm_perf_writel(reg, PERF_CKCTL_REG);
/* assign command line from kernel config */
strcpy(arcs_cmdline, CONFIG_CMDLINE);
/* register gpiochip */
bcm63xx_gpio_init();
/* do low level board init */
board_prom_init();
}
void __init prom_free_prom_memory(void)
{
}

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arch/mips/bcm63xx/setup.c Normal file
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/bootmem.h>
#include <linux/ioport.h>
#include <linux/pm.h>
#include <asm/bootinfo.h>
#include <asm/time.h>
#include <asm/reboot.h>
#include <asm/cacheflush.h>
#include <bcm63xx_board.h>
#include <bcm63xx_cpu.h>
#include <bcm63xx_regs.h>
#include <bcm63xx_io.h>
void bcm63xx_machine_halt(void)
{
printk(KERN_INFO "System halted\n");
while (1)
;
}
static void bcm6348_a1_reboot(void)
{
u32 reg;
/* soft reset all blocks */
printk(KERN_INFO "soft-reseting all blocks ...\n");
reg = bcm_perf_readl(PERF_SOFTRESET_REG);
reg &= ~SOFTRESET_6348_ALL;
bcm_perf_writel(reg, PERF_SOFTRESET_REG);
mdelay(10);
reg = bcm_perf_readl(PERF_SOFTRESET_REG);
reg |= SOFTRESET_6348_ALL;
bcm_perf_writel(reg, PERF_SOFTRESET_REG);
mdelay(10);
/* Jump to the power on address. */
printk(KERN_INFO "jumping to reset vector.\n");
/* set high vectors (base at 0xbfc00000 */
set_c0_status(ST0_BEV | ST0_ERL);
/* run uncached in kseg0 */
change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
__flush_cache_all();
/* remove all wired TLB entries */
write_c0_wired(0);
__asm__ __volatile__(
"jr\t%0"
:
: "r" (0xbfc00000));
while (1)
;
}
void bcm63xx_machine_reboot(void)
{
u32 reg;
/* mask and clear all external irq */
reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
reg &= ~EXTIRQ_CFG_MASK_ALL;
reg |= EXTIRQ_CFG_CLEAR_ALL;
bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
if (BCMCPU_IS_6348() && (bcm63xx_get_cpu_rev() == 0xa1))
bcm6348_a1_reboot();
printk(KERN_INFO "triggering watchdog soft-reset...\n");
bcm_perf_writel(SYS_PLL_SOFT_RESET, PERF_SYS_PLL_CTL_REG);
while (1)
;
}
static void __bcm63xx_machine_reboot(char *p)
{
bcm63xx_machine_reboot();
}
/*
* return system type in /proc/cpuinfo
*/
const char *get_system_type(void)
{
static char buf[128];
snprintf(buf, sizeof(buf), "bcm63xx/%s (0x%04x/0x%04X)",
board_get_name(),
bcm63xx_get_cpu_id(), bcm63xx_get_cpu_rev());
return buf;
}
void __init plat_time_init(void)
{
mips_hpt_frequency = bcm63xx_get_cpu_freq() / 2;
}
void __init plat_mem_setup(void)
{
add_memory_region(0, bcm63xx_get_memory_size(), BOOT_MEM_RAM);
_machine_halt = bcm63xx_machine_halt;
_machine_restart = __bcm63xx_machine_reboot;
pm_power_off = bcm63xx_machine_halt;
set_io_port_base(0);
ioport_resource.start = 0;
ioport_resource.end = ~0;
board_setup();
}
int __init bcm63xx_register_devices(void)
{
return board_register_devices();
}
arch_initcall(bcm63xx_register_devices);

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arch/mips/bcm63xx/timer.c Normal file
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
*/
#include <linux/kernel.h>
#include <linux/err.h>
#include <linux/module.h>
#include <linux/spinlock.h>
#include <linux/interrupt.h>
#include <linux/clk.h>
#include <bcm63xx_cpu.h>
#include <bcm63xx_io.h>
#include <bcm63xx_timer.h>
#include <bcm63xx_regs.h>
static DEFINE_SPINLOCK(timer_reg_lock);
static DEFINE_SPINLOCK(timer_data_lock);
static struct clk *periph_clk;
static struct timer_data {
void (*cb)(void *);
void *data;
} timer_data[BCM63XX_TIMER_COUNT];
static irqreturn_t timer_interrupt(int irq, void *dev_id)
{
u32 stat;
int i;
spin_lock(&timer_reg_lock);
stat = bcm_timer_readl(TIMER_IRQSTAT_REG);
bcm_timer_writel(stat, TIMER_IRQSTAT_REG);
spin_unlock(&timer_reg_lock);
for (i = 0; i < BCM63XX_TIMER_COUNT; i++) {
if (!(stat & TIMER_IRQSTAT_TIMER_CAUSE(i)))
continue;
spin_lock(&timer_data_lock);
if (!timer_data[i].cb) {
spin_unlock(&timer_data_lock);
continue;
}
timer_data[i].cb(timer_data[i].data);
spin_unlock(&timer_data_lock);
}
return IRQ_HANDLED;
}
int bcm63xx_timer_enable(int id)
{
u32 reg;
unsigned long flags;
if (id >= BCM63XX_TIMER_COUNT)
return -EINVAL;
spin_lock_irqsave(&timer_reg_lock, flags);
reg = bcm_timer_readl(TIMER_CTLx_REG(id));
reg |= TIMER_CTL_ENABLE_MASK;
bcm_timer_writel(reg, TIMER_CTLx_REG(id));
reg = bcm_timer_readl(TIMER_IRQSTAT_REG);
reg |= TIMER_IRQSTAT_TIMER_IR_EN(id);
bcm_timer_writel(reg, TIMER_IRQSTAT_REG);
spin_unlock_irqrestore(&timer_reg_lock, flags);
return 0;
}
EXPORT_SYMBOL(bcm63xx_timer_enable);
int bcm63xx_timer_disable(int id)
{
u32 reg;
unsigned long flags;
if (id >= BCM63XX_TIMER_COUNT)
return -EINVAL;
spin_lock_irqsave(&timer_reg_lock, flags);
reg = bcm_timer_readl(TIMER_CTLx_REG(id));
reg &= ~TIMER_CTL_ENABLE_MASK;
bcm_timer_writel(reg, TIMER_CTLx_REG(id));
reg = bcm_timer_readl(TIMER_IRQSTAT_REG);
reg &= ~TIMER_IRQSTAT_TIMER_IR_EN(id);
bcm_timer_writel(reg, TIMER_IRQSTAT_REG);
spin_unlock_irqrestore(&timer_reg_lock, flags);
return 0;
}
EXPORT_SYMBOL(bcm63xx_timer_disable);
int bcm63xx_timer_register(int id, void (*callback)(void *data), void *data)
{
unsigned long flags;
int ret;
if (id >= BCM63XX_TIMER_COUNT || !callback)
return -EINVAL;
ret = 0;
spin_lock_irqsave(&timer_data_lock, flags);
if (timer_data[id].cb) {
ret = -EBUSY;
goto out;
}
timer_data[id].cb = callback;
timer_data[id].data = data;
out:
spin_unlock_irqrestore(&timer_data_lock, flags);
return ret;
}
EXPORT_SYMBOL(bcm63xx_timer_register);
void bcm63xx_timer_unregister(int id)
{
unsigned long flags;
if (id >= BCM63XX_TIMER_COUNT)
return;
spin_lock_irqsave(&timer_data_lock, flags);
timer_data[id].cb = NULL;
spin_unlock_irqrestore(&timer_data_lock, flags);
}
EXPORT_SYMBOL(bcm63xx_timer_unregister);
unsigned int bcm63xx_timer_countdown(unsigned int countdown_us)
{
return (clk_get_rate(periph_clk) / (1000 * 1000)) * countdown_us;
}
EXPORT_SYMBOL(bcm63xx_timer_countdown);
int bcm63xx_timer_set(int id, int monotonic, unsigned int countdown_us)
{
u32 reg, countdown;
unsigned long flags;
if (id >= BCM63XX_TIMER_COUNT)
return -EINVAL;
countdown = bcm63xx_timer_countdown(countdown_us);
if (countdown & ~TIMER_CTL_COUNTDOWN_MASK)
return -EINVAL;
spin_lock_irqsave(&timer_reg_lock, flags);
reg = bcm_timer_readl(TIMER_CTLx_REG(id));
if (monotonic)
reg &= ~TIMER_CTL_MONOTONIC_MASK;
else
reg |= TIMER_CTL_MONOTONIC_MASK;
reg &= ~TIMER_CTL_COUNTDOWN_MASK;
reg |= countdown;
bcm_timer_writel(reg, TIMER_CTLx_REG(id));
spin_unlock_irqrestore(&timer_reg_lock, flags);
return 0;
}
EXPORT_SYMBOL(bcm63xx_timer_set);
int bcm63xx_timer_init(void)
{
int ret, irq;
u32 reg;
reg = bcm_timer_readl(TIMER_IRQSTAT_REG);
reg &= ~TIMER_IRQSTAT_TIMER0_IR_EN;
reg &= ~TIMER_IRQSTAT_TIMER1_IR_EN;
reg &= ~TIMER_IRQSTAT_TIMER2_IR_EN;
bcm_timer_writel(reg, TIMER_IRQSTAT_REG);
periph_clk = clk_get(NULL, "periph");
if (IS_ERR(periph_clk))
return -ENODEV;
irq = bcm63xx_get_irq_number(IRQ_TIMER);
ret = request_irq(irq, timer_interrupt, 0, "bcm63xx_timer", NULL);
if (ret) {
printk(KERN_ERR "bcm63xx_timer: failed to register irq\n");
return ret;
}
return 0;
}
arch_initcall(bcm63xx_timer_init);

972
arch/mips/configs/bcm63xx_defconfig Normal file
View File

@ -0,0 +1,972 @@
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.30-rc6
# Sun May 31 20:17:18 2009
#
CONFIG_MIPS=y
#
# Machine selection
#
# CONFIG_MACH_ALCHEMY is not set
# CONFIG_BASLER_EXCITE is not set
# CONFIG_BCM47XX is not set
CONFIG_BCM63XX=y
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MACH_JAZZ is not set
# CONFIG_LASAT is not set
# CONFIG_LEMOTE_FULONG is not set
# CONFIG_MIPS_MALTA is not set
# CONFIG_MIPS_SIM is not set
# CONFIG_NEC_MARKEINS is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_NXP_STB220 is not set
# CONFIG_NXP_STB225 is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_PNX8550_STB810 is not set
# CONFIG_PMC_MSP is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_SGI_IP22 is not set
# CONFIG_SGI_IP27 is not set
# CONFIG_SGI_IP28 is not set
# CONFIG_SGI_IP32 is not set
# CONFIG_SIBYTE_CRHINE is not set
# CONFIG_SIBYTE_CARMEL is not set
# CONFIG_SIBYTE_CRHONE is not set
# CONFIG_SIBYTE_RHONE is not set
# CONFIG_SIBYTE_SWARM is not set
# CONFIG_SIBYTE_LITTLESUR is not set
# CONFIG_SIBYTE_SENTOSA is not set
# CONFIG_SIBYTE_BIGSUR is not set
# CONFIG_SNI_RM is not set
# CONFIG_MACH_TX39XX is not set
# CONFIG_MACH_TX49XX is not set
# CONFIG_MIKROTIK_RB532 is not set
# CONFIG_WR_PPMC is not set
# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set
# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set
#
# CPU support
#
CONFIG_BCM63XX_CPU_6348=y
CONFIG_BCM63XX_CPU_6358=y
CONFIG_BOARD_BCM963XX=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
# CONFIG_ARCH_HAS_ILOG2_U32 is not set
# CONFIG_ARCH_HAS_ILOG2_U64 is not set
CONFIG_ARCH_SUPPORTS_OPROFILE=y
CONFIG_GENERIC_FIND_NEXT_BIT=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_TIME=y
CONFIG_GENERIC_CMOS_UPDATE=y
CONFIG_SCHED_OMIT_FRAME_POINTER=y
CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
CONFIG_CEVT_R4K_LIB=y
CONFIG_CEVT_R4K=y
CONFIG_CSRC_R4K_LIB=y
CONFIG_CSRC_R4K=y
CONFIG_DMA_NONCOHERENT=y
CONFIG_DMA_NEED_PCI_MAP_STATE=y
CONFIG_EARLY_PRINTK=y
CONFIG_SYS_HAS_EARLY_PRINTK=y
# CONFIG_HOTPLUG_CPU is not set
# CONFIG_NO_IOPORT is not set
CONFIG_GENERIC_GPIO=y
CONFIG_CPU_BIG_ENDIAN=y
# CONFIG_CPU_LITTLE_ENDIAN is not set
CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
CONFIG_IRQ_CPU=y
CONFIG_SWAP_IO_SPACE=y
CONFIG_MIPS_L1_CACHE_SHIFT=5
#
# CPU selection
#
# CONFIG_CPU_LOONGSON2 is not set
CONFIG_CPU_MIPS32_R1=y
# CONFIG_CPU_MIPS32_R2 is not set
# CONFIG_CPU_MIPS64_R1 is not set
# CONFIG_CPU_MIPS64_R2 is not set
# CONFIG_CPU_R3000 is not set
# CONFIG_CPU_TX39XX is not set
# CONFIG_CPU_VR41XX is not set
# CONFIG_CPU_R4300 is not set
# CONFIG_CPU_R4X00 is not set
# CONFIG_CPU_TX49XX is not set
# CONFIG_CPU_R5000 is not set
# CONFIG_CPU_R5432 is not set
# CONFIG_CPU_R5500 is not set
# CONFIG_CPU_R6000 is not set
# CONFIG_CPU_NEVADA is not set
# CONFIG_CPU_R8000 is not set
# CONFIG_CPU_R10000 is not set
# CONFIG_CPU_RM7000 is not set
# CONFIG_CPU_RM9000 is not set
# CONFIG_CPU_SB1 is not set
# CONFIG_CPU_CAVIUM_OCTEON is not set
CONFIG_SYS_HAS_CPU_MIPS32_R1=y
CONFIG_CPU_MIPS32=y
CONFIG_CPU_MIPSR1=y
CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
CONFIG_HARDWARE_WATCHPOINTS=y
#
# Kernel type
#
CONFIG_32BIT=y
# CONFIG_64BIT is not set
CONFIG_PAGE_SIZE_4KB=y
# CONFIG_PAGE_SIZE_8KB is not set
# CONFIG_PAGE_SIZE_16KB is not set
# CONFIG_PAGE_SIZE_32KB is not set
# CONFIG_PAGE_SIZE_64KB is not set
CONFIG_CPU_HAS_PREFETCH=y
CONFIG_MIPS_MT_DISABLED=y
# CONFIG_MIPS_MT_SMP is not set
# CONFIG_MIPS_MT_SMTC is not set
CONFIG_CPU_HAS_LLSC=y
CONFIG_CPU_HAS_SYNC=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_CPU_SUPPORTS_HIGHMEM=y
CONFIG_ARCH_FLATMEM_ENABLE=y
CONFIG_ARCH_POPULATES_NODE_MAP=y
CONFIG_SELECT_MEMORY_MODEL=y
CONFIG_FLATMEM_MANUAL=y
# CONFIG_DISCONTIGMEM_MANUAL is not set
# CONFIG_SPARSEMEM_MANUAL is not set
CONFIG_FLATMEM=y
CONFIG_FLAT_NODE_MEM_MAP=y
CONFIG_PAGEFLAGS_EXTENDED=y
CONFIG_SPLIT_PTLOCK_CPUS=4
# CONFIG_PHYS_ADDR_T_64BIT is not set
CONFIG_ZONE_DMA_FLAG=0
CONFIG_VIRT_TO_BUS=y
CONFIG_UNEVICTABLE_LRU=y
CONFIG_HAVE_MLOCK=y
CONFIG_HAVE_MLOCKED_PAGE_BIT=y
CONFIG_TICK_ONESHOT=y
CONFIG_NO_HZ=y
# CONFIG_HIGH_RES_TIMERS is not set
CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
# CONFIG_HZ_48 is not set
# CONFIG_HZ_100 is not set
# CONFIG_HZ_128 is not set
CONFIG_HZ_250=y
# CONFIG_HZ_256 is not set
# CONFIG_HZ_1000 is not set
# CONFIG_HZ_1024 is not set
CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
CONFIG_HZ=250
CONFIG_PREEMPT_NONE=y
# CONFIG_PREEMPT_VOLUNTARY is not set
# CONFIG_PREEMPT is not set
# CONFIG_KEXEC is not set
# CONFIG_SECCOMP is not set
CONFIG_LOCKDEP_SUPPORT=y
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
#
# General setup
#
CONFIG_EXPERIMENTAL=y
CONFIG_BROKEN_ON_SMP=y
CONFIG_INIT_ENV_ARG_LIMIT=32
CONFIG_LOCALVERSION=""
# CONFIG_LOCALVERSION_AUTO is not set
# CONFIG_SWAP is not set
# CONFIG_SYSVIPC is not set
# CONFIG_POSIX_MQUEUE is not set
# CONFIG_BSD_PROCESS_ACCT is not set
# CONFIG_TASKSTATS is not set
# CONFIG_AUDIT is not set
#
# RCU Subsystem
#
CONFIG_CLASSIC_RCU=y
# CONFIG_TREE_RCU is not set
# CONFIG_PREEMPT_RCU is not set
# CONFIG_TREE_RCU_TRACE is not set
# CONFIG_PREEMPT_RCU_TRACE is not set
# CONFIG_IKCONFIG is not set
CONFIG_LOG_BUF_SHIFT=17
# CONFIG_GROUP_SCHED is not set
# CONFIG_CGROUPS is not set
CONFIG_SYSFS_DEPRECATED=y
CONFIG_SYSFS_DEPRECATED_V2=y
# CONFIG_RELAY is not set
# CONFIG_NAMESPACES is not set
# CONFIG_BLK_DEV_INITRD is not set
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_SYSCTL=y
CONFIG_EMBEDDED=y
CONFIG_SYSCTL_SYSCALL=y
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_EXTRA_PASS is not set
# CONFIG_STRIP_ASM_SYMS is not set
CONFIG_HOTPLUG=y
CONFIG_PRINTK=y
CONFIG_BUG=y
CONFIG_ELF_CORE=y
# CONFIG_PCSPKR_PLATFORM is not set
CONFIG_BASE_FULL=y
# CONFIG_FUTEX is not set
# CONFIG_EPOLL is not set
# CONFIG_SIGNALFD is not set
# CONFIG_TIMERFD is not set
# CONFIG_EVENTFD is not set
# CONFIG_SHMEM is not set
# CONFIG_AIO is not set
# CONFIG_VM_EVENT_COUNTERS is not set
CONFIG_PCI_QUIRKS=y
# CONFIG_SLUB_DEBUG is not set
CONFIG_COMPAT_BRK=y
# CONFIG_SLAB is not set
CONFIG_SLUB=y
# CONFIG_SLOB is not set
# CONFIG_PROFILING is not set
# CONFIG_MARKERS is not set
CONFIG_HAVE_OPROFILE=y
# CONFIG_SLOW_WORK is not set
# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
CONFIG_BASE_SMALL=0
# CONFIG_MODULES is not set
CONFIG_BLOCK=y
# CONFIG_LBD is not set
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_BLK_DEV_INTEGRITY is not set
#
# IO Schedulers
#
CONFIG_IOSCHED_NOOP=y
# CONFIG_IOSCHED_AS is not set
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
# CONFIG_DEFAULT_AS is not set
# CONFIG_DEFAULT_DEADLINE is not set
# CONFIG_DEFAULT_CFQ is not set
CONFIG_DEFAULT_NOOP=y
CONFIG_DEFAULT_IOSCHED="noop"
# CONFIG_FREEZER is not set
#
# Bus options (PCI, PCMCIA, EISA, ISA, TC)
#
CONFIG_HW_HAS_PCI=y
CONFIG_PCI=y
CONFIG_PCI_DOMAINS=y
# CONFIG_ARCH_SUPPORTS_MSI is not set
# CONFIG_PCI_LEGACY is not set
# CONFIG_PCI_STUB is not set
# CONFIG_PCI_IOV is not set
CONFIG_MMU=y
CONFIG_PCCARD=y
# CONFIG_PCMCIA_DEBUG is not set
CONFIG_PCMCIA=y
CONFIG_PCMCIA_LOAD_CIS=y
CONFIG_PCMCIA_IOCTL=y
CONFIG_CARDBUS=y
#
# PC-card bridges
#
# CONFIG_YENTA is not set
# CONFIG_PD6729 is not set
# CONFIG_I82092 is not set
CONFIG_PCMCIA_BCM63XX=y
# CONFIG_HOTPLUG_PCI is not set
#
# Executable file formats
#
CONFIG_BINFMT_ELF=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
# CONFIG_HAVE_AOUT is not set
# CONFIG_BINFMT_MISC is not set
CONFIG_TRAD_SIGNALS=y
#
# Power management options
#
CONFIG_ARCH_SUSPEND_POSSIBLE=y
# CONFIG_PM is not set
CONFIG_NET=y
#
# Networking options
#
# CONFIG_PACKET is not set
CONFIG_UNIX=y
# CONFIG_NET_KEY is not set
CONFIG_INET=y
# CONFIG_IP_MULTICAST is not set
# CONFIG_IP_ADVANCED_ROUTER is not set
CONFIG_IP_FIB_HASH=y
# CONFIG_IP_PNP is not set
# CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE is not set
# CONFIG_ARPD is not set
# CONFIG_SYN_COOKIES is not set
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
# CONFIG_INET_XFRM_TUNNEL is not set
# CONFIG_INET_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_LRO is not set
# CONFIG_INET_DIAG is not set
# CONFIG_TCP_CONG_ADVANCED is not set
CONFIG_TCP_CONG_CUBIC=y
CONFIG_DEFAULT_TCP_CONG="cubic"
# CONFIG_TCP_MD5SIG is not set
# CONFIG_IPV6 is not set
# CONFIG_NETWORK_SECMARK is not set
# CONFIG_NETFILTER is not set
# CONFIG_IP_DCCP is not set
# CONFIG_IP_SCTP is not set
# CONFIG_TIPC is not set
# CONFIG_ATM is not set
# CONFIG_BRIDGE is not set
# CONFIG_NET_DSA is not set
# CONFIG_VLAN_8021Q is not set
# CONFIG_DECNET is not set
# CONFIG_LLC2 is not set
# CONFIG_IPX is not set
# CONFIG_ATALK is not set
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_ECONET is not set
# CONFIG_WAN_ROUTER is not set
# CONFIG_PHONET is not set
# CONFIG_NET_SCHED is not set
# CONFIG_DCB is not set
#
# Network testing
#
# CONFIG_NET_PKTGEN is not set
# CONFIG_HAMRADIO is not set
# CONFIG_CAN is not set
# CONFIG_IRDA is not set
# CONFIG_BT is not set
# CONFIG_AF_RXRPC is not set
# CONFIG_WIRELESS is not set
# CONFIG_WIMAX is not set
# CONFIG_RFKILL is not set
# CONFIG_NET_9P is not set
#
# Device Drivers
#
#
# Generic Driver Options
#
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
# CONFIG_STANDALONE is not set
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
CONFIG_FW_LOADER=y
CONFIG_FIRMWARE_IN_KERNEL=y
CONFIG_EXTRA_FIRMWARE=""
# CONFIG_SYS_HYPERVISOR is not set
# CONFIG_CONNECTOR is not set
CONFIG_MTD=y
# CONFIG_MTD_DEBUG is not set
# CONFIG_MTD_CONCAT is not set
CONFIG_MTD_PARTITIONS=y
# CONFIG_MTD_REDBOOT_PARTS is not set
# CONFIG_MTD_CMDLINE_PARTS is not set
# CONFIG_MTD_AR7_PARTS is not set
#
# User Modules And Translation Layers
#
# CONFIG_MTD_CHAR is not set
# CONFIG_MTD_BLKDEVS is not set
# CONFIG_MTD_BLOCK is not set
# CONFIG_MTD_BLOCK_RO is not set
# CONFIG_FTL is not set
# CONFIG_NFTL is not set
# CONFIG_INFTL is not set
# CONFIG_RFD_FTL is not set
# CONFIG_SSFDC is not set
# CONFIG_MTD_OOPS is not set
#
# RAM/ROM/Flash chip drivers
#
CONFIG_MTD_CFI=y
# CONFIG_MTD_JEDECPROBE is not set
CONFIG_MTD_GEN_PROBE=y
# CONFIG_MTD_CFI_ADV_OPTIONS is not set
CONFIG_MTD_MAP_BANK_WIDTH_1=y
CONFIG_MTD_MAP_BANK_WIDTH_2=y
CONFIG_MTD_MAP_BANK_WIDTH_4=y
# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
CONFIG_MTD_CFI_I1=y
CONFIG_MTD_CFI_I2=y
# CONFIG_MTD_CFI_I4 is not set
# CONFIG_MTD_CFI_I8 is not set
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_CFI_AMDSTD=y
# CONFIG_MTD_CFI_STAA is not set
CONFIG_MTD_CFI_UTIL=y
# CONFIG_MTD_RAM is not set
# CONFIG_MTD_ROM is not set
# CONFIG_MTD_ABSENT is not set
#
# Mapping drivers for chip access
#
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
CONFIG_MTD_PHYSMAP=y
# CONFIG_MTD_PHYSMAP_COMPAT is not set
# CONFIG_MTD_INTEL_VR_NOR is not set
# CONFIG_MTD_PLATRAM is not set
#
# Self-contained MTD device drivers
#
# CONFIG_MTD_PMC551 is not set
# CONFIG_MTD_SLRAM is not set
# CONFIG_MTD_PHRAM is not set
# CONFIG_MTD_MTDRAM is not set
# CONFIG_MTD_BLOCK2MTD is not set
#
# Disk-On-Chip Device Drivers
#
# CONFIG_MTD_DOC2000 is not set
# CONFIG_MTD_DOC2001 is not set
# CONFIG_MTD_DOC2001PLUS is not set
# CONFIG_MTD_NAND is not set
# CONFIG_MTD_ONENAND is not set
#
# LPDDR flash memory drivers
#
# CONFIG_MTD_LPDDR is not set
#
# UBI - Unsorted block images
#
# CONFIG_MTD_UBI is not set
# CONFIG_PARPORT is not set
# CONFIG_BLK_DEV is not set
# CONFIG_MISC_DEVICES is not set
CONFIG_HAVE_IDE=y
# CONFIG_IDE is not set
#
# SCSI device support
#
# CONFIG_RAID_ATTRS is not set
# CONFIG_SCSI is not set
# CONFIG_SCSI_DMA is not set
# CONFIG_SCSI_NETLINK is not set
# CONFIG_ATA is not set
# CONFIG_MD is not set
# CONFIG_FUSION is not set
#
# IEEE 1394 (FireWire) support
#
#
# Enable only one of the two stacks, unless you know what you are doing
#
# CONFIG_FIREWIRE is not set
# CONFIG_IEEE1394 is not set
# CONFIG_I2O is not set
CONFIG_NETDEVICES=y
CONFIG_COMPAT_NET_DEV_OPS=y
# CONFIG_DUMMY is not set
# CONFIG_BONDING is not set
# CONFIG_MACVLAN is not set
# CONFIG_EQUALIZER is not set
# CONFIG_TUN is not set
# CONFIG_VETH is not set
# CONFIG_ARCNET is not set
CONFIG_PHYLIB=y
#
# MII PHY device drivers
#
# CONFIG_MARVELL_PHY is not set
# CONFIG_DAVICOM_PHY is not set
# CONFIG_QSEMI_PHY is not set
# CONFIG_LXT_PHY is not set
# CONFIG_CICADA_PHY is not set
# CONFIG_VITESSE_PHY is not set
# CONFIG_SMSC_PHY is not set
# CONFIG_BROADCOM_PHY is not set
CONFIG_BCM63XX_PHY=y
# CONFIG_ICPLUS_PHY is not set
# CONFIG_REALTEK_PHY is not set
# CONFIG_NATIONAL_PHY is not set
# CONFIG_STE10XP is not set
# CONFIG_LSI_ET1011C_PHY is not set
# CONFIG_FIXED_PHY is not set
# CONFIG_MDIO_BITBANG is not set
CONFIG_NET_ETHERNET=y
CONFIG_MII=y
# CONFIG_AX88796 is not set
# CONFIG_HAPPYMEAL is not set
# CONFIG_SUNGEM is not set
# CONFIG_CASSINI is not set
# CONFIG_NET_VENDOR_3COM is not set
# CONFIG_SMC91X is not set
# CONFIG_DM9000 is not set
# CONFIG_ETHOC is not set
# CONFIG_DNET is not set
# CONFIG_NET_TULIP is not set
# CONFIG_HP100 is not set
# CONFIG_IBM_NEW_EMAC_ZMII is not set
# CONFIG_IBM_NEW_EMAC_RGMII is not set
# CONFIG_IBM_NEW_EMAC_TAH is not set
# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
# CONFIG_NET_PCI is not set
# CONFIG_B44 is not set
# CONFIG_ATL2 is not set
CONFIG_BCM63XX_ENET=y
# CONFIG_NETDEV_1000 is not set
# CONFIG_NETDEV_10000 is not set
# CONFIG_TR is not set
#
# Wireless LAN
#
# CONFIG_WLAN_PRE80211 is not set
# CONFIG_WLAN_80211 is not set
#
# Enable WiMAX (Networking options) to see the WiMAX drivers
#
#
# USB Network Adapters
#
# CONFIG_USB_CATC is not set
# CONFIG_USB_KAWETH is not set
# CONFIG_USB_PEGASUS is not set
# CONFIG_USB_RTL8150 is not set
# CONFIG_USB_USBNET is not set
# CONFIG_NET_PCMCIA is not set
# CONFIG_WAN is not set
# CONFIG_FDDI is not set
# CONFIG_HIPPI is not set
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
# CONFIG_NETCONSOLE is not set
# CONFIG_NETPOLL is not set
# CONFIG_NET_POLL_CONTROLLER is not set
# CONFIG_ISDN is not set
# CONFIG_PHONE is not set
#
# Input device support
#
# CONFIG_INPUT is not set
#
# Hardware I/O ports
#
# CONFIG_SERIO is not set
# CONFIG_GAMEPORT is not set
#
# Character devices
#
# CONFIG_VT is not set
# CONFIG_DEVKMEM is not set
# CONFIG_SERIAL_NONSTANDARD is not set
# CONFIG_NOZOMI is not set
#
# Serial drivers
#
# CONFIG_SERIAL_8250 is not set
#
# Non-8250 serial port support
#
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
# CONFIG_SERIAL_JSM is not set
CONFIG_SERIAL_BCM63XX=y
CONFIG_SERIAL_BCM63XX_CONSOLE=y
# CONFIG_UNIX98_PTYS is not set
CONFIG_LEGACY_PTYS=y
CONFIG_LEGACY_PTY_COUNT=256
# CONFIG_IPMI_HANDLER is not set
# CONFIG_HW_RANDOM is not set
# CONFIG_R3964 is not set
# CONFIG_APPLICOM is not set
#
# PCMCIA character devices
#
# CONFIG_SYNCLINK_CS is not set
# CONFIG_CARDMAN_4000 is not set
# CONFIG_CARDMAN_4040 is not set
# CONFIG_IPWIRELESS is not set
# CONFIG_RAW_DRIVER is not set
# CONFIG_TCG_TPM is not set
CONFIG_DEVPORT=y
# CONFIG_I2C is not set
# CONFIG_SPI is not set
CONFIG_ARCH_REQUIRE_GPIOLIB=y
CONFIG_GPIOLIB=y
# CONFIG_GPIO_SYSFS is not set
#
# Memory mapped GPIO expanders:
#
#
# I2C GPIO expanders:
#
#
# PCI GPIO expanders:
#
# CONFIG_GPIO_BT8XX is not set
#
# SPI GPIO expanders:
#
# CONFIG_W1 is not set
# CONFIG_POWER_SUPPLY is not set
# CONFIG_HWMON is not set
# CONFIG_THERMAL is not set
# CONFIG_THERMAL_HWMON is not set
# CONFIG_WATCHDOG is not set
CONFIG_SSB_POSSIBLE=y
#
# Sonics Silicon Backplane
#
CONFIG_SSB=y
CONFIG_SSB_SPROM=y
CONFIG_SSB_PCIHOST_POSSIBLE=y
CONFIG_SSB_PCIHOST=y
# CONFIG_SSB_B43_PCI_BRIDGE is not set
CONFIG_SSB_PCMCIAHOST_POSSIBLE=y
# CONFIG_SSB_PCMCIAHOST is not set
# CONFIG_SSB_SILENT is not set
# CONFIG_SSB_DEBUG is not set
CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y
# CONFIG_SSB_DRIVER_PCICORE is not set
# CONFIG_SSB_DRIVER_MIPS is not set
#
# Multifunction device drivers
#
# CONFIG_MFD_CORE is not set
# CONFIG_MFD_SM501 is not set
# CONFIG_HTC_PASIC3 is not set
# CONFIG_MFD_TMIO is not set
# CONFIG_REGULATOR is not set
#
# Multimedia devices
#
#
# Multimedia core support
#
# CONFIG_VIDEO_DEV is not set
# CONFIG_DVB_CORE is not set
# CONFIG_VIDEO_MEDIA is not set
#
# Multimedia drivers
#
# CONFIG_DAB is not set
#
# Graphics support
#
# CONFIG_DRM is not set
# CONFIG_VGASTATE is not set
# CONFIG_VIDEO_OUTPUT_CONTROL is not set
# CONFIG_FB is not set
# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
#
# Display device support
#
CONFIG_DISPLAY_SUPPORT=y
#
# Display hardware drivers
#
# CONFIG_SOUND is not set
CONFIG_USB_SUPPORT=y
CONFIG_USB_ARCH_HAS_HCD=y
CONFIG_USB_ARCH_HAS_OHCI=y
CONFIG_USB_ARCH_HAS_EHCI=y
CONFIG_USB=y
# CONFIG_USB_DEBUG is not set
# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
#
# Miscellaneous USB options
#
# CONFIG_USB_DEVICEFS is not set
# CONFIG_USB_DEVICE_CLASS is not set
# CONFIG_USB_DYNAMIC_MINORS is not set
# CONFIG_USB_OTG is not set
# CONFIG_USB_OTG_WHITELIST is not set
# CONFIG_USB_OTG_BLACKLIST_HUB is not set
# CONFIG_USB_MON is not set
# CONFIG_USB_WUSB is not set
# CONFIG_USB_WUSB_CBAF is not set
#
# USB Host Controller Drivers
#
# CONFIG_USB_C67X00_HCD is not set
CONFIG_USB_EHCI_HCD=y
# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
# CONFIG_USB_EHCI_TT_NEWSCHED is not set
CONFIG_USB_EHCI_BIG_ENDIAN_MMIO=y
# CONFIG_USB_OXU210HP_HCD is not set
# CONFIG_USB_ISP116X_HCD is not set
# CONFIG_USB_ISP1760_HCD is not set
CONFIG_USB_OHCI_HCD=y
# CONFIG_USB_OHCI_HCD_SSB is not set
CONFIG_USB_OHCI_BIG_ENDIAN_DESC=y
CONFIG_USB_OHCI_BIG_ENDIAN_MMIO=y
CONFIG_USB_OHCI_LITTLE_ENDIAN=y
# CONFIG_USB_UHCI_HCD is not set
# CONFIG_USB_SL811_HCD is not set
# CONFIG_USB_R8A66597_HCD is not set
# CONFIG_USB_WHCI_HCD is not set
# CONFIG_USB_HWA_HCD is not set
#
# USB Device Class drivers
#
# CONFIG_USB_ACM is not set
# CONFIG_USB_PRINTER is not set
# CONFIG_USB_WDM is not set
# CONFIG_USB_TMC is not set
#
# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
#
#
# also be needed; see USB_STORAGE Help for more info
#
# CONFIG_USB_LIBUSUAL is not set
#
# USB Imaging devices
#
# CONFIG_USB_MDC800 is not set
#
# USB port drivers
#
# CONFIG_USB_SERIAL is not set
#
# USB Miscellaneous drivers
#
# CONFIG_USB_EMI62 is not set
# CONFIG_USB_EMI26 is not set
# CONFIG_USB_ADUTUX is not set
# CONFIG_USB_SEVSEG is not set
# CONFIG_USB_RIO500 is not set
# CONFIG_USB_LEGOTOWER is not set
# CONFIG_USB_LCD is not set
# CONFIG_USB_BERRY_CHARGE is not set
# CONFIG_USB_LED is not set
# CONFIG_USB_CYPRESS_CY7C63 is not set
# CONFIG_USB_CYTHERM is not set
# CONFIG_USB_IDMOUSE is not set
# CONFIG_USB_FTDI_ELAN is not set
# CONFIG_USB_APPLEDISPLAY is not set
# CONFIG_USB_SISUSBVGA is not set
# CONFIG_USB_LD is not set
# CONFIG_USB_TRANCEVIBRATOR is not set
# CONFIG_USB_IOWARRIOR is not set
# CONFIG_USB_ISIGHTFW is not set
# CONFIG_USB_VST is not set
# CONFIG_USB_GADGET is not set
#
# OTG and related infrastructure
#
# CONFIG_USB_GPIO_VBUS is not set
# CONFIG_NOP_USB_XCEIV is not set
# CONFIG_UWB is not set
# CONFIG_MMC is not set
# CONFIG_MEMSTICK is not set
# CONFIG_NEW_LEDS is not set
# CONFIG_ACCESSIBILITY is not set
# CONFIG_INFINIBAND is not set
CONFIG_RTC_LIB=y
# CONFIG_RTC_CLASS is not set
# CONFIG_DMADEVICES is not set
# CONFIG_AUXDISPLAY is not set
# CONFIG_UIO is not set
# CONFIG_STAGING is not set
#
# File systems
#
# CONFIG_EXT2_FS is not set
# CONFIG_EXT3_FS is not set
# CONFIG_EXT4_FS is not set
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
# CONFIG_FS_POSIX_ACL is not set
# CONFIG_FILE_LOCKING is not set
# CONFIG_XFS_FS is not set
# CONFIG_OCFS2_FS is not set
# CONFIG_BTRFS_FS is not set
# CONFIG_DNOTIFY is not set
# CONFIG_INOTIFY is not set
# CONFIG_QUOTA is not set
# CONFIG_AUTOFS_FS is not set
# CONFIG_AUTOFS4_FS is not set
# CONFIG_FUSE_FS is not set
#
# Caches
#
# CONFIG_FSCACHE is not set
#
# CD-ROM/DVD Filesystems
#
# CONFIG_ISO9660_FS is not set
# CONFIG_UDF_FS is not set
#
# DOS/FAT/NT Filesystems
#
# CONFIG_MSDOS_FS is not set
# CONFIG_VFAT_FS is not set
# CONFIG_NTFS_FS is not set
#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
CONFIG_PROC_KCORE=y
CONFIG_PROC_SYSCTL=y
CONFIG_PROC_PAGE_MONITOR=y
CONFIG_SYSFS=y
CONFIG_TMPFS=y
# CONFIG_TMPFS_POSIX_ACL is not set
# CONFIG_HUGETLB_PAGE is not set
# CONFIG_CONFIGFS_FS is not set
CONFIG_MISC_FILESYSTEMS=y
# CONFIG_ADFS_FS is not set
# CONFIG_AFFS_FS is not set
# CONFIG_HFS_FS is not set
# CONFIG_HFSPLUS_FS is not set
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
# CONFIG_JFFS2_FS is not set
# CONFIG_CRAMFS is not set
# CONFIG_SQUASHFS is not set
# CONFIG_VXFS_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_OMFS_FS is not set
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
# CONFIG_ROMFS_FS is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
# CONFIG_NILFS2_FS is not set
# CONFIG_NETWORK_FILESYSTEMS is not set
#
# Partition Types
#
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_MSDOS_PARTITION=y
# CONFIG_NLS is not set
# CONFIG_DLM is not set
#
# Kernel hacking
#
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
# CONFIG_PRINTK_TIME is not set
CONFIG_ENABLE_WARN_DEPRECATED=y
CONFIG_ENABLE_MUST_CHECK=y
CONFIG_FRAME_WARN=1024
CONFIG_MAGIC_SYSRQ=y
# CONFIG_UNUSED_SYMBOLS is not set
# CONFIG_DEBUG_FS is not set
# CONFIG_HEADERS_CHECK is not set
# CONFIG_DEBUG_KERNEL is not set
# CONFIG_DEBUG_MEMORY_INIT is not set
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
CONFIG_SYSCTL_SYSCALL_CHECK=y
CONFIG_TRACING_SUPPORT=y
#
# Tracers
#
# CONFIG_IRQSOFF_TRACER is not set
# CONFIG_SCHED_TRACER is not set
# CONFIG_CONTEXT_SWITCH_TRACER is not set
# CONFIG_EVENT_TRACER is not set
# CONFIG_BOOT_TRACER is not set
# CONFIG_TRACE_BRANCH_PROFILING is not set
# CONFIG_KMEMTRACE is not set
# CONFIG_WORKQUEUE_TRACER is not set
# CONFIG_BLK_DEV_IO_TRACE is not set
# CONFIG_SAMPLES is not set
CONFIG_HAVE_ARCH_KGDB=y
CONFIG_CMDLINE="console=ttyS0,115200"
#
# Security options
#
# CONFIG_KEYS is not set
# CONFIG_SECURITY is not set
# CONFIG_SECURITYFS is not set
# CONFIG_SECURITY_FILE_CAPABILITIES is not set
# CONFIG_CRYPTO is not set
# CONFIG_BINARY_PRINTF is not set
#
# Library routines
#
CONFIG_BITREVERSE=y
CONFIG_GENERIC_FIND_LAST_BIT=y
# CONFIG_CRC_CCITT is not set
# CONFIG_CRC16 is not set
# CONFIG_CRC_T10DIF is not set
# CONFIG_CRC_ITU_T is not set
CONFIG_CRC32=y
# CONFIG_CRC7 is not set
# CONFIG_LIBCRC32C is not set
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_DMA=y
CONFIG_NLATTR=y

4
arch/mips/include/asm/fixmap.h
View File

@ -67,11 +67,15 @@ enum fixed_addresses {
* the start of the fixmap, and leave one page empty * the start of the fixmap, and leave one page empty
* at the top of mem.. * at the top of mem..
*/ */
#ifdef CONFIG_BCM63XX
#define FIXADDR_TOP ((unsigned long)(long)(int)0xff000000)
#else
#if defined(CONFIG_CPU_TX39XX) || defined(CONFIG_CPU_TX49XX) #if defined(CONFIG_CPU_TX39XX) || defined(CONFIG_CPU_TX49XX)
#define FIXADDR_TOP ((unsigned long)(long)(int)(0xff000000 - 0x20000)) #define FIXADDR_TOP ((unsigned long)(long)(int)(0xff000000 - 0x20000))
#else #else
#define FIXADDR_TOP ((unsigned long)(long)(int)0xfffe0000) #define FIXADDR_TOP ((unsigned long)(long)(int)0xfffe0000)
#endif #endif
#endif
#define FIXADDR_SIZE (__end_of_fixed_addresses << PAGE_SHIFT) #define FIXADDR_SIZE (__end_of_fixed_addresses << PAGE_SHIFT)
#define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE) #define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE)

12
arch/mips/include/asm/mach-bcm63xx/bcm63xx_board.h Normal file
View File

@ -0,0 +1,12 @@
#ifndef BCM63XX_BOARD_H_
#define BCM63XX_BOARD_H_
const char *board_get_name(void);
void board_prom_init(void);
void board_setup(void);
int board_register_devices(void);
#endif /* ! BCM63XX_BOARD_H_ */

11
arch/mips/include/asm/mach-bcm63xx/bcm63xx_clk.h Normal file
View File

@ -0,0 +1,11 @@
#ifndef BCM63XX_CLK_H_
#define BCM63XX_CLK_H_
struct clk {
void (*set)(struct clk *, int);
unsigned int rate;
unsigned int usage;
int id;
};
#endif /* ! BCM63XX_CLK_H_ */

538
arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h Normal file
View File

@ -0,0 +1,538 @@
#ifndef BCM63XX_CPU_H_
#define BCM63XX_CPU_H_
#include <linux/types.h>
#include <linux/init.h>
/*
* Macro to fetch bcm63xx cpu id and revision, should be optimized at
* compile time if only one CPU support is enabled (idea stolen from
* arm mach-types)
*/
#define BCM6338_CPU_ID 0x6338
#define BCM6345_CPU_ID 0x6345
#define BCM6348_CPU_ID 0x6348
#define BCM6358_CPU_ID 0x6358
void __init bcm63xx_cpu_init(void);
u16 __bcm63xx_get_cpu_id(void);
u16 bcm63xx_get_cpu_rev(void);
unsigned int bcm63xx_get_cpu_freq(void);
#ifdef CONFIG_BCM63XX_CPU_6338
# ifdef bcm63xx_get_cpu_id
# undef bcm63xx_get_cpu_id
# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
# define BCMCPU_RUNTIME_DETECT
# else
# define bcm63xx_get_cpu_id() BCM6338_CPU_ID
# endif
# define BCMCPU_IS_6338() (bcm63xx_get_cpu_id() == BCM6338_CPU_ID)
#else
# define BCMCPU_IS_6338() (0)
#endif
#ifdef CONFIG_BCM63XX_CPU_6345
# ifdef bcm63xx_get_cpu_id
# undef bcm63xx_get_cpu_id
# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
# define BCMCPU_RUNTIME_DETECT
# else
# define bcm63xx_get_cpu_id() BCM6345_CPU_ID
# endif
# define BCMCPU_IS_6345() (bcm63xx_get_cpu_id() == BCM6345_CPU_ID)
#else
# define BCMCPU_IS_6345() (0)
#endif
#ifdef CONFIG_BCM63XX_CPU_6348
# ifdef bcm63xx_get_cpu_id
# undef bcm63xx_get_cpu_id
# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
# define BCMCPU_RUNTIME_DETECT
# else
# define bcm63xx_get_cpu_id() BCM6348_CPU_ID
# endif
# define BCMCPU_IS_6348() (bcm63xx_get_cpu_id() == BCM6348_CPU_ID)
#else
# define BCMCPU_IS_6348() (0)
#endif
#ifdef CONFIG_BCM63XX_CPU_6358
# ifdef bcm63xx_get_cpu_id
# undef bcm63xx_get_cpu_id
# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
# define BCMCPU_RUNTIME_DETECT
# else
# define bcm63xx_get_cpu_id() BCM6358_CPU_ID
# endif
# define BCMCPU_IS_6358() (bcm63xx_get_cpu_id() == BCM6358_CPU_ID)
#else
# define BCMCPU_IS_6358() (0)
#endif
#ifndef bcm63xx_get_cpu_id
#error "No CPU support configured"
#endif
/*
* While registers sets are (mostly) the same across 63xx CPU, base
* address of these sets do change.
*/
enum bcm63xx_regs_set {
RSET_DSL_LMEM = 0,
RSET_PERF,
RSET_TIMER,
RSET_WDT,
RSET_UART0,
RSET_GPIO,
RSET_SPI,
RSET_UDC0,
RSET_OHCI0,
RSET_OHCI_PRIV,
RSET_USBH_PRIV,
RSET_MPI,
RSET_PCMCIA,
RSET_DSL,
RSET_ENET0,
RSET_ENET1,
RSET_ENETDMA,
RSET_EHCI0,
RSET_SDRAM,
RSET_MEMC,
RSET_DDR,
};
#define RSET_DSL_LMEM_SIZE (64 * 1024 * 4)
#define RSET_DSL_SIZE 4096
#define RSET_WDT_SIZE 12
#define RSET_ENET_SIZE 2048
#define RSET_ENETDMA_SIZE 2048
#define RSET_UART_SIZE 24
#define RSET_UDC_SIZE 256
#define RSET_OHCI_SIZE 256
#define RSET_EHCI_SIZE 256
#define RSET_PCMCIA_SIZE 12
/*
* 6338 register sets base address
*/
#define BCM_6338_DSL_LMEM_BASE (0xfff00000)
#define BCM_6338_PERF_BASE (0xfffe0000)
#define BCM_6338_BB_BASE (0xfffe0100)
#define BCM_6338_TIMER_BASE (0xfffe0200)
#define BCM_6338_WDT_BASE (0xfffe021c)
#define BCM_6338_UART0_BASE (0xfffe0300)
#define BCM_6338_GPIO_BASE (0xfffe0400)
#define BCM_6338_SPI_BASE (0xfffe0c00)
#define BCM_6338_UDC0_BASE (0xdeadbeef)
#define BCM_6338_USBDMA_BASE (0xfffe2400)
#define BCM_6338_OHCI0_BASE (0xdeadbeef)
#define BCM_6338_OHCI_PRIV_BASE (0xfffe3000)
#define BCM_6338_USBH_PRIV_BASE (0xdeadbeef)
#define BCM_6338_MPI_BASE (0xfffe3160)
#define BCM_6338_PCMCIA_BASE (0xdeadbeef)
#define BCM_6338_SDRAM_REGS_BASE (0xfffe3100)
#define BCM_6338_DSL_BASE (0xfffe1000)
#define BCM_6338_SAR_BASE (0xfffe2000)
#define BCM_6338_UBUS_BASE (0xdeadbeef)
#define BCM_6338_ENET0_BASE (0xfffe2800)
#define BCM_6338_ENET1_BASE (0xdeadbeef)
#define BCM_6338_ENETDMA_BASE (0xfffe2400)
#define BCM_6338_EHCI0_BASE (0xdeadbeef)
#define BCM_6338_SDRAM_BASE (0xfffe3100)
#define BCM_6338_MEMC_BASE (0xdeadbeef)
#define BCM_6338_DDR_BASE (0xdeadbeef)
/*
* 6345 register sets base address
*/
#define BCM_6345_DSL_LMEM_BASE (0xfff00000)
#define BCM_6345_PERF_BASE (0xfffe0000)
#define BCM_6345_BB_BASE (0xfffe0100)
#define BCM_6345_TIMER_BASE (0xfffe0200)
#define BCM_6345_WDT_BASE (0xfffe021c)
#define BCM_6345_UART0_BASE (0xfffe0300)
#define BCM_6345_GPIO_BASE (0xfffe0400)
#define BCM_6345_SPI_BASE (0xdeadbeef)
#define BCM_6345_UDC0_BASE (0xdeadbeef)
#define BCM_6345_USBDMA_BASE (0xfffe2800)
#define BCM_6345_ENET0_BASE (0xfffe1800)
#define BCM_6345_ENETDMA_BASE (0xfffe2800)
#define BCM_6345_PCMCIA_BASE (0xfffe2028)
#define BCM_6345_MPI_BASE (0xdeadbeef)
#define BCM_6345_OHCI0_BASE (0xfffe2100)
#define BCM_6345_OHCI_PRIV_BASE (0xfffe2200)
#define BCM_6345_USBH_PRIV_BASE (0xdeadbeef)
#define BCM_6345_SDRAM_REGS_BASE (0xfffe2300)
#define BCM_6345_DSL_BASE (0xdeadbeef)
#define BCM_6345_SAR_BASE (0xdeadbeef)
#define BCM_6345_UBUS_BASE (0xdeadbeef)
#define BCM_6345_ENET1_BASE (0xdeadbeef)
#define BCM_6345_EHCI0_BASE (0xdeadbeef)
#define BCM_6345_SDRAM_BASE (0xfffe2300)
#define BCM_6345_MEMC_BASE (0xdeadbeef)
#define BCM_6345_DDR_BASE (0xdeadbeef)
/*
* 6348 register sets base address
*/
#define BCM_6348_DSL_LMEM_BASE (0xfff00000)
#define BCM_6348_PERF_BASE (0xfffe0000)
#define BCM_6348_TIMER_BASE (0xfffe0200)
#define BCM_6348_WDT_BASE (0xfffe021c)
#define BCM_6348_UART0_BASE (0xfffe0300)
#define BCM_6348_GPIO_BASE (0xfffe0400)
#define BCM_6348_SPI_BASE (0xfffe0c00)
#define BCM_6348_UDC0_BASE (0xfffe1000)
#define BCM_6348_OHCI0_BASE (0xfffe1b00)
#define BCM_6348_OHCI_PRIV_BASE (0xfffe1c00)
#define BCM_6348_USBH_PRIV_BASE (0xdeadbeef)
#define BCM_6348_MPI_BASE (0xfffe2000)
#define BCM_6348_PCMCIA_BASE (0xfffe2054)
#define BCM_6348_SDRAM_REGS_BASE (0xfffe2300)
#define BCM_6348_DSL_BASE (0xfffe3000)
#define BCM_6348_ENET0_BASE (0xfffe6000)
#define BCM_6348_ENET1_BASE (0xfffe6800)
#define BCM_6348_ENETDMA_BASE (0xfffe7000)
#define BCM_6348_EHCI0_BASE (0xdeadbeef)
#define BCM_6348_SDRAM_BASE (0xfffe2300)
#define BCM_6348_MEMC_BASE (0xdeadbeef)
#define BCM_6348_DDR_BASE (0xdeadbeef)
/*
* 6358 register sets base address
*/
#define BCM_6358_DSL_LMEM_BASE (0xfff00000)
#define BCM_6358_PERF_BASE (0xfffe0000)
#define BCM_6358_TIMER_BASE (0xfffe0040)
#define BCM_6358_WDT_BASE (0xfffe005c)
#define BCM_6358_UART0_BASE (0xfffe0100)
#define BCM_6358_GPIO_BASE (0xfffe0080)
#define BCM_6358_SPI_BASE (0xdeadbeef)
#define BCM_6358_UDC0_BASE (0xfffe0800)
#define BCM_6358_OHCI0_BASE (0xfffe1400)
#define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef)
#define BCM_6358_USBH_PRIV_BASE (0xfffe1500)
#define BCM_6358_MPI_BASE (0xfffe1000)
#define BCM_6358_PCMCIA_BASE (0xfffe1054)
#define BCM_6358_SDRAM_REGS_BASE (0xfffe2300)
#define BCM_6358_DSL_BASE (0xfffe3000)
#define BCM_6358_ENET0_BASE (0xfffe4000)
#define BCM_6358_ENET1_BASE (0xfffe4800)
#define BCM_6358_ENETDMA_BASE (0xfffe5000)
#define BCM_6358_EHCI0_BASE (0xfffe1300)
#define BCM_6358_SDRAM_BASE (0xdeadbeef)
#define BCM_6358_MEMC_BASE (0xfffe1200)
#define BCM_6358_DDR_BASE (0xfffe12a0)
extern const unsigned long *bcm63xx_regs_base;
static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
{
#ifdef BCMCPU_RUNTIME_DETECT
return bcm63xx_regs_base[set];
#else
#ifdef CONFIG_BCM63XX_CPU_6338
switch (set) {
case RSET_DSL_LMEM:
return BCM_6338_DSL_LMEM_BASE;
case RSET_PERF:
return BCM_6338_PERF_BASE;
case RSET_TIMER:
return BCM_6338_TIMER_BASE;
case RSET_WDT:
return BCM_6338_WDT_BASE;
case RSET_UART0:
return BCM_6338_UART0_BASE;
case RSET_GPIO:
return BCM_6338_GPIO_BASE;
case RSET_SPI:
return BCM_6338_SPI_BASE;
case RSET_UDC0:
return BCM_6338_UDC0_BASE;
case RSET_OHCI0:
return BCM_6338_OHCI0_BASE;
case RSET_OHCI_PRIV:
return BCM_6338_OHCI_PRIV_BASE;
case RSET_USBH_PRIV:
return BCM_6338_USBH_PRIV_BASE;
case RSET_MPI:
return BCM_6338_MPI_BASE;
case RSET_PCMCIA:
return BCM_6338_PCMCIA_BASE;
case RSET_DSL:
return BCM_6338_DSL_BASE;
case RSET_ENET0:
return BCM_6338_ENET0_BASE;
case RSET_ENET1:
return BCM_6338_ENET1_BASE;
case RSET_ENETDMA:
return BCM_6338_ENETDMA_BASE;
case RSET_EHCI0:
return BCM_6338_EHCI0_BASE;
case RSET_SDRAM:
return BCM_6338_SDRAM_BASE;
case RSET_MEMC:
return BCM_6338_MEMC_BASE;
case RSET_DDR:
return BCM_6338_DDR_BASE;
}
#endif
#ifdef CONFIG_BCM63XX_CPU_6345
switch (set) {
case RSET_DSL_LMEM:
return BCM_6345_DSL_LMEM_BASE;
case RSET_PERF:
return BCM_6345_PERF_BASE;
case RSET_TIMER:
return BCM_6345_TIMER_BASE;
case RSET_WDT:
return BCM_6345_WDT_BASE;
case RSET_UART0:
return BCM_6345_UART0_BASE;
case RSET_GPIO:
return BCM_6345_GPIO_BASE;
case RSET_SPI:
return BCM_6345_SPI_BASE;
case RSET_UDC0:
return BCM_6345_UDC0_BASE;
case RSET_OHCI0:
return BCM_6345_OHCI0_BASE;
case RSET_OHCI_PRIV:
return BCM_6345_OHCI_PRIV_BASE;
case RSET_USBH_PRIV:
return BCM_6345_USBH_PRIV_BASE;
case RSET_MPI:
return BCM_6345_MPI_BASE;
case RSET_PCMCIA:
return BCM_6345_PCMCIA_BASE;
case RSET_DSL:
return BCM_6345_DSL_BASE;
case RSET_ENET0:
return BCM_6345_ENET0_BASE;
case RSET_ENET1:
return BCM_6345_ENET1_BASE;
case RSET_ENETDMA:
return BCM_6345_ENETDMA_BASE;
case RSET_EHCI0:
return BCM_6345_EHCI0_BASE;
case RSET_SDRAM:
return BCM_6345_SDRAM_BASE;
case RSET_MEMC:
return BCM_6345_MEMC_BASE;
case RSET_DDR:
return BCM_6345_DDR_BASE;
}
#endif
#ifdef CONFIG_BCM63XX_CPU_6348
switch (set) {
case RSET_DSL_LMEM:
return BCM_6348_DSL_LMEM_BASE;
case RSET_PERF:
return BCM_6348_PERF_BASE;
case RSET_TIMER:
return BCM_6348_TIMER_BASE;
case RSET_WDT:
return BCM_6348_WDT_BASE;
case RSET_UART0:
return BCM_6348_UART0_BASE;
case RSET_GPIO:
return BCM_6348_GPIO_BASE;
case RSET_SPI:
return BCM_6348_SPI_BASE;
case RSET_UDC0:
return BCM_6348_UDC0_BASE;
case RSET_OHCI0:
return BCM_6348_OHCI0_BASE;
case RSET_OHCI_PRIV:
return BCM_6348_OHCI_PRIV_BASE;
case RSET_USBH_PRIV:
return BCM_6348_USBH_PRIV_BASE;
case RSET_MPI:
return BCM_6348_MPI_BASE;
case RSET_PCMCIA:
return BCM_6348_PCMCIA_BASE;
case RSET_DSL:
return BCM_6348_DSL_BASE;
case RSET_ENET0:
return BCM_6348_ENET0_BASE;
case RSET_ENET1:
return BCM_6348_ENET1_BASE;
case RSET_ENETDMA:
return BCM_6348_ENETDMA_BASE;
case RSET_EHCI0:
return BCM_6348_EHCI0_BASE;
case RSET_SDRAM:
return BCM_6348_SDRAM_BASE;
case RSET_MEMC:
return BCM_6348_MEMC_BASE;
case RSET_DDR:
return BCM_6348_DDR_BASE;
}
#endif
#ifdef CONFIG_BCM63XX_CPU_6358
switch (set) {
case RSET_DSL_LMEM:
return BCM_6358_DSL_LMEM_BASE;
case RSET_PERF:
return BCM_6358_PERF_BASE;
case RSET_TIMER:
return BCM_6358_TIMER_BASE;
case RSET_WDT:
return BCM_6358_WDT_BASE;
case RSET_UART0:
return BCM_6358_UART0_BASE;
case RSET_GPIO:
return BCM_6358_GPIO_BASE;
case RSET_SPI:
return BCM_6358_SPI_BASE;
case RSET_UDC0:
return BCM_6358_UDC0_BASE;
case RSET_OHCI0:
return BCM_6358_OHCI0_BASE;
case RSET_OHCI_PRIV:
return BCM_6358_OHCI_PRIV_BASE;
case RSET_USBH_PRIV:
return BCM_6358_USBH_PRIV_BASE;
case RSET_MPI:
return BCM_6358_MPI_BASE;
case RSET_PCMCIA:
return BCM_6358_PCMCIA_BASE;
case RSET_ENET0:
return BCM_6358_ENET0_BASE;
case RSET_ENET1:
return BCM_6358_ENET1_BASE;
case RSET_ENETDMA:
return BCM_6358_ENETDMA_BASE;
case RSET_DSL:
return BCM_6358_DSL_BASE;
case RSET_EHCI0:
return BCM_6358_EHCI0_BASE;
case RSET_SDRAM:
return BCM_6358_SDRAM_BASE;
case RSET_MEMC:
return BCM_6358_MEMC_BASE;
case RSET_DDR:
return BCM_6358_DDR_BASE;
}
#endif
#endif
/* unreached */
return 0;
}
/*
* IRQ number changes across CPU too
*/
enum bcm63xx_irq {
IRQ_TIMER = 0,
IRQ_UART0,
IRQ_DSL,
IRQ_ENET0,
IRQ_ENET1,
IRQ_ENET_PHY,
IRQ_OHCI0,
IRQ_EHCI0,
IRQ_PCMCIA0,
IRQ_ENET0_RXDMA,
IRQ_ENET0_TXDMA,
IRQ_ENET1_RXDMA,
IRQ_ENET1_TXDMA,
IRQ_PCI,
IRQ_PCMCIA,
};
/*
* 6338 irqs
*/
#define BCM_6338_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
#define BCM_6338_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
#define BCM_6338_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
#define BCM_6338_DG_IRQ (IRQ_INTERNAL_BASE + 4)
#define BCM_6338_DSL_IRQ (IRQ_INTERNAL_BASE + 5)
#define BCM_6338_ATM_IRQ (IRQ_INTERNAL_BASE + 6)
#define BCM_6338_UDC0_IRQ (IRQ_INTERNAL_BASE + 7)
#define BCM_6338_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
#define BCM_6338_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
#define BCM_6338_SDRAM_IRQ (IRQ_INTERNAL_BASE + 10)
#define BCM_6338_USB_CNTL_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 11)
#define BCM_6338_USB_CNTL_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 12)
#define BCM_6338_USB_BULK_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13)
#define BCM_6338_USB_BULK_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 14)
#define BCM_6338_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15)
#define BCM_6338_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16)
#define BCM_6338_SDIO_IRQ (IRQ_INTERNAL_BASE + 17)
/*
* 6345 irqs
*/
#define BCM_6345_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
#define BCM_6345_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
#define BCM_6345_DSL_IRQ (IRQ_INTERNAL_BASE + 3)
#define BCM_6345_ATM_IRQ (IRQ_INTERNAL_BASE + 4)
#define BCM_6345_USB_IRQ (IRQ_INTERNAL_BASE + 5)
#define BCM_6345_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
#define BCM_6345_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12)
#define BCM_6345_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 1)
#define BCM_6345_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 2)
#define BCM_6345_EBI_RX_IRQ (IRQ_INTERNAL_BASE + 13 + 5)
#define BCM_6345_EBI_TX_IRQ (IRQ_INTERNAL_BASE + 13 + 6)
#define BCM_6345_RESERVED_RX_IRQ (IRQ_INTERNAL_BASE + 13 + 9)
#define BCM_6345_RESERVED_TX_IRQ (IRQ_INTERNAL_BASE + 13 + 10)
#define BCM_6345_USB_BULK_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 13)
#define BCM_6345_USB_BULK_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 14)
#define BCM_6345_USB_CNTL_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 15)
#define BCM_6345_USB_CNTL_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 16)
#define BCM_6345_USB_ISO_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 17)
#define BCM_6345_USB_ISO_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 18)
/*
* 6348 irqs
*/
#define BCM_6348_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
#define BCM_6348_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
#define BCM_6348_DSL_IRQ (IRQ_INTERNAL_BASE + 4)
#define BCM_6348_ENET1_IRQ (IRQ_INTERNAL_BASE + 7)
#define BCM_6348_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
#define BCM_6348_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
#define BCM_6348_OHCI0_IRQ (IRQ_INTERNAL_BASE + 12)
#define BCM_6348_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 20)
#define BCM_6348_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 21)
#define BCM_6348_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 22)
#define BCM_6348_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 23)
#define BCM_6348_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24)
#define BCM_6348_PCI_IRQ (IRQ_INTERNAL_BASE + 24)
/*
* 6358 irqs
*/
#define BCM_6358_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
#define BCM_6358_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
#define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
#define BCM_6358_ENET1_IRQ (IRQ_INTERNAL_BASE + 6)
#define BCM_6358_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
#define BCM_6358_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
#define BCM_6358_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10)
#define BCM_6358_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15)
#define BCM_6358_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16)
#define BCM_6358_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 17)
#define BCM_6358_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 18)
#define BCM_6358_DSL_IRQ (IRQ_INTERNAL_BASE + 29)
#define BCM_6358_PCI_IRQ (IRQ_INTERNAL_BASE + 31)
#define BCM_6358_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24)
extern const int *bcm63xx_irqs;
static inline int bcm63xx_get_irq_number(enum bcm63xx_irq irq)
{
return bcm63xx_irqs[irq];
}
/*
* return installed memory size
*/
unsigned int bcm63xx_get_memory_size(void);
#endif /* !BCM63XX_CPU_H_ */

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arch/mips/include/asm/mach-bcm63xx/bcm63xx_cs.h Normal file
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#ifndef BCM63XX_CS_H
#define BCM63XX_CS_H
int bcm63xx_set_cs_base(unsigned int cs, u32 base, unsigned int size);
int bcm63xx_set_cs_timing(unsigned int cs, unsigned int wait,
unsigned int setup, unsigned int hold);
int bcm63xx_set_cs_param(unsigned int cs, u32 flags);
int bcm63xx_set_cs_status(unsigned int cs, int enable);
#endif /* !BCM63XX_CS_H */

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arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_dsp.h Normal file
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#ifndef __BCM63XX_DSP_H
#define __BCM63XX_DSP_H
struct bcm63xx_dsp_platform_data {
unsigned gpio_rst;
unsigned gpio_int;
unsigned cs;
unsigned ext_irq;
};
int __init bcm63xx_dsp_register(const struct bcm63xx_dsp_platform_data *pd);
#endif /* __BCM63XX_DSP_H */

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arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h Normal file
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#ifndef BCM63XX_DEV_ENET_H_
#define BCM63XX_DEV_ENET_H_
#include <linux/if_ether.h>
#include <linux/init.h>
/*
* on board ethernet platform data
*/
struct bcm63xx_enet_platform_data {
char mac_addr[ETH_ALEN];
int has_phy;
/* if has_phy, then set use_internal_phy */
int use_internal_phy;
/* or fill phy info to use an external one */
int phy_id;
int has_phy_interrupt;
int phy_interrupt;
/* if has_phy, use autonegociated pause parameters or force
* them */
int pause_auto;
int pause_rx;
int pause_tx;
/* if !has_phy, set desired forced speed/duplex */
int force_speed_100;
int force_duplex_full;
/* if !has_phy, set callback to perform mii device
* init/remove */
int (*mii_config)(struct net_device *dev, int probe,
int (*mii_read)(struct net_device *dev,
int phy_id, int reg),
void (*mii_write)(struct net_device *dev,
int phy_id, int reg, int val));
};
int __init bcm63xx_enet_register(int unit,
const struct bcm63xx_enet_platform_data *pd);
#endif /* ! BCM63XX_DEV_ENET_H_ */

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arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_pci.h Normal file
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#ifndef BCM63XX_DEV_PCI_H_
#define BCM63XX_DEV_PCI_H_
extern int bcm63xx_pci_enabled;
#endif /* BCM63XX_DEV_PCI_H_ */

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arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h Normal file
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#ifndef BCM63XX_GPIO_H
#define BCM63XX_GPIO_H
#include <linux/init.h>
int __init bcm63xx_gpio_init(void);
static inline unsigned long bcm63xx_gpio_count(void)
{
switch (bcm63xx_get_cpu_id()) {
case BCM6358_CPU_ID:
return 40;
case BCM6348_CPU_ID:
default:
return 37;
}
}
#define GPIO_DIR_OUT 0x0
#define GPIO_DIR_IN 0x1
#endif /* !BCM63XX_GPIO_H */

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arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h Normal file
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#ifndef BCM63XX_IO_H_
#define BCM63XX_IO_H_
#include "bcm63xx_cpu.h"
/*
* Physical memory map, RAM is mapped at 0x0.
*
* Note that size MUST be a power of two.
*/
#define BCM_PCMCIA_COMMON_BASE_PA (0x20000000)
#define BCM_PCMCIA_COMMON_SIZE (16 * 1024 * 1024)
#define BCM_PCMCIA_COMMON_END_PA (BCM_PCMCIA_COMMON_BASE_PA + \
BCM_PCMCIA_COMMON_SIZE - 1)
#define BCM_PCMCIA_ATTR_BASE_PA (0x21000000)
#define BCM_PCMCIA_ATTR_SIZE (16 * 1024 * 1024)
#define BCM_PCMCIA_ATTR_END_PA (BCM_PCMCIA_ATTR_BASE_PA + \
BCM_PCMCIA_ATTR_SIZE - 1)
#define BCM_PCMCIA_IO_BASE_PA (0x22000000)
#define BCM_PCMCIA_IO_SIZE (64 * 1024)
#define BCM_PCMCIA_IO_END_PA (BCM_PCMCIA_IO_BASE_PA + \
BCM_PCMCIA_IO_SIZE - 1)
#define BCM_PCI_MEM_BASE_PA (0x30000000)
#define BCM_PCI_MEM_SIZE (128 * 1024 * 1024)
#define BCM_PCI_MEM_END_PA (BCM_PCI_MEM_BASE_PA + \
BCM_PCI_MEM_SIZE - 1)
#define BCM_PCI_IO_BASE_PA (0x08000000)
#define BCM_PCI_IO_SIZE (64 * 1024)
#define BCM_PCI_IO_END_PA (BCM_PCI_IO_BASE_PA + \
BCM_PCI_IO_SIZE - 1)
#define BCM_PCI_IO_HALF_PA (BCM_PCI_IO_BASE_PA + \
(BCM_PCI_IO_SIZE / 2) - 1)
#define BCM_CB_MEM_BASE_PA (0x38000000)
#define BCM_CB_MEM_SIZE (128 * 1024 * 1024)
#define BCM_CB_MEM_END_PA (BCM_CB_MEM_BASE_PA + \
BCM_CB_MEM_SIZE - 1)
/*
* Internal registers are accessed through KSEG3
*/
#define BCM_REGS_VA(x) ((void __iomem *)(x))
#define bcm_readb(a) (*(volatile unsigned char *) BCM_REGS_VA(a))
#define bcm_readw(a) (*(volatile unsigned short *) BCM_REGS_VA(a))
#define bcm_readl(a) (*(volatile unsigned int *) BCM_REGS_VA(a))
#define bcm_writeb(v, a) (*(volatile unsigned char *) BCM_REGS_VA((a)) = (v))
#define bcm_writew(v, a) (*(volatile unsigned short *) BCM_REGS_VA((a)) = (v))
#define bcm_writel(v, a) (*(volatile unsigned int *) BCM_REGS_VA((a)) = (v))
/*
* IO helpers to access register set for current CPU
*/
#define bcm_rset_readb(s, o) bcm_readb(bcm63xx_regset_address(s) + (o))
#define bcm_rset_readw(s, o) bcm_readw(bcm63xx_regset_address(s) + (o))
#define bcm_rset_readl(s, o) bcm_readl(bcm63xx_regset_address(s) + (o))
#define bcm_rset_writeb(s, v, o) bcm_writeb((v), \
bcm63xx_regset_address(s) + (o))
#define bcm_rset_writew(s, v, o) bcm_writew((v), \
bcm63xx_regset_address(s) + (o))
#define bcm_rset_writel(s, v, o) bcm_writel((v), \
bcm63xx_regset_address(s) + (o))
/*
* helpers for frequently used register sets
*/
#define bcm_perf_readl(o) bcm_rset_readl(RSET_PERF, (o))
#define bcm_perf_writel(v, o) bcm_rset_writel(RSET_PERF, (v), (o))
#define bcm_timer_readl(o) bcm_rset_readl(RSET_TIMER, (o))
#define bcm_timer_writel(v, o) bcm_rset_writel(RSET_TIMER, (v), (o))
#define bcm_wdt_readl(o) bcm_rset_readl(RSET_WDT, (o))
#define bcm_wdt_writel(v, o) bcm_rset_writel(RSET_WDT, (v), (o))
#define bcm_gpio_readl(o) bcm_rset_readl(RSET_GPIO, (o))
#define bcm_gpio_writel(v, o) bcm_rset_writel(RSET_GPIO, (v), (o))
#define bcm_uart0_readl(o) bcm_rset_readl(RSET_UART0, (o))
#define bcm_uart0_writel(v, o) bcm_rset_writel(RSET_UART0, (v), (o))
#define bcm_mpi_readl(o) bcm_rset_readl(RSET_MPI, (o))
#define bcm_mpi_writel(v, o) bcm_rset_writel(RSET_MPI, (v), (o))
#define bcm_pcmcia_readl(o) bcm_rset_readl(RSET_PCMCIA, (o))
#define bcm_pcmcia_writel(v, o) bcm_rset_writel(RSET_PCMCIA, (v), (o))
#define bcm_sdram_readl(o) bcm_rset_readl(RSET_SDRAM, (o))
#define bcm_sdram_writel(v, o) bcm_rset_writel(RSET_SDRAM, (v), (o))
#define bcm_memc_readl(o) bcm_rset_readl(RSET_MEMC, (o))
#define bcm_memc_writel(v, o) bcm_rset_writel(RSET_MEMC, (v), (o))
#define bcm_ddr_readl(o) bcm_rset_readl(RSET_DDR, (o))
#define bcm_ddr_writel(v, o) bcm_rset_writel(RSET_DDR, (v), (o))
#endif /* ! BCM63XX_IO_H_ */

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arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h Normal file
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#ifndef BCM63XX_IRQ_H_
#define BCM63XX_IRQ_H_
#include <bcm63xx_cpu.h>
#define IRQ_MIPS_BASE 0
#define IRQ_INTERNAL_BASE 8
#define IRQ_EXT_BASE (IRQ_MIPS_BASE + 3)
#define IRQ_EXT_0 (IRQ_EXT_BASE + 0)
#define IRQ_EXT_1 (IRQ_EXT_BASE + 1)
#define IRQ_EXT_2 (IRQ_EXT_BASE + 2)
#define IRQ_EXT_3 (IRQ_EXT_BASE + 3)
#endif /* ! BCM63XX_IRQ_H_ */

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arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h Normal file
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#ifndef BCM63XX_REGS_H_
#define BCM63XX_REGS_H_
/*************************************************************************
* _REG relative to RSET_PERF
*************************************************************************/
/* Chip Identifier / Revision register */
#define PERF_REV_REG 0x0
#define REV_CHIPID_SHIFT 16
#define REV_CHIPID_MASK (0xffff << REV_CHIPID_SHIFT)
#define REV_REVID_SHIFT 0
#define REV_REVID_MASK (0xffff << REV_REVID_SHIFT)
/* Clock Control register */
#define PERF_CKCTL_REG 0x4
#define CKCTL_6338_ADSLPHY_EN (1 << 0)
#define CKCTL_6338_MPI_EN (1 << 1)
#define CKCTL_6338_DRAM_EN (1 << 2)
#define CKCTL_6338_ENET_EN (1 << 4)
#define CKCTL_6338_USBS_EN (1 << 4)
#define CKCTL_6338_SAR_EN (1 << 5)
#define CKCTL_6338_SPI_EN (1 << 9)
#define CKCTL_6338_ALL_SAFE_EN (CKCTL_6338_ADSLPHY_EN | \
CKCTL_6338_MPI_EN | \
CKCTL_6338_ENET_EN | \
CKCTL_6338_SAR_EN | \
CKCTL_6338_SPI_EN)
#define CKCTL_6345_CPU_EN (1 << 0)
#define CKCTL_6345_BUS_EN (1 << 1)
#define CKCTL_6345_EBI_EN (1 << 2)
#define CKCTL_6345_UART_EN (1 << 3)
#define CKCTL_6345_ADSLPHY_EN (1 << 4)
#define CKCTL_6345_ENET_EN (1 << 7)
#define CKCTL_6345_USBH_EN (1 << 8)
#define CKCTL_6345_ALL_SAFE_EN (CKCTL_6345_ENET_EN | \
CKCTL_6345_USBH_EN | \
CKCTL_6345_ADSLPHY_EN)
#define CKCTL_6348_ADSLPHY_EN (1 << 0)
#define CKCTL_6348_MPI_EN (1 << 1)
#define CKCTL_6348_SDRAM_EN (1 << 2)
#define CKCTL_6348_M2M_EN (1 << 3)
#define CKCTL_6348_ENET_EN (1 << 4)
#define CKCTL_6348_SAR_EN (1 << 5)
#define CKCTL_6348_USBS_EN (1 << 6)
#define CKCTL_6348_USBH_EN (1 << 8)
#define CKCTL_6348_SPI_EN (1 << 9)
#define CKCTL_6348_ALL_SAFE_EN (CKCTL_6348_ADSLPHY_EN | \
CKCTL_6348_M2M_EN | \
CKCTL_6348_ENET_EN | \
CKCTL_6348_SAR_EN | \
CKCTL_6348_USBS_EN | \
CKCTL_6348_USBH_EN | \
CKCTL_6348_SPI_EN)
#define CKCTL_6358_ENET_EN (1 << 4)
#define CKCTL_6358_ADSLPHY_EN (1 << 5)
#define CKCTL_6358_PCM_EN (1 << 8)
#define CKCTL_6358_SPI_EN (1 << 9)
#define CKCTL_6358_USBS_EN (1 << 10)
#define CKCTL_6358_SAR_EN (1 << 11)
#define CKCTL_6358_EMUSB_EN (1 << 17)
#define CKCTL_6358_ENET0_EN (1 << 18)
#define CKCTL_6358_ENET1_EN (1 << 19)
#define CKCTL_6358_USBSU_EN (1 << 20)
#define CKCTL_6358_EPHY_EN (1 << 21)
#define CKCTL_6358_ALL_SAFE_EN (CKCTL_6358_ENET_EN | \
CKCTL_6358_ADSLPHY_EN | \
CKCTL_6358_PCM_EN | \
CKCTL_6358_SPI_EN | \
CKCTL_6358_USBS_EN | \
CKCTL_6358_SAR_EN | \
CKCTL_6358_EMUSB_EN | \
CKCTL_6358_ENET0_EN | \
CKCTL_6358_ENET1_EN | \
CKCTL_6358_USBSU_EN | \
CKCTL_6358_EPHY_EN)
/* System PLL Control register */
#define PERF_SYS_PLL_CTL_REG 0x8
#define SYS_PLL_SOFT_RESET 0x1
/* Interrupt Mask register */
#define PERF_IRQMASK_REG 0xc
#define PERF_IRQSTAT_REG 0x10
/* Interrupt Status register */
#define PERF_IRQSTAT_REG 0x10
/* External Interrupt Configuration register */
#define PERF_EXTIRQ_CFG_REG 0x14
#define EXTIRQ_CFG_SENSE(x) (1 << (x))
#define EXTIRQ_CFG_STAT(x) (1 << (x + 5))
#define EXTIRQ_CFG_CLEAR(x) (1 << (x + 10))
#define EXTIRQ_CFG_MASK(x) (1 << (x + 15))
#define EXTIRQ_CFG_BOTHEDGE(x) (1 << (x + 20))
#define EXTIRQ_CFG_LEVELSENSE(x) (1 << (x + 25))
#define EXTIRQ_CFG_CLEAR_ALL (0xf << 10)
#define EXTIRQ_CFG_MASK_ALL (0xf << 15)
/* Soft Reset register */
#define PERF_SOFTRESET_REG 0x28
#define SOFTRESET_6338_SPI_MASK (1 << 0)
#define SOFTRESET_6338_ENET_MASK (1 << 2)
#define SOFTRESET_6338_USBH_MASK (1 << 3)
#define SOFTRESET_6338_USBS_MASK (1 << 4)
#define SOFTRESET_6338_ADSL_MASK (1 << 5)
#define SOFTRESET_6338_DMAMEM_MASK (1 << 6)
#define SOFTRESET_6338_SAR_MASK (1 << 7)
#define SOFTRESET_6338_ACLC_MASK (1 << 8)
#define SOFTRESET_6338_ADSLMIPSPLL_MASK (1 << 10)
#define SOFTRESET_6338_ALL (SOFTRESET_6338_SPI_MASK | \
SOFTRESET_6338_ENET_MASK | \
SOFTRESET_6338_USBH_MASK | \
SOFTRESET_6338_USBS_MASK | \
SOFTRESET_6338_ADSL_MASK | \
SOFTRESET_6338_DMAMEM_MASK | \
SOFTRESET_6338_SAR_MASK | \
SOFTRESET_6338_ACLC_MASK | \
SOFTRESET_6338_ADSLMIPSPLL_MASK)
#define SOFTRESET_6348_SPI_MASK (1 << 0)
#define SOFTRESET_6348_ENET_MASK (1 << 2)
#define SOFTRESET_6348_USBH_MASK (1 << 3)
#define SOFTRESET_6348_USBS_MASK (1 << 4)
#define SOFTRESET_6348_ADSL_MASK (1 << 5)
#define SOFTRESET_6348_DMAMEM_MASK (1 << 6)
#define SOFTRESET_6348_SAR_MASK (1 << 7)
#define SOFTRESET_6348_ACLC_MASK (1 << 8)
#define SOFTRESET_6348_ADSLMIPSPLL_MASK (1 << 10)
#define SOFTRESET_6348_ALL (SOFTRESET_6348_SPI_MASK | \
SOFTRESET_6348_ENET_MASK | \
SOFTRESET_6348_USBH_MASK | \
SOFTRESET_6348_USBS_MASK | \
SOFTRESET_6348_ADSL_MASK | \
SOFTRESET_6348_DMAMEM_MASK | \
SOFTRESET_6348_SAR_MASK | \
SOFTRESET_6348_ACLC_MASK | \
SOFTRESET_6348_ADSLMIPSPLL_MASK)
/* MIPS PLL control register */
#define PERF_MIPSPLLCTL_REG 0x34
#define MIPSPLLCTL_N1_SHIFT 20
#define MIPSPLLCTL_N1_MASK (0x7 << MIPSPLLCTL_N1_SHIFT)
#define MIPSPLLCTL_N2_SHIFT 15
#define MIPSPLLCTL_N2_MASK (0x1f << MIPSPLLCTL_N2_SHIFT)
#define MIPSPLLCTL_M1REF_SHIFT 12
#define MIPSPLLCTL_M1REF_MASK (0x7 << MIPSPLLCTL_M1REF_SHIFT)
#define MIPSPLLCTL_M2REF_SHIFT 9
#define MIPSPLLCTL_M2REF_MASK (0x7 << MIPSPLLCTL_M2REF_SHIFT)
#define MIPSPLLCTL_M1CPU_SHIFT 6
#define MIPSPLLCTL_M1CPU_MASK (0x7 << MIPSPLLCTL_M1CPU_SHIFT)
#define MIPSPLLCTL_M1BUS_SHIFT 3
#define MIPSPLLCTL_M1BUS_MASK (0x7 << MIPSPLLCTL_M1BUS_SHIFT)
#define MIPSPLLCTL_M2BUS_SHIFT 0
#define MIPSPLLCTL_M2BUS_MASK (0x7 << MIPSPLLCTL_M2BUS_SHIFT)
/* ADSL PHY PLL Control register */
#define PERF_ADSLPLLCTL_REG 0x38
#define ADSLPLLCTL_N1_SHIFT 20
#define ADSLPLLCTL_N1_MASK (0x7 << ADSLPLLCTL_N1_SHIFT)
#define ADSLPLLCTL_N2_SHIFT 15
#define ADSLPLLCTL_N2_MASK (0x1f << ADSLPLLCTL_N2_SHIFT)
#define ADSLPLLCTL_M1REF_SHIFT 12
#define ADSLPLLCTL_M1REF_MASK (0x7 << ADSLPLLCTL_M1REF_SHIFT)
#define ADSLPLLCTL_M2REF_SHIFT 9
#define ADSLPLLCTL_M2REF_MASK (0x7 << ADSLPLLCTL_M2REF_SHIFT)
#define ADSLPLLCTL_M1CPU_SHIFT 6
#define ADSLPLLCTL_M1CPU_MASK (0x7 << ADSLPLLCTL_M1CPU_SHIFT)
#define ADSLPLLCTL_M1BUS_SHIFT 3
#define ADSLPLLCTL_M1BUS_MASK (0x7 << ADSLPLLCTL_M1BUS_SHIFT)
#define ADSLPLLCTL_M2BUS_SHIFT 0
#define ADSLPLLCTL_M2BUS_MASK (0x7 << ADSLPLLCTL_M2BUS_SHIFT)
#define ADSLPLLCTL_VAL(n1, n2, m1ref, m2ref, m1cpu, m1bus, m2bus) \
(((n1) << ADSLPLLCTL_N1_SHIFT) | \
((n2) << ADSLPLLCTL_N2_SHIFT) | \
((m1ref) << ADSLPLLCTL_M1REF_SHIFT) | \
((m2ref) << ADSLPLLCTL_M2REF_SHIFT) | \
((m1cpu) << ADSLPLLCTL_M1CPU_SHIFT) | \
((m1bus) << ADSLPLLCTL_M1BUS_SHIFT) | \
((m2bus) << ADSLPLLCTL_M2BUS_SHIFT))
/*************************************************************************
* _REG relative to RSET_TIMER
*************************************************************************/
#define BCM63XX_TIMER_COUNT 4
#define TIMER_T0_ID 0
#define TIMER_T1_ID 1
#define TIMER_T2_ID 2
#define TIMER_WDT_ID 3
/* Timer irqstat register */
#define TIMER_IRQSTAT_REG 0
#define TIMER_IRQSTAT_TIMER_CAUSE(x) (1 << (x))
#define TIMER_IRQSTAT_TIMER0_CAUSE (1 << 0)
#define TIMER_IRQSTAT_TIMER1_CAUSE (1 << 1)
#define TIMER_IRQSTAT_TIMER2_CAUSE (1 << 2)
#define TIMER_IRQSTAT_WDT_CAUSE (1 << 3)
#define TIMER_IRQSTAT_TIMER_IR_EN(x) (1 << ((x) + 8))
#define TIMER_IRQSTAT_TIMER0_IR_EN (1 << 8)
#define TIMER_IRQSTAT_TIMER1_IR_EN (1 << 9)
#define TIMER_IRQSTAT_TIMER2_IR_EN (1 << 10)
/* Timer control register */
#define TIMER_CTLx_REG(x) (0x4 + (x * 4))
#define TIMER_CTL0_REG 0x4
#define TIMER_CTL1_REG 0x8
#define TIMER_CTL2_REG 0xC
#define TIMER_CTL_COUNTDOWN_MASK (0x3fffffff)
#define TIMER_CTL_MONOTONIC_MASK (1 << 30)
#define TIMER_CTL_ENABLE_MASK (1 << 31)
/*************************************************************************
* _REG relative to RSET_WDT
*************************************************************************/
/* Watchdog default count register */
#define WDT_DEFVAL_REG 0x0
/* Watchdog control register */
#define WDT_CTL_REG 0x4
/* Watchdog control register constants */
#define WDT_START_1 (0xff00)
#define WDT_START_2 (0x00ff)
#define WDT_STOP_1 (0xee00)
#define WDT_STOP_2 (0x00ee)
/* Watchdog reset length register */
#define WDT_RSTLEN_REG 0x8
/*************************************************************************
* _REG relative to RSET_UARTx
*************************************************************************/
/* UART Control Register */
#define UART_CTL_REG 0x0
#define UART_CTL_RXTMOUTCNT_SHIFT 0
#define UART_CTL_RXTMOUTCNT_MASK (0x1f << UART_CTL_RXTMOUTCNT_SHIFT)
#define UART_CTL_RSTTXDN_SHIFT 5
#define UART_CTL_RSTTXDN_MASK (1 << UART_CTL_RSTTXDN_SHIFT)
#define UART_CTL_RSTRXFIFO_SHIFT 6
#define UART_CTL_RSTRXFIFO_MASK (1 << UART_CTL_RSTRXFIFO_SHIFT)
#define UART_CTL_RSTTXFIFO_SHIFT 7
#define UART_CTL_RSTTXFIFO_MASK (1 << UART_CTL_RSTTXFIFO_SHIFT)
#define UART_CTL_STOPBITS_SHIFT 8
#define UART_CTL_STOPBITS_MASK (0xf << UART_CTL_STOPBITS_SHIFT)
#define UART_CTL_STOPBITS_1 (0x7 << UART_CTL_STOPBITS_SHIFT)
#define UART_CTL_STOPBITS_2 (0xf << UART_CTL_STOPBITS_SHIFT)
#define UART_CTL_BITSPERSYM_SHIFT 12
#define UART_CTL_BITSPERSYM_MASK (0x3 << UART_CTL_BITSPERSYM_SHIFT)
#define UART_CTL_XMITBRK_SHIFT 14
#define UART_CTL_XMITBRK_MASK (1 << UART_CTL_XMITBRK_SHIFT)
#define UART_CTL_RSVD_SHIFT 15
#define UART_CTL_RSVD_MASK (1 << UART_CTL_RSVD_SHIFT)
#define UART_CTL_RXPAREVEN_SHIFT 16
#define UART_CTL_RXPAREVEN_MASK (1 << UART_CTL_RXPAREVEN_SHIFT)
#define UART_CTL_RXPAREN_SHIFT 17
#define UART_CTL_RXPAREN_MASK (1 << UART_CTL_RXPAREN_SHIFT)
#define UART_CTL_TXPAREVEN_SHIFT 18
#define UART_CTL_TXPAREVEN_MASK (1 << UART_CTL_TXPAREVEN_SHIFT)
#define UART_CTL_TXPAREN_SHIFT 18
#define UART_CTL_TXPAREN_MASK (1 << UART_CTL_TXPAREN_SHIFT)
#define UART_CTL_LOOPBACK_SHIFT 20
#define UART_CTL_LOOPBACK_MASK (1 << UART_CTL_LOOPBACK_SHIFT)
#define UART_CTL_RXEN_SHIFT 21
#define UART_CTL_RXEN_MASK (1 << UART_CTL_RXEN_SHIFT)
#define UART_CTL_TXEN_SHIFT 22
#define UART_CTL_TXEN_MASK (1 << UART_CTL_TXEN_SHIFT)
#define UART_CTL_BRGEN_SHIFT 23
#define UART_CTL_BRGEN_MASK (1 << UART_CTL_BRGEN_SHIFT)
/* UART Baudword register */
#define UART_BAUD_REG 0x4
/* UART Misc Control register */
#define UART_MCTL_REG 0x8
#define UART_MCTL_DTR_SHIFT 0
#define UART_MCTL_DTR_MASK (1 << UART_MCTL_DTR_SHIFT)
#define UART_MCTL_RTS_SHIFT 1
#define UART_MCTL_RTS_MASK (1 << UART_MCTL_RTS_SHIFT)
#define UART_MCTL_RXFIFOTHRESH_SHIFT 8
#define UART_MCTL_RXFIFOTHRESH_MASK (0xf << UART_MCTL_RXFIFOTHRESH_SHIFT)
#define UART_MCTL_TXFIFOTHRESH_SHIFT 12
#define UART_MCTL_TXFIFOTHRESH_MASK (0xf << UART_MCTL_TXFIFOTHRESH_SHIFT)
#define UART_MCTL_RXFIFOFILL_SHIFT 16
#define UART_MCTL_RXFIFOFILL_MASK (0x1f << UART_MCTL_RXFIFOFILL_SHIFT)
#define UART_MCTL_TXFIFOFILL_SHIFT 24
#define UART_MCTL_TXFIFOFILL_MASK (0x1f << UART_MCTL_TXFIFOFILL_SHIFT)
/* UART External Input Configuration register */
#define UART_EXTINP_REG 0xc
#define UART_EXTINP_RI_SHIFT 0
#define UART_EXTINP_RI_MASK (1 << UART_EXTINP_RI_SHIFT)
#define UART_EXTINP_CTS_SHIFT 1
#define UART_EXTINP_CTS_MASK (1 << UART_EXTINP_CTS_SHIFT)
#define UART_EXTINP_DCD_SHIFT 2
#define UART_EXTINP_DCD_MASK (1 << UART_EXTINP_DCD_SHIFT)
#define UART_EXTINP_DSR_SHIFT 3
#define UART_EXTINP_DSR_MASK (1 << UART_EXTINP_DSR_SHIFT)
#define UART_EXTINP_IRSTAT(x) (1 << (x + 4))
#define UART_EXTINP_IRMASK(x) (1 << (x + 8))
#define UART_EXTINP_IR_RI 0
#define UART_EXTINP_IR_CTS 1
#define UART_EXTINP_IR_DCD 2
#define UART_EXTINP_IR_DSR 3
#define UART_EXTINP_RI_NOSENSE_SHIFT 16
#define UART_EXTINP_RI_NOSENSE_MASK (1 << UART_EXTINP_RI_NOSENSE_SHIFT)
#define UART_EXTINP_CTS_NOSENSE_SHIFT 17
#define UART_EXTINP_CTS_NOSENSE_MASK (1 << UART_EXTINP_CTS_NOSENSE_SHIFT)
#define UART_EXTINP_DCD_NOSENSE_SHIFT 18
#define UART_EXTINP_DCD_NOSENSE_MASK (1 << UART_EXTINP_DCD_NOSENSE_SHIFT)
#define UART_EXTINP_DSR_NOSENSE_SHIFT 19
#define UART_EXTINP_DSR_NOSENSE_MASK (1 << UART_EXTINP_DSR_NOSENSE_SHIFT)
/* UART Interrupt register */
#define UART_IR_REG 0x10
#define UART_IR_MASK(x) (1 << (x + 16))
#define UART_IR_STAT(x) (1 << (x))
#define UART_IR_EXTIP 0
#define UART_IR_TXUNDER 1
#define UART_IR_TXOVER 2
#define UART_IR_TXTRESH 3
#define UART_IR_TXRDLATCH 4
#define UART_IR_TXEMPTY 5
#define UART_IR_RXUNDER 6
#define UART_IR_RXOVER 7
#define UART_IR_RXTIMEOUT 8
#define UART_IR_RXFULL 9
#define UART_IR_RXTHRESH 10
#define UART_IR_RXNOTEMPTY 11
#define UART_IR_RXFRAMEERR 12
#define UART_IR_RXPARERR 13
#define UART_IR_RXBRK 14
#define UART_IR_TXDONE 15
/* UART Fifo register */
#define UART_FIFO_REG 0x14
#define UART_FIFO_VALID_SHIFT 0
#define UART_FIFO_VALID_MASK 0xff
#define UART_FIFO_FRAMEERR_SHIFT 8
#define UART_FIFO_FRAMEERR_MASK (1 << UART_FIFO_FRAMEERR_SHIFT)
#define UART_FIFO_PARERR_SHIFT 9
#define UART_FIFO_PARERR_MASK (1 << UART_FIFO_PARERR_SHIFT)
#define UART_FIFO_BRKDET_SHIFT 10
#define UART_FIFO_BRKDET_MASK (1 << UART_FIFO_BRKDET_SHIFT)
#define UART_FIFO_ANYERR_MASK (UART_FIFO_FRAMEERR_MASK | \
UART_FIFO_PARERR_MASK | \
UART_FIFO_BRKDET_MASK)
/*************************************************************************
* _REG relative to RSET_GPIO
*************************************************************************/
/* GPIO registers */
#define GPIO_CTL_HI_REG 0x0
#define GPIO_CTL_LO_REG 0x4
#define GPIO_DATA_HI_REG 0x8
#define GPIO_DATA_LO_REG 0xC
/* GPIO mux registers and constants */
#define GPIO_MODE_REG 0x18
#define GPIO_MODE_6348_G4_DIAG 0x00090000
#define GPIO_MODE_6348_G4_UTOPIA 0x00080000
#define GPIO_MODE_6348_G4_LEGACY_LED 0x00030000
#define GPIO_MODE_6348_G4_MII_SNOOP 0x00020000
#define GPIO_MODE_6348_G4_EXT_EPHY 0x00010000
#define GPIO_MODE_6348_G3_DIAG 0x00009000
#define GPIO_MODE_6348_G3_UTOPIA 0x00008000
#define GPIO_MODE_6348_G3_EXT_MII 0x00007000
#define GPIO_MODE_6348_G2_DIAG 0x00000900
#define GPIO_MODE_6348_G2_PCI 0x00000500
#define GPIO_MODE_6348_G1_DIAG 0x00000090
#define GPIO_MODE_6348_G1_UTOPIA 0x00000080
#define GPIO_MODE_6348_G1_SPI_UART 0x00000060
#define GPIO_MODE_6348_G1_SPI_MASTER 0x00000060
#define GPIO_MODE_6348_G1_MII_PCCARD 0x00000040
#define GPIO_MODE_6348_G1_MII_SNOOP 0x00000020
#define GPIO_MODE_6348_G1_EXT_EPHY 0x00000010
#define GPIO_MODE_6348_G0_DIAG 0x00000009
#define GPIO_MODE_6348_G0_EXT_MII 0x00000007
#define GPIO_MODE_6358_EXTRACS (1 << 5)
#define GPIO_MODE_6358_UART1 (1 << 6)
#define GPIO_MODE_6358_EXTRA_SPI_SS (1 << 7)
#define GPIO_MODE_6358_SERIAL_LED (1 << 10)
#define GPIO_MODE_6358_UTOPIA (1 << 12)
/*************************************************************************
* _REG relative to RSET_ENET
*************************************************************************/
/* Receiver Configuration register */
#define ENET_RXCFG_REG 0x0
#define ENET_RXCFG_ALLMCAST_SHIFT 1
#define ENET_RXCFG_ALLMCAST_MASK (1 << ENET_RXCFG_ALLMCAST_SHIFT)
#define ENET_RXCFG_PROMISC_SHIFT 3
#define ENET_RXCFG_PROMISC_MASK (1 << ENET_RXCFG_PROMISC_SHIFT)
#define ENET_RXCFG_LOOPBACK_SHIFT 4
#define ENET_RXCFG_LOOPBACK_MASK (1 << ENET_RXCFG_LOOPBACK_SHIFT)
#define ENET_RXCFG_ENFLOW_SHIFT 5
#define ENET_RXCFG_ENFLOW_MASK (1 << ENET_RXCFG_ENFLOW_SHIFT)
/* Receive Maximum Length register */
#define ENET_RXMAXLEN_REG 0x4
#define ENET_RXMAXLEN_SHIFT 0
#define ENET_RXMAXLEN_MASK (0x7ff << ENET_RXMAXLEN_SHIFT)
/* Transmit Maximum Length register */
#define ENET_TXMAXLEN_REG 0x8
#define ENET_TXMAXLEN_SHIFT 0
#define ENET_TXMAXLEN_MASK (0x7ff << ENET_TXMAXLEN_SHIFT)
/* MII Status/Control register */
#define ENET_MIISC_REG 0x10
#define ENET_MIISC_MDCFREQDIV_SHIFT 0
#define ENET_MIISC_MDCFREQDIV_MASK (0x7f << ENET_MIISC_MDCFREQDIV_SHIFT)
#define ENET_MIISC_PREAMBLEEN_SHIFT 7
#define ENET_MIISC_PREAMBLEEN_MASK (1 << ENET_MIISC_PREAMBLEEN_SHIFT)
/* MII Data register */
#define ENET_MIIDATA_REG 0x14
#define ENET_MIIDATA_DATA_SHIFT 0
#define ENET_MIIDATA_DATA_MASK (0xffff << ENET_MIIDATA_DATA_SHIFT)
#define ENET_MIIDATA_TA_SHIFT 16
#define ENET_MIIDATA_TA_MASK (0x3 << ENET_MIIDATA_TA_SHIFT)
#define ENET_MIIDATA_REG_SHIFT 18
#define ENET_MIIDATA_REG_MASK (0x1f << ENET_MIIDATA_REG_SHIFT)
#define ENET_MIIDATA_PHYID_SHIFT 23
#define ENET_MIIDATA_PHYID_MASK (0x1f << ENET_MIIDATA_PHYID_SHIFT)
#define ENET_MIIDATA_OP_READ_MASK (0x6 << 28)
#define ENET_MIIDATA_OP_WRITE_MASK (0x5 << 28)
/* Ethernet Interrupt Mask register */
#define ENET_IRMASK_REG 0x18
/* Ethernet Interrupt register */
#define ENET_IR_REG 0x1c
#define ENET_IR_MII (1 << 0)
#define ENET_IR_MIB (1 << 1)
#define ENET_IR_FLOWC (1 << 2)
/* Ethernet Control register */
#define ENET_CTL_REG 0x2c
#define ENET_CTL_ENABLE_SHIFT 0
#define ENET_CTL_ENABLE_MASK (1 << ENET_CTL_ENABLE_SHIFT)
#define ENET_CTL_DISABLE_SHIFT 1
#define ENET_CTL_DISABLE_MASK (1 << ENET_CTL_DISABLE_SHIFT)
#define ENET_CTL_SRESET_SHIFT 2
#define ENET_CTL_SRESET_MASK (1 << ENET_CTL_SRESET_SHIFT)
#define ENET_CTL_EPHYSEL_SHIFT 3
#define ENET_CTL_EPHYSEL_MASK (1 << ENET_CTL_EPHYSEL_SHIFT)
/* Transmit Control register */
#define ENET_TXCTL_REG 0x30
#define ENET_TXCTL_FD_SHIFT 0
#define ENET_TXCTL_FD_MASK (1 << ENET_TXCTL_FD_SHIFT)
/* Transmit Watermask register */
#define ENET_TXWMARK_REG 0x34
#define ENET_TXWMARK_WM_SHIFT 0
#define ENET_TXWMARK_WM_MASK (0x3f << ENET_TXWMARK_WM_SHIFT)
/* MIB Control register */
#define ENET_MIBCTL_REG 0x38
#define ENET_MIBCTL_RDCLEAR_SHIFT 0
#define ENET_MIBCTL_RDCLEAR_MASK (1 << ENET_MIBCTL_RDCLEAR_SHIFT)
/* Perfect Match Data Low register */
#define ENET_PML_REG(x) (0x58 + (x) * 8)
#define ENET_PMH_REG(x) (0x5c + (x) * 8)
#define ENET_PMH_DATAVALID_SHIFT 16
#define ENET_PMH_DATAVALID_MASK (1 << ENET_PMH_DATAVALID_SHIFT)
/* MIB register */
#define ENET_MIB_REG(x) (0x200 + (x) * 4)
#define ENET_MIB_REG_COUNT 55
/*************************************************************************
* _REG relative to RSET_ENETDMA
*************************************************************************/
/* Controller Configuration Register */
#define ENETDMA_CFG_REG (0x0)
#define ENETDMA_CFG_EN_SHIFT 0
#define ENETDMA_CFG_EN_MASK (1 << ENETDMA_CFG_EN_SHIFT)
#define ENETDMA_CFG_FLOWCH_MASK(x) (1 << ((x >> 1) + 1))
/* Flow Control Descriptor Low Threshold register */
#define ENETDMA_FLOWCL_REG(x) (0x4 + (x) * 6)
/* Flow Control Descriptor High Threshold register */
#define ENETDMA_FLOWCH_REG(x) (0x8 + (x) * 6)
/* Flow Control Descriptor Buffer Alloca Threshold register */
#define ENETDMA_BUFALLOC_REG(x) (0xc + (x) * 6)
#define ENETDMA_BUFALLOC_FORCE_SHIFT 31
#define ENETDMA_BUFALLOC_FORCE_MASK (1 << ENETDMA_BUFALLOC_FORCE_SHIFT)
/* Channel Configuration register */
#define ENETDMA_CHANCFG_REG(x) (0x100 + (x) * 0x10)
#define ENETDMA_CHANCFG_EN_SHIFT 0
#define ENETDMA_CHANCFG_EN_MASK (1 << ENETDMA_CHANCFG_EN_SHIFT)
#define ENETDMA_CHANCFG_PKTHALT_SHIFT 1
#define ENETDMA_CHANCFG_PKTHALT_MASK (1 << ENETDMA_CHANCFG_PKTHALT_SHIFT)
/* Interrupt Control/Status register */
#define ENETDMA_IR_REG(x) (0x104 + (x) * 0x10)
#define ENETDMA_IR_BUFDONE_MASK (1 << 0)
#define ENETDMA_IR_PKTDONE_MASK (1 << 1)
#define ENETDMA_IR_NOTOWNER_MASK (1 << 2)
/* Interrupt Mask register */
#define ENETDMA_IRMASK_REG(x) (0x108 + (x) * 0x10)
/* Maximum Burst Length */
#define ENETDMA_MAXBURST_REG(x) (0x10C + (x) * 0x10)
/* Ring Start Address register */
#define ENETDMA_RSTART_REG(x) (0x200 + (x) * 0x10)
/* State Ram Word 2 */
#define ENETDMA_SRAM2_REG(x) (0x204 + (x) * 0x10)
/* State Ram Word 3 */
#define ENETDMA_SRAM3_REG(x) (0x208 + (x) * 0x10)
/* State Ram Word 4 */
#define ENETDMA_SRAM4_REG(x) (0x20c + (x) * 0x10)
/*************************************************************************
* _REG relative to RSET_OHCI_PRIV
*************************************************************************/
#define OHCI_PRIV_REG 0x0
#define OHCI_PRIV_PORT1_HOST_SHIFT 0
#define OHCI_PRIV_PORT1_HOST_MASK (1 << OHCI_PRIV_PORT1_HOST_SHIFT)
#define OHCI_PRIV_REG_SWAP_SHIFT 3
#define OHCI_PRIV_REG_SWAP_MASK (1 << OHCI_PRIV_REG_SWAP_SHIFT)
/*************************************************************************
* _REG relative to RSET_USBH_PRIV
*************************************************************************/
#define USBH_PRIV_SWAP_REG 0x0
#define USBH_PRIV_SWAP_EHCI_ENDN_SHIFT 4
#define USBH_PRIV_SWAP_EHCI_ENDN_MASK (1 << USBH_PRIV_SWAP_EHCI_ENDN_SHIFT)
#define USBH_PRIV_SWAP_EHCI_DATA_SHIFT 3
#define USBH_PRIV_SWAP_EHCI_DATA_MASK (1 << USBH_PRIV_SWAP_EHCI_DATA_SHIFT)
#define USBH_PRIV_SWAP_OHCI_ENDN_SHIFT 1
#define USBH_PRIV_SWAP_OHCI_ENDN_MASK (1 << USBH_PRIV_SWAP_OHCI_ENDN_SHIFT)
#define USBH_PRIV_SWAP_OHCI_DATA_SHIFT 0
#define USBH_PRIV_SWAP_OHCI_DATA_MASK (1 << USBH_PRIV_SWAP_OHCI_DATA_SHIFT)
#define USBH_PRIV_TEST_REG 0x24
/*************************************************************************
* _REG relative to RSET_MPI
*************************************************************************/
/* well known (hard wired) chip select */
#define MPI_CS_PCMCIA_COMMON 4
#define MPI_CS_PCMCIA_ATTR 5
#define MPI_CS_PCMCIA_IO 6
/* Chip select base register */
#define MPI_CSBASE_REG(x) (0x0 + (x) * 8)
#define MPI_CSBASE_BASE_SHIFT 13
#define MPI_CSBASE_BASE_MASK (0x1ffff << MPI_CSBASE_BASE_SHIFT)
#define MPI_CSBASE_SIZE_SHIFT 0
#define MPI_CSBASE_SIZE_MASK (0xf << MPI_CSBASE_SIZE_SHIFT)
#define MPI_CSBASE_SIZE_8K 0
#define MPI_CSBASE_SIZE_16K 1
#define MPI_CSBASE_SIZE_32K 2
#define MPI_CSBASE_SIZE_64K 3
#define MPI_CSBASE_SIZE_128K 4
#define MPI_CSBASE_SIZE_256K 5
#define MPI_CSBASE_SIZE_512K 6
#define MPI_CSBASE_SIZE_1M 7
#define MPI_CSBASE_SIZE_2M 8
#define MPI_CSBASE_SIZE_4M 9
#define MPI_CSBASE_SIZE_8M 10
#define MPI_CSBASE_SIZE_16M 11
#define MPI_CSBASE_SIZE_32M 12
#define MPI_CSBASE_SIZE_64M 13
#define MPI_CSBASE_SIZE_128M 14
#define MPI_CSBASE_SIZE_256M 15
/* Chip select control register */
#define MPI_CSCTL_REG(x) (0x4 + (x) * 8)
#define MPI_CSCTL_ENABLE_MASK (1 << 0)
#define MPI_CSCTL_WAIT_SHIFT 1
#define MPI_CSCTL_WAIT_MASK (0x7 << MPI_CSCTL_WAIT_SHIFT)
#define MPI_CSCTL_DATA16_MASK (1 << 4)
#define MPI_CSCTL_SYNCMODE_MASK (1 << 7)
#define MPI_CSCTL_TSIZE_MASK (1 << 8)
#define MPI_CSCTL_ENDIANSWAP_MASK (1 << 10)
#define MPI_CSCTL_SETUP_SHIFT 16
#define MPI_CSCTL_SETUP_MASK (0xf << MPI_CSCTL_SETUP_SHIFT)
#define MPI_CSCTL_HOLD_SHIFT 20
#define MPI_CSCTL_HOLD_MASK (0xf << MPI_CSCTL_HOLD_SHIFT)
/* PCI registers */
#define MPI_SP0_RANGE_REG 0x100
#define MPI_SP0_REMAP_REG 0x104
#define MPI_SP0_REMAP_ENABLE_MASK (1 << 0)
#define MPI_SP1_RANGE_REG 0x10C
#define MPI_SP1_REMAP_REG 0x110
#define MPI_SP1_REMAP_ENABLE_MASK (1 << 0)
#define MPI_L2PCFG_REG 0x11C
#define MPI_L2PCFG_CFG_TYPE_SHIFT 0
#define MPI_L2PCFG_CFG_TYPE_MASK (0x3 << MPI_L2PCFG_CFG_TYPE_SHIFT)
#define MPI_L2PCFG_REG_SHIFT 2
#define MPI_L2PCFG_REG_MASK (0x3f << MPI_L2PCFG_REG_SHIFT)
#define MPI_L2PCFG_FUNC_SHIFT 8
#define MPI_L2PCFG_FUNC_MASK (0x7 << MPI_L2PCFG_FUNC_SHIFT)
#define MPI_L2PCFG_DEVNUM_SHIFT 11
#define MPI_L2PCFG_DEVNUM_MASK (0x1f << MPI_L2PCFG_DEVNUM_SHIFT)
#define MPI_L2PCFG_CFG_USEREG_MASK (1 << 30)
#define MPI_L2PCFG_CFG_SEL_MASK (1 << 31)
#define MPI_L2PMEMRANGE1_REG 0x120
#define MPI_L2PMEMBASE1_REG 0x124
#define MPI_L2PMEMREMAP1_REG 0x128
#define MPI_L2PMEMRANGE2_REG 0x12C
#define MPI_L2PMEMBASE2_REG 0x130
#define MPI_L2PMEMREMAP2_REG 0x134
#define MPI_L2PIORANGE_REG 0x138
#define MPI_L2PIOBASE_REG 0x13C
#define MPI_L2PIOREMAP_REG 0x140
#define MPI_L2P_BASE_MASK (0xffff8000)
#define MPI_L2PREMAP_ENABLED_MASK (1 << 0)
#define MPI_L2PREMAP_IS_CARDBUS_MASK (1 << 2)
#define MPI_PCIMODESEL_REG 0x144
#define MPI_PCIMODESEL_BAR1_NOSWAP_MASK (1 << 0)
#define MPI_PCIMODESEL_BAR2_NOSWAP_MASK (1 << 1)
#define MPI_PCIMODESEL_EXT_ARB_MASK (1 << 2)
#define MPI_PCIMODESEL_PREFETCH_SHIFT 4
#define MPI_PCIMODESEL_PREFETCH_MASK (0xf << MPI_PCIMODESEL_PREFETCH_SHIFT)
#define MPI_LOCBUSCTL_REG 0x14C
#define MPI_LOCBUSCTL_EN_PCI_GPIO_MASK (1 << 0)
#define MPI_LOCBUSCTL_U2P_NOSWAP_MASK (1 << 1)
#define MPI_LOCINT_REG 0x150
#define MPI_LOCINT_MASK(x) (1 << (x + 16))
#define MPI_LOCINT_STAT(x) (1 << (x))
#define MPI_LOCINT_DIR_FAILED 6
#define MPI_LOCINT_EXT_PCI_INT 7
#define MPI_LOCINT_SERR 8
#define MPI_LOCINT_CSERR 9
#define MPI_PCICFGCTL_REG 0x178
#define MPI_PCICFGCTL_CFGADDR_SHIFT 2
#define MPI_PCICFGCTL_CFGADDR_MASK (0x1f << MPI_PCICFGCTL_CFGADDR_SHIFT)
#define MPI_PCICFGCTL_WRITEEN_MASK (1 << 7)
#define MPI_PCICFGDATA_REG 0x17C
/* PCI host bridge custom register */
#define BCMPCI_REG_TIMERS 0x40
#define REG_TIMER_TRDY_SHIFT 0
#define REG_TIMER_TRDY_MASK (0xff << REG_TIMER_TRDY_SHIFT)
#define REG_TIMER_RETRY_SHIFT 8
#define REG_TIMER_RETRY_MASK (0xff << REG_TIMER_RETRY_SHIFT)
/*************************************************************************
* _REG relative to RSET_PCMCIA
*************************************************************************/
#define PCMCIA_C1_REG 0x0
#define PCMCIA_C1_CD1_MASK (1 << 0)
#define PCMCIA_C1_CD2_MASK (1 << 1)
#define PCMCIA_C1_VS1_MASK (1 << 2)
#define PCMCIA_C1_VS2_MASK (1 << 3)
#define PCMCIA_C1_VS1OE_MASK (1 << 6)
#define PCMCIA_C1_VS2OE_MASK (1 << 7)
#define PCMCIA_C1_CBIDSEL_SHIFT (8)
#define PCMCIA_C1_CBIDSEL_MASK (0x1f << PCMCIA_C1_CBIDSEL_SHIFT)
#define PCMCIA_C1_EN_PCMCIA_GPIO_MASK (1 << 13)
#define PCMCIA_C1_EN_PCMCIA_MASK (1 << 14)
#define PCMCIA_C1_EN_CARDBUS_MASK (1 << 15)
#define PCMCIA_C1_RESET_MASK (1 << 18)
#define PCMCIA_C2_REG 0x8
#define PCMCIA_C2_DATA16_MASK (1 << 0)
#define PCMCIA_C2_BYTESWAP_MASK (1 << 1)
#define PCMCIA_C2_RWCOUNT_SHIFT 2
#define PCMCIA_C2_RWCOUNT_MASK (0x3f << PCMCIA_C2_RWCOUNT_SHIFT)
#define PCMCIA_C2_INACTIVE_SHIFT 8
#define PCMCIA_C2_INACTIVE_MASK (0x3f << PCMCIA_C2_INACTIVE_SHIFT)
#define PCMCIA_C2_SETUP_SHIFT 16
#define PCMCIA_C2_SETUP_MASK (0x3f << PCMCIA_C2_SETUP_SHIFT)
#define PCMCIA_C2_HOLD_SHIFT 24
#define PCMCIA_C2_HOLD_MASK (0x3f << PCMCIA_C2_HOLD_SHIFT)
/*************************************************************************
* _REG relative to RSET_SDRAM
*************************************************************************/
#define SDRAM_CFG_REG 0x0
#define SDRAM_CFG_ROW_SHIFT 4
#define SDRAM_CFG_ROW_MASK (0x3 << SDRAM_CFG_ROW_SHIFT)
#define SDRAM_CFG_COL_SHIFT 6
#define SDRAM_CFG_COL_MASK (0x3 << SDRAM_CFG_COL_SHIFT)
#define SDRAM_CFG_32B_SHIFT 10
#define SDRAM_CFG_32B_MASK (1 << SDRAM_CFG_32B_SHIFT)
#define SDRAM_CFG_BANK_SHIFT 13
#define SDRAM_CFG_BANK_MASK (1 << SDRAM_CFG_BANK_SHIFT)
#define SDRAM_PRIO_REG 0x2C
#define SDRAM_PRIO_MIPS_SHIFT 29
#define SDRAM_PRIO_MIPS_MASK (1 << SDRAM_PRIO_MIPS_SHIFT)
#define SDRAM_PRIO_ADSL_SHIFT 30
#define SDRAM_PRIO_ADSL_MASK (1 << SDRAM_PRIO_ADSL_SHIFT)
#define SDRAM_PRIO_EN_SHIFT 31
#define SDRAM_PRIO_EN_MASK (1 << SDRAM_PRIO_EN_SHIFT)
/*************************************************************************
* _REG relative to RSET_MEMC
*************************************************************************/
#define MEMC_CFG_REG 0x4
#define MEMC_CFG_32B_SHIFT 1
#define MEMC_CFG_32B_MASK (1 << MEMC_CFG_32B_SHIFT)
#define MEMC_CFG_COL_SHIFT 3
#define MEMC_CFG_COL_MASK (0x3 << MEMC_CFG_COL_SHIFT)
#define MEMC_CFG_ROW_SHIFT 6
#define MEMC_CFG_ROW_MASK (0x3 << MEMC_CFG_ROW_SHIFT)
/*************************************************************************
* _REG relative to RSET_DDR
*************************************************************************/
#define DDR_DMIPSPLLCFG_REG 0x18
#define DMIPSPLLCFG_M1_SHIFT 0
#define DMIPSPLLCFG_M1_MASK (0xff << DMIPSPLLCFG_M1_SHIFT)
#define DMIPSPLLCFG_N1_SHIFT 23
#define DMIPSPLLCFG_N1_MASK (0x3f << DMIPSPLLCFG_N1_SHIFT)
#define DMIPSPLLCFG_N2_SHIFT 29
#define DMIPSPLLCFG_N2_MASK (0x7 << DMIPSPLLCFG_N2_SHIFT)
#endif /* BCM63XX_REGS_H_ */

11
arch/mips/include/asm/mach-bcm63xx/bcm63xx_timer.h Normal file
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@ -0,0 +1,11 @@
#ifndef BCM63XX_TIMER_H_
#define BCM63XX_TIMER_H_
int bcm63xx_timer_register(int id, void (*callback)(void *data), void *data);
void bcm63xx_timer_unregister(int id);
int bcm63xx_timer_set(int id, int monotonic, unsigned int countdown_us);
int bcm63xx_timer_enable(int id);
int bcm63xx_timer_disable(int id);
unsigned int bcm63xx_timer_countdown(unsigned int countdown_us);
#endif /* !BCM63XX_TIMER_H_ */

60
arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h Normal file
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@ -0,0 +1,60 @@
#ifndef BOARD_BCM963XX_H_
#define BOARD_BCM963XX_H_
#include <linux/types.h>
#include <linux/gpio.h>
#include <linux/leds.h>
#include <bcm63xx_dev_enet.h>
#include <bcm63xx_dev_dsp.h>
/*
* flash mapping
*/
#define BCM963XX_CFE_VERSION_OFFSET 0x570
#define BCM963XX_NVRAM_OFFSET 0x580
/*
* nvram structure
*/
struct bcm963xx_nvram {
u32 version;
u8 reserved1[256];
u8 name[16];
u32 main_tp_number;
u32 psi_size;
u32 mac_addr_count;
u8 mac_addr_base[6];
u8 reserved2[2];
u32 checksum_old;
u8 reserved3[720];
u32 checksum_high;
};
/*
* board definition
*/
struct board_info {
u8 name[16];
unsigned int expected_cpu_id;
/* enabled feature/device */
unsigned int has_enet0:1;
unsigned int has_enet1:1;
unsigned int has_pci:1;
unsigned int has_pccard:1;
unsigned int has_ohci0:1;
unsigned int has_ehci0:1;
unsigned int has_dsp:1;
/* ethernet config */
struct bcm63xx_enet_platform_data enet0;
struct bcm63xx_enet_platform_data enet1;
/* DSP config */
struct bcm63xx_dsp_platform_data dsp;
/* GPIO LEDs */
struct gpio_led leds[5];
};
#endif /* ! BOARD_BCM963XX_H_ */

51
arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h Normal file
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@ -0,0 +1,51 @@
#ifndef __ASM_MACH_BCM963XX_CPU_FEATURE_OVERRIDES_H
#define __ASM_MACH_BCM963XX_CPU_FEATURE_OVERRIDES_H
#include <bcm63xx_cpu.h>
#define cpu_has_tlb 1
#define cpu_has_4kex 1
#define cpu_has_4k_cache 1
#define cpu_has_fpu 0
#define cpu_has_32fpr 0
#define cpu_has_counter 1
#define cpu_has_watch 0
#define cpu_has_divec 1
#define cpu_has_vce 0
#define cpu_has_cache_cdex_p 0
#define cpu_has_cache_cdex_s 0
#define cpu_has_prefetch 1
#define cpu_has_mcheck 1
#define cpu_has_ejtag 1
#define cpu_has_llsc 1
#define cpu_has_mips16 0
#define cpu_has_mdmx 0
#define cpu_has_mips3d 0
#define cpu_has_smartmips 0
#define cpu_has_vtag_icache 0
#if !defined(BCMCPU_RUNTIME_DETECT) && (defined(CONFIG_BCMCPU_IS_6348) || defined(CONFIG_CPU_IS_6338) || defined(CONFIG_CPU_IS_BCM6345))
#define cpu_has_dc_aliases 0
#endif
#define cpu_has_ic_fills_f_dc 0
#define cpu_has_pindexed_dcache 0
#define cpu_has_mips32r1 1
#define cpu_has_mips32r2 0
#define cpu_has_mips64r1 0
#define cpu_has_mips64r2 0
#define cpu_has_dsp 0
#define cpu_has_mipsmt 0
#define cpu_has_userlocal 0
#define cpu_has_nofpuex 0
#define cpu_has_64bits 0
#define cpu_has_64bit_zero_reg 0
#define cpu_dcache_line_size() 16
#define cpu_icache_line_size() 16
#define cpu_scache_line_size() 0
#endif /* __ASM_MACH_BCM963XX_CPU_FEATURE_OVERRIDES_H */

15
arch/mips/include/asm/mach-bcm63xx/gpio.h Normal file
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@ -0,0 +1,15 @@
#ifndef __ASM_MIPS_MACH_BCM63XX_GPIO_H
#define __ASM_MIPS_MACH_BCM63XX_GPIO_H
#include <bcm63xx_gpio.h>
#define gpio_to_irq(gpio) NULL
#define gpio_get_value __gpio_get_value
#define gpio_set_value __gpio_set_value
#define gpio_cansleep __gpio_cansleep
#include <asm-generic/gpio.h>
#endif /* __ASM_MIPS_MACH_BCM63XX_GPIO_H */

25
arch/mips/include/asm/mach-bcm63xx/war.h Normal file
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@ -0,0 +1,25 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
*/
#ifndef __ASM_MIPS_MACH_BCM63XX_WAR_H
#define __ASM_MIPS_MACH_BCM63XX_WAR_H
#define R4600_V1_INDEX_ICACHEOP_WAR 0
#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
#define R5432_CP0_INTERRUPT_WAR 0
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS4K_ICACHE_REFILL_WAR 0
#define MIPS_CACHE_SYNC_WAR 0
#define TX49XX_ICACHE_INDEX_INV_WAR 0
#define RM9000_CDEX_SMP_WAR 0
#define ICACHE_REFILLS_WORKAROUND_WAR 0
#define R10000_LLSC_WAR 0
#define MIPS34K_MISSED_ITLB_WAR 0
#endif /* __ASM_MIPS_MACH_BCM63XX_WAR_H */

2
arch/mips/pci/Makefile
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@ -16,6 +16,8 @@ obj-$(CONFIG_PCI_VR41XX) += ops-vr41xx.o pci-vr41xx.o
obj-$(CONFIG_NEC_MARKEINS) += ops-emma2rh.o pci-emma2rh.o fixup-emma2rh.o obj-$(CONFIG_NEC_MARKEINS) += ops-emma2rh.o pci-emma2rh.o fixup-emma2rh.o
obj-$(CONFIG_PCI_TX4927) += ops-tx4927.o obj-$(CONFIG_PCI_TX4927) += ops-tx4927.o
obj-$(CONFIG_BCM47XX) += pci-bcm47xx.o obj-$(CONFIG_BCM47XX) += pci-bcm47xx.o
obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o fixup-bcm63xx.o \
ops-bcm63xx.o
# #
# These are still pretty much in the old state, watch, go blind. # These are still pretty much in the old state, watch, go blind.

21
arch/mips/pci/fixup-bcm63xx.c Normal file
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@ -0,0 +1,21 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
*/
#include <linux/types.h>
#include <linux/pci.h>
#include <bcm63xx_cpu.h>
int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
return bcm63xx_get_irq_number(IRQ_PCI);
}
int pcibios_plat_dev_init(struct pci_dev *dev)
{
return 0;
}

467
arch/mips/pci/ops-bcm63xx.c Normal file
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@ -0,0 +1,467 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
*/
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/io.h>
#include "pci-bcm63xx.h"
/*
* swizzle 32bits data to return only the needed part
*/
static int postprocess_read(u32 data, int where, unsigned int size)
{
u32 ret;
ret = 0;
switch (size) {
case 1:
ret = (data >> ((where & 3) << 3)) & 0xff;
break;
case 2:
ret = (data >> ((where & 3) << 3)) & 0xffff;
break;
case 4:
ret = data;
break;
}
return ret;
}
static int preprocess_write(u32 orig_data, u32 val, int where,
unsigned int size)
{
u32 ret;
ret = 0;
switch (size) {
case 1:
ret = (orig_data & ~(0xff << ((where & 3) << 3))) |
(val << ((where & 3) << 3));
break;
case 2:
ret = (orig_data & ~(0xffff << ((where & 3) << 3))) |
(val << ((where & 3) << 3));
break;
case 4:
ret = val;
break;
}
return ret;
}
/*
* setup hardware for a configuration cycle with given parameters
*/
static int bcm63xx_setup_cfg_access(int type, unsigned int busn,
unsigned int devfn, int where)
{
unsigned int slot, func, reg;
u32 val;
slot = PCI_SLOT(devfn);
func = PCI_FUNC(devfn);
reg = where >> 2;
/* sanity check */
if (slot > (MPI_L2PCFG_DEVNUM_MASK >> MPI_L2PCFG_DEVNUM_SHIFT))
return 1;
if (func > (MPI_L2PCFG_FUNC_MASK >> MPI_L2PCFG_FUNC_SHIFT))
return 1;
if (reg > (MPI_L2PCFG_REG_MASK >> MPI_L2PCFG_REG_SHIFT))
return 1;
/* ok, setup config access */
val = (reg << MPI_L2PCFG_REG_SHIFT);
val |= (func << MPI_L2PCFG_FUNC_SHIFT);
val |= (slot << MPI_L2PCFG_DEVNUM_SHIFT);
val |= MPI_L2PCFG_CFG_USEREG_MASK;
val |= MPI_L2PCFG_CFG_SEL_MASK;
/* type 0 cycle for local bus, type 1 cycle for anything else */
if (type != 0) {
/* FIXME: how to specify bus ??? */
val |= (1 << MPI_L2PCFG_CFG_TYPE_SHIFT);
}
bcm_mpi_writel(val, MPI_L2PCFG_REG);
return 0;
}
static int bcm63xx_do_cfg_read(int type, unsigned int busn,
unsigned int devfn, int where, int size,
u32 *val)
{
u32 data;
/* two phase cycle, first we write address, then read data at
* another location, caller already has a spinlock so no need
* to add one here */
if (bcm63xx_setup_cfg_access(type, busn, devfn, where))
return PCIBIOS_DEVICE_NOT_FOUND;
iob();
data = le32_to_cpu(__raw_readl(pci_iospace_start));
/* restore IO space normal behaviour */
bcm_mpi_writel(0, MPI_L2PCFG_REG);
*val = postprocess_read(data, where, size);
return PCIBIOS_SUCCESSFUL;
}
static int bcm63xx_do_cfg_write(int type, unsigned int busn,
unsigned int devfn, int where, int size,
u32 val)
{
u32 data;
/* two phase cycle, first we write address, then write data to
* another location, caller already has a spinlock so no need
* to add one here */
if (bcm63xx_setup_cfg_access(type, busn, devfn, where))
return PCIBIOS_DEVICE_NOT_FOUND;
iob();
data = le32_to_cpu(__raw_readl(pci_iospace_start));
data = preprocess_write(data, val, where, size);
__raw_writel(cpu_to_le32(data), pci_iospace_start);
wmb();
/* no way to know the access is done, we have to wait */
udelay(500);
/* restore IO space normal behaviour */
bcm_mpi_writel(0, MPI_L2PCFG_REG);
return PCIBIOS_SUCCESSFUL;
}
static int bcm63xx_pci_read(struct pci_bus *bus, unsigned int devfn,
int where, int size, u32 *val)
{
int type;
type = bus->parent ? 1 : 0;
if (type == 0 && PCI_SLOT(devfn) == CARDBUS_PCI_IDSEL)
return PCIBIOS_DEVICE_NOT_FOUND;
return bcm63xx_do_cfg_read(type, bus->number, devfn,
where, size, val);
}
static int bcm63xx_pci_write(struct pci_bus *bus, unsigned int devfn,
int where, int size, u32 val)
{
int type;
type = bus->parent ? 1 : 0;
if (type == 0 && PCI_SLOT(devfn) == CARDBUS_PCI_IDSEL)
return PCIBIOS_DEVICE_NOT_FOUND;
return bcm63xx_do_cfg_write(type, bus->number, devfn,
where, size, val);
}
struct pci_ops bcm63xx_pci_ops = {
.read = bcm63xx_pci_read,
.write = bcm63xx_pci_write
};
#ifdef CONFIG_CARDBUS
/*
* emulate configuration read access on a cardbus bridge
*/
#define FAKE_CB_BRIDGE_SLOT 0x1e
static int fake_cb_bridge_bus_number = -1;
static struct {
u16 pci_command;
u8 cb_latency;
u8 subordinate_busn;
u8 cardbus_busn;
u8 pci_busn;
int bus_assigned;
u16 bridge_control;
u32 mem_base0;
u32 mem_limit0;
u32 mem_base1;
u32 mem_limit1;
u32 io_base0;
u32 io_limit0;
u32 io_base1;
u32 io_limit1;
} fake_cb_bridge_regs;
static int fake_cb_bridge_read(int where, int size, u32 *val)
{
unsigned int reg;
u32 data;
data = 0;
reg = where >> 2;
switch (reg) {
case (PCI_VENDOR_ID >> 2):
case (PCI_CB_SUBSYSTEM_VENDOR_ID >> 2):
/* create dummy vendor/device id from our cpu id */
data = (bcm63xx_get_cpu_id() << 16) | PCI_VENDOR_ID_BROADCOM;
break;
case (PCI_COMMAND >> 2):
data = (PCI_STATUS_DEVSEL_SLOW << 16);
data |= fake_cb_bridge_regs.pci_command;
break;
case (PCI_CLASS_REVISION >> 2):
data = (PCI_CLASS_BRIDGE_CARDBUS << 16);
break;
case (PCI_CACHE_LINE_SIZE >> 2):
data = (PCI_HEADER_TYPE_CARDBUS << 16);
break;
case (PCI_INTERRUPT_LINE >> 2):
/* bridge control */
data = (fake_cb_bridge_regs.bridge_control << 16);
/* pin:intA line:0xff */
data |= (0x1 << 8) | 0xff;
break;
case (PCI_CB_PRIMARY_BUS >> 2):
data = (fake_cb_bridge_regs.cb_latency << 24);
data |= (fake_cb_bridge_regs.subordinate_busn << 16);
data |= (fake_cb_bridge_regs.cardbus_busn << 8);
data |= fake_cb_bridge_regs.pci_busn;
break;
case (PCI_CB_MEMORY_BASE_0 >> 2):
data = fake_cb_bridge_regs.mem_base0;
break;
case (PCI_CB_MEMORY_LIMIT_0 >> 2):
data = fake_cb_bridge_regs.mem_limit0;
break;
case (PCI_CB_MEMORY_BASE_1 >> 2):
data = fake_cb_bridge_regs.mem_base1;
break;
case (PCI_CB_MEMORY_LIMIT_1 >> 2):
data = fake_cb_bridge_regs.mem_limit1;
break;
case (PCI_CB_IO_BASE_0 >> 2):
/* | 1 for 32bits io support */
data = fake_cb_bridge_regs.io_base0 | 0x1;
break;
case (PCI_CB_IO_LIMIT_0 >> 2):
data = fake_cb_bridge_regs.io_limit0;
break;
case (PCI_CB_IO_BASE_1 >> 2):
/* | 1 for 32bits io support */
data = fake_cb_bridge_regs.io_base1 | 0x1;
break;
case (PCI_CB_IO_LIMIT_1 >> 2):
data = fake_cb_bridge_regs.io_limit1;
break;
}
*val = postprocess_read(data, where, size);
return PCIBIOS_SUCCESSFUL;
}
/*
* emulate configuration write access on a cardbus bridge
*/
static int fake_cb_bridge_write(int where, int size, u32 val)
{
unsigned int reg;
u32 data, tmp;
int ret;
ret = fake_cb_bridge_read((where & ~0x3), 4, &data);
if (ret != PCIBIOS_SUCCESSFUL)
return ret;
data = preprocess_write(data, val, where, size);
reg = where >> 2;
switch (reg) {
case (PCI_COMMAND >> 2):
fake_cb_bridge_regs.pci_command = (data & 0xffff);
break;
case (PCI_CB_PRIMARY_BUS >> 2):
fake_cb_bridge_regs.cb_latency = (data >> 24) & 0xff;
fake_cb_bridge_regs.subordinate_busn = (data >> 16) & 0xff;
fake_cb_bridge_regs.cardbus_busn = (data >> 8) & 0xff;
fake_cb_bridge_regs.pci_busn = data & 0xff;
if (fake_cb_bridge_regs.cardbus_busn)
fake_cb_bridge_regs.bus_assigned = 1;
break;
case (PCI_INTERRUPT_LINE >> 2):
tmp = (data >> 16) & 0xffff;
/* disable memory prefetch support */
tmp &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
tmp &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1;
fake_cb_bridge_regs.bridge_control = tmp;
break;
case (PCI_CB_MEMORY_BASE_0 >> 2):
fake_cb_bridge_regs.mem_base0 = data;
break;
case (PCI_CB_MEMORY_LIMIT_0 >> 2):
fake_cb_bridge_regs.mem_limit0 = data;
break;
case (PCI_CB_MEMORY_BASE_1 >> 2):
fake_cb_bridge_regs.mem_base1 = data;
break;
case (PCI_CB_MEMORY_LIMIT_1 >> 2):
fake_cb_bridge_regs.mem_limit1 = data;
break;
case (PCI_CB_IO_BASE_0 >> 2):
fake_cb_bridge_regs.io_base0 = data;
break;
case (PCI_CB_IO_LIMIT_0 >> 2):
fake_cb_bridge_regs.io_limit0 = data;
break;
case (PCI_CB_IO_BASE_1 >> 2):
fake_cb_bridge_regs.io_base1 = data;
break;
case (PCI_CB_IO_LIMIT_1 >> 2):
fake_cb_bridge_regs.io_limit1 = data;
break;
}
return PCIBIOS_SUCCESSFUL;
}
static int bcm63xx_cb_read(struct pci_bus *bus, unsigned int devfn,
int where, int size, u32 *val)
{
/* snoop access to slot 0x1e on root bus, we fake a cardbus
* bridge at this location */
if (!bus->parent && PCI_SLOT(devfn) == FAKE_CB_BRIDGE_SLOT) {
fake_cb_bridge_bus_number = bus->number;
return fake_cb_bridge_read(where, size, val);
}
/* a configuration cycle for the device behind the cardbus
* bridge is actually done as a type 0 cycle on the primary
* bus. This means that only one device can be on the cardbus
* bus */
if (fake_cb_bridge_regs.bus_assigned &&
bus->number == fake_cb_bridge_regs.cardbus_busn &&
PCI_SLOT(devfn) == 0)
return bcm63xx_do_cfg_read(0, 0,
PCI_DEVFN(CARDBUS_PCI_IDSEL, 0),
where, size, val);
return PCIBIOS_DEVICE_NOT_FOUND;
}
static int bcm63xx_cb_write(struct pci_bus *bus, unsigned int devfn,
int where, int size, u32 val)
{
if (!bus->parent && PCI_SLOT(devfn) == FAKE_CB_BRIDGE_SLOT) {
fake_cb_bridge_bus_number = bus->number;
return fake_cb_bridge_write(where, size, val);
}
if (fake_cb_bridge_regs.bus_assigned &&
bus->number == fake_cb_bridge_regs.cardbus_busn &&
PCI_SLOT(devfn) == 0)
return bcm63xx_do_cfg_write(0, 0,
PCI_DEVFN(CARDBUS_PCI_IDSEL, 0),
where, size, val);
return PCIBIOS_DEVICE_NOT_FOUND;
}
struct pci_ops bcm63xx_cb_ops = {
.read = bcm63xx_cb_read,
.write = bcm63xx_cb_write,
};
/*
* only one IO window, so it cannot be shared by PCI and cardbus, use
* fixup to choose and detect unhandled configuration
*/
static void bcm63xx_fixup(struct pci_dev *dev)
{
static int io_window = -1;
int i, found, new_io_window;
u32 val;
/* look for any io resource */
found = 0;
for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
found = 1;
break;
}
}
if (!found)
return;
/* skip our fake bus with only cardbus bridge on it */
if (dev->bus->number == fake_cb_bridge_bus_number)
return;
/* find on which bus the device is */
if (fake_cb_bridge_regs.bus_assigned &&
dev->bus->number == fake_cb_bridge_regs.cardbus_busn &&
PCI_SLOT(dev->devfn) == 0)
new_io_window = 1;
else
new_io_window = 0;
if (new_io_window == io_window)
return;
if (io_window != -1) {
printk(KERN_ERR "bcm63xx: both PCI and cardbus devices "
"need IO, which hardware cannot do\n");
return;
}
printk(KERN_INFO "bcm63xx: PCI IO window assigned to %s\n",
(new_io_window == 0) ? "PCI" : "cardbus");
val = bcm_mpi_readl(MPI_L2PIOREMAP_REG);
if (io_window)
val |= MPI_L2PREMAP_IS_CARDBUS_MASK;
else
val &= ~MPI_L2PREMAP_IS_CARDBUS_MASK;
bcm_mpi_writel(val, MPI_L2PIOREMAP_REG);
io_window = new_io_window;
}
DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, bcm63xx_fixup);
#endif

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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
*/
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <asm/bootinfo.h>
#include "pci-bcm63xx.h"
/*
* Allow PCI to be disabled at runtime depending on board nvram
* configuration
*/
int bcm63xx_pci_enabled;
static struct resource bcm_pci_mem_resource = {
.name = "bcm63xx PCI memory space",
.start = BCM_PCI_MEM_BASE_PA,
.end = BCM_PCI_MEM_END_PA,
.flags = IORESOURCE_MEM
};
static struct resource bcm_pci_io_resource = {
.name = "bcm63xx PCI IO space",
.start = BCM_PCI_IO_BASE_PA,
#ifdef CONFIG_CARDBUS
.end = BCM_PCI_IO_HALF_PA,
#else
.end = BCM_PCI_IO_END_PA,
#endif
.flags = IORESOURCE_IO
};
struct pci_controller bcm63xx_controller = {
.pci_ops = &bcm63xx_pci_ops,
.io_resource = &bcm_pci_io_resource,
.mem_resource = &bcm_pci_mem_resource,
};
/*
* We handle cardbus via a fake Cardbus bridge, memory and io spaces
* have to be clearly separated from PCI one since we have different
* memory decoder.
*/
#ifdef CONFIG_CARDBUS
static struct resource bcm_cb_mem_resource = {
.name = "bcm63xx Cardbus memory space",
.start = BCM_CB_MEM_BASE_PA,
.end = BCM_CB_MEM_END_PA,
.flags = IORESOURCE_MEM
};
static struct resource bcm_cb_io_resource = {
.name = "bcm63xx Cardbus IO space",
.start = BCM_PCI_IO_HALF_PA + 1,
.end = BCM_PCI_IO_END_PA,
.flags = IORESOURCE_IO
};
struct pci_controller bcm63xx_cb_controller = {
.pci_ops = &bcm63xx_cb_ops,
.io_resource = &bcm_cb_io_resource,
.mem_resource = &bcm_cb_mem_resource,
};
#endif
static u32 bcm63xx_int_cfg_readl(u32 reg)
{
u32 tmp;
tmp = reg & MPI_PCICFGCTL_CFGADDR_MASK;
tmp |= MPI_PCICFGCTL_WRITEEN_MASK;
bcm_mpi_writel(tmp, MPI_PCICFGCTL_REG);
iob();
return bcm_mpi_readl(MPI_PCICFGDATA_REG);
}
static void bcm63xx_int_cfg_writel(u32 val, u32 reg)
{
u32 tmp;
tmp = reg & MPI_PCICFGCTL_CFGADDR_MASK;
tmp |= MPI_PCICFGCTL_WRITEEN_MASK;
bcm_mpi_writel(tmp, MPI_PCICFGCTL_REG);
bcm_mpi_writel(val, MPI_PCICFGDATA_REG);
}
void __iomem *pci_iospace_start;
static int __init bcm63xx_pci_init(void)
{
unsigned int mem_size;
u32 val;
if (!BCMCPU_IS_6348() && !BCMCPU_IS_6358())
return -ENODEV;
if (!bcm63xx_pci_enabled)
return -ENODEV;
/*
* configuration access are done through IO space, remap 4
* first bytes to access it from CPU.
*
* this means that no io access from CPU should happen while
* we do a configuration cycle, but there's no way we can add
* a spinlock for each io access, so this is currently kind of
* broken on SMP.
*/
pci_iospace_start = ioremap_nocache(BCM_PCI_IO_BASE_PA, 4);
if (!pci_iospace_start)
return -ENOMEM;
/* setup local bus to PCI access (PCI memory) */
val = BCM_PCI_MEM_BASE_PA & MPI_L2P_BASE_MASK;
bcm_mpi_writel(val, MPI_L2PMEMBASE1_REG);
bcm_mpi_writel(~(BCM_PCI_MEM_SIZE - 1), MPI_L2PMEMRANGE1_REG);
bcm_mpi_writel(val | MPI_L2PREMAP_ENABLED_MASK, MPI_L2PMEMREMAP1_REG);
/* set Cardbus IDSEL (type 0 cfg access on primary bus for
* this IDSEL will be done on Cardbus instead) */
val = bcm_pcmcia_readl(PCMCIA_C1_REG);
val &= ~PCMCIA_C1_CBIDSEL_MASK;
val |= (CARDBUS_PCI_IDSEL << PCMCIA_C1_CBIDSEL_SHIFT);
bcm_pcmcia_writel(val, PCMCIA_C1_REG);
#ifdef CONFIG_CARDBUS
/* setup local bus to PCI access (Cardbus memory) */
val = BCM_CB_MEM_BASE_PA & MPI_L2P_BASE_MASK;
bcm_mpi_writel(val, MPI_L2PMEMBASE2_REG);
bcm_mpi_writel(~(BCM_CB_MEM_SIZE - 1), MPI_L2PMEMRANGE2_REG);
val |= MPI_L2PREMAP_ENABLED_MASK | MPI_L2PREMAP_IS_CARDBUS_MASK;
bcm_mpi_writel(val, MPI_L2PMEMREMAP2_REG);
#else
/* disable second access windows */
bcm_mpi_writel(0, MPI_L2PMEMREMAP2_REG);
#endif
/* setup local bus to PCI access (IO memory), we have only 1
* IO window for both PCI and cardbus, but it cannot handle
* both at the same time, assume standard PCI for now, if
* cardbus card has IO zone, PCI fixup will change window to
* cardbus */
val = BCM_PCI_IO_BASE_PA & MPI_L2P_BASE_MASK;
bcm_mpi_writel(val, MPI_L2PIOBASE_REG);
bcm_mpi_writel(~(BCM_PCI_IO_SIZE - 1), MPI_L2PIORANGE_REG);
bcm_mpi_writel(val | MPI_L2PREMAP_ENABLED_MASK, MPI_L2PIOREMAP_REG);
/* enable PCI related GPIO pins */
bcm_mpi_writel(MPI_LOCBUSCTL_EN_PCI_GPIO_MASK, MPI_LOCBUSCTL_REG);
/* setup PCI to local bus access, used by PCI device to target
* local RAM while bus mastering */
bcm63xx_int_cfg_writel(0, PCI_BASE_ADDRESS_3);
if (BCMCPU_IS_6358())
val = MPI_SP0_REMAP_ENABLE_MASK;
else
val = 0;
bcm_mpi_writel(val, MPI_SP0_REMAP_REG);
bcm63xx_int_cfg_writel(0x0, PCI_BASE_ADDRESS_4);
bcm_mpi_writel(0, MPI_SP1_REMAP_REG);
mem_size = bcm63xx_get_memory_size();
/* 6348 before rev b0 exposes only 16 MB of RAM memory through
* PCI, throw a warning if we have more memory */
if (BCMCPU_IS_6348() && (bcm63xx_get_cpu_rev() & 0xf0) == 0xa0) {
if (mem_size > (16 * 1024 * 1024))
printk(KERN_WARNING "bcm63xx: this CPU "
"revision cannot handle more than 16MB "
"of RAM for PCI bus mastering\n");
} else {
/* setup sp0 range to local RAM size */
bcm_mpi_writel(~(mem_size - 1), MPI_SP0_RANGE_REG);
bcm_mpi_writel(0, MPI_SP1_RANGE_REG);
}
/* change host bridge retry counter to infinite number of
* retry, needed for some broadcom wifi cards with Silicon
* Backplane bus where access to srom seems very slow */
val = bcm63xx_int_cfg_readl(BCMPCI_REG_TIMERS);
val &= ~REG_TIMER_RETRY_MASK;
bcm63xx_int_cfg_writel(val, BCMPCI_REG_TIMERS);
/* enable memory decoder and bus mastering */
val = bcm63xx_int_cfg_readl(PCI_COMMAND);
val |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
bcm63xx_int_cfg_writel(val, PCI_COMMAND);
/* enable read prefetching & disable byte swapping for bus
* mastering transfers */
val = bcm_mpi_readl(MPI_PCIMODESEL_REG);
val &= ~MPI_PCIMODESEL_BAR1_NOSWAP_MASK;
val &= ~MPI_PCIMODESEL_BAR2_NOSWAP_MASK;
val &= ~MPI_PCIMODESEL_PREFETCH_MASK;
val |= (8 << MPI_PCIMODESEL_PREFETCH_SHIFT);
bcm_mpi_writel(val, MPI_PCIMODESEL_REG);
/* enable pci interrupt */
val = bcm_mpi_readl(MPI_LOCINT_REG);
val |= MPI_LOCINT_MASK(MPI_LOCINT_EXT_PCI_INT);
bcm_mpi_writel(val, MPI_LOCINT_REG);
register_pci_controller(&bcm63xx_controller);
#ifdef CONFIG_CARDBUS
register_pci_controller(&bcm63xx_cb_controller);
#endif
/* mark memory space used for IO mapping as reserved */
request_mem_region(BCM_PCI_IO_BASE_PA, BCM_PCI_IO_SIZE,
"bcm63xx PCI IO space");
return 0;
}
arch_initcall(bcm63xx_pci_init);

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#ifndef PCI_BCM63XX_H_
#define PCI_BCM63XX_H_
#include <bcm63xx_cpu.h>
#include <bcm63xx_io.h>
#include <bcm63xx_regs.h>
#include <bcm63xx_dev_pci.h>
/*
* Cardbus shares the PCI bus, but has no IDSEL, so a special id is
* reserved for it. If you have a standard PCI device at this id, you
* need to change the following definition.
*/
#define CARDBUS_PCI_IDSEL 0x8
/*
* defined in ops-bcm63xx.c
*/
extern struct pci_ops bcm63xx_pci_ops;
extern struct pci_ops bcm63xx_cb_ops;
/*
* defined in pci-bcm63xx.c
*/
extern void __iomem *pci_iospace_start;
#endif /* ! PCI_BCM63XX_H_ */