pinctrl: ingenic: Merge GPIO functionality
Merge the code of the gpio-ingenic driver into the pinctrl-ingenic driver. The reason behind this, is that the same hardware block handles both pin config / muxing and GPIO. ingenic_gpio_probe() have been marked as __init, but for the most part, the code is the exact same as what it was in the gpio-ingenic driver. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Paul Cercueil
Linus Walleij
parent
4717b11f80
commit
e72394e2ea
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@ -315,6 +315,8 @@ config PINCTRL_INGENIC
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select GENERIC_PINCONF
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select GENERIC_PINCTRL_GROUPS
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select GENERIC_PINMUX_FUNCTIONS
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select GPIOLIB
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select GPIOLIB_IRQCHIP
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select REGMAP_MMIO
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config PINCTRL_RK805
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@ -11,6 +11,7 @@
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/of_device.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/pinctrl/pinctrl.h>
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#include <linux/pinctrl/pinmux.h>
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@ -24,6 +25,9 @@
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#include "pinconf.h"
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#include "pinmux.h"
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#define GPIO_PIN 0x00
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#define GPIO_MSK 0x20
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#define JZ4740_GPIO_DATA 0x10
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#define JZ4740_GPIO_PULL_DIS 0x30
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#define JZ4740_GPIO_FUNC 0x40
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@ -33,7 +37,6 @@
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#define JZ4740_GPIO_FLAG 0x80
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#define JZ4770_GPIO_INT 0x10
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#define JZ4770_GPIO_MSK 0x20
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#define JZ4770_GPIO_PAT1 0x30
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#define JZ4770_GPIO_PAT0 0x40
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#define JZ4770_GPIO_FLAG 0x50
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@ -72,6 +75,13 @@ struct ingenic_pinctrl {
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const struct ingenic_chip_info *info;
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};
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struct ingenic_gpio_chip {
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struct ingenic_pinctrl *jzpc;
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struct gpio_chip gc;
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struct irq_chip irq_chip;
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unsigned int irq, reg_base;
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};
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static const u32 jz4740_pull_ups[4] = {
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0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
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};
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@ -438,6 +448,235 @@ static const struct ingenic_chip_info jz4770_chip_info = {
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.pull_downs = jz4770_pull_downs,
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};
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static u32 gpio_ingenic_read_reg(struct ingenic_gpio_chip *jzgc, u8 reg)
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{
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unsigned int val;
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regmap_read(jzgc->jzpc->map, jzgc->reg_base + reg, &val);
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return (u32) val;
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}
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static void gpio_ingenic_set_bit(struct ingenic_gpio_chip *jzgc,
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u8 reg, u8 offset, bool set)
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{
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if (set)
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reg = REG_SET(reg);
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else
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reg = REG_CLEAR(reg);
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regmap_write(jzgc->jzpc->map, jzgc->reg_base + reg, BIT(offset));
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}
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static inline bool ingenic_gpio_get_value(struct ingenic_gpio_chip *jzgc,
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u8 offset)
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{
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unsigned int val = gpio_ingenic_read_reg(jzgc, GPIO_PIN);
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return !!(val & BIT(offset));
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}
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static void ingenic_gpio_set_value(struct ingenic_gpio_chip *jzgc,
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u8 offset, int value)
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{
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if (jzgc->jzpc->version >= ID_JZ4770)
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gpio_ingenic_set_bit(jzgc, JZ4770_GPIO_PAT0, offset, !!value);
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else
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gpio_ingenic_set_bit(jzgc, JZ4740_GPIO_DATA, offset, !!value);
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}
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static void irq_set_type(struct ingenic_gpio_chip *jzgc,
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u8 offset, unsigned int type)
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{
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u8 reg1, reg2;
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if (jzgc->jzpc->version >= ID_JZ4770) {
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reg1 = JZ4770_GPIO_PAT1;
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reg2 = JZ4770_GPIO_PAT0;
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} else {
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reg1 = JZ4740_GPIO_TRIG;
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reg2 = JZ4740_GPIO_DIR;
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}
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switch (type) {
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case IRQ_TYPE_EDGE_RISING:
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gpio_ingenic_set_bit(jzgc, reg2, offset, true);
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gpio_ingenic_set_bit(jzgc, reg1, offset, true);
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break;
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case IRQ_TYPE_EDGE_FALLING:
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gpio_ingenic_set_bit(jzgc, reg2, offset, false);
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gpio_ingenic_set_bit(jzgc, reg1, offset, true);
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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gpio_ingenic_set_bit(jzgc, reg2, offset, true);
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gpio_ingenic_set_bit(jzgc, reg1, offset, false);
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break;
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case IRQ_TYPE_LEVEL_LOW:
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default:
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gpio_ingenic_set_bit(jzgc, reg2, offset, false);
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gpio_ingenic_set_bit(jzgc, reg1, offset, false);
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break;
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}
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}
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static void ingenic_gpio_irq_mask(struct irq_data *irqd)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
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struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
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gpio_ingenic_set_bit(jzgc, GPIO_MSK, irqd->hwirq, true);
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}
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static void ingenic_gpio_irq_unmask(struct irq_data *irqd)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
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struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
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gpio_ingenic_set_bit(jzgc, GPIO_MSK, irqd->hwirq, false);
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}
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static void ingenic_gpio_irq_enable(struct irq_data *irqd)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
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struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
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int irq = irqd->hwirq;
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if (jzgc->jzpc->version >= ID_JZ4770)
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gpio_ingenic_set_bit(jzgc, JZ4770_GPIO_INT, irq, true);
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else
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gpio_ingenic_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, true);
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ingenic_gpio_irq_unmask(irqd);
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}
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static void ingenic_gpio_irq_disable(struct irq_data *irqd)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
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struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
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int irq = irqd->hwirq;
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ingenic_gpio_irq_mask(irqd);
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if (jzgc->jzpc->version >= ID_JZ4770)
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gpio_ingenic_set_bit(jzgc, JZ4770_GPIO_INT, irq, false);
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else
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gpio_ingenic_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, false);
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}
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static void ingenic_gpio_irq_ack(struct irq_data *irqd)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
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struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
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int irq = irqd->hwirq;
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bool high;
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if (irqd_get_trigger_type(irqd) == IRQ_TYPE_EDGE_BOTH) {
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/*
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* Switch to an interrupt for the opposite edge to the one that
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* triggered the interrupt being ACKed.
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*/
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high = ingenic_gpio_get_value(jzgc, irq);
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if (high)
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irq_set_type(jzgc, irq, IRQ_TYPE_EDGE_FALLING);
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else
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irq_set_type(jzgc, irq, IRQ_TYPE_EDGE_RISING);
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}
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if (jzgc->jzpc->version >= ID_JZ4770)
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gpio_ingenic_set_bit(jzgc, JZ4770_GPIO_FLAG, irq, false);
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else
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gpio_ingenic_set_bit(jzgc, JZ4740_GPIO_DATA, irq, true);
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}
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static int ingenic_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
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struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
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switch (type) {
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case IRQ_TYPE_EDGE_BOTH:
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case IRQ_TYPE_EDGE_RISING:
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case IRQ_TYPE_EDGE_FALLING:
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irq_set_handler_locked(irqd, handle_edge_irq);
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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case IRQ_TYPE_LEVEL_LOW:
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irq_set_handler_locked(irqd, handle_level_irq);
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break;
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default:
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irq_set_handler_locked(irqd, handle_bad_irq);
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}
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if (type == IRQ_TYPE_EDGE_BOTH) {
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/*
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* The hardware does not support interrupts on both edges. The
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* best we can do is to set up a single-edge interrupt and then
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* switch to the opposing edge when ACKing the interrupt.
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*/
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bool high = ingenic_gpio_get_value(jzgc, irqd->hwirq);
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type = high ? IRQ_TYPE_EDGE_FALLING : IRQ_TYPE_EDGE_RISING;
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}
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irq_set_type(jzgc, irqd->hwirq, type);
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return 0;
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}
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static int ingenic_gpio_irq_set_wake(struct irq_data *irqd, unsigned int on)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
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struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
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return irq_set_irq_wake(jzgc->irq, on);
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}
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static void ingenic_gpio_irq_handler(struct irq_desc *desc)
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{
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struct gpio_chip *gc = irq_desc_get_handler_data(desc);
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struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
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struct irq_chip *irq_chip = irq_data_get_irq_chip(&desc->irq_data);
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unsigned long flag, i;
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chained_irq_enter(irq_chip, desc);
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if (jzgc->jzpc->version >= ID_JZ4770)
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flag = gpio_ingenic_read_reg(jzgc, JZ4770_GPIO_FLAG);
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else
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flag = gpio_ingenic_read_reg(jzgc, JZ4740_GPIO_FLAG);
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for_each_set_bit(i, &flag, 32)
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generic_handle_irq(irq_linear_revmap(gc->irq.domain, i));
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chained_irq_exit(irq_chip, desc);
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}
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static void ingenic_gpio_set(struct gpio_chip *gc,
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unsigned int offset, int value)
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{
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struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
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ingenic_gpio_set_value(jzgc, offset, value);
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}
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static int ingenic_gpio_get(struct gpio_chip *gc, unsigned int offset)
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{
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struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
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return (int) ingenic_gpio_get_value(jzgc, offset);
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}
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static int ingenic_gpio_direction_input(struct gpio_chip *gc,
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unsigned int offset)
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{
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return pinctrl_gpio_direction_input(gc->base + offset);
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}
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static int ingenic_gpio_direction_output(struct gpio_chip *gc,
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unsigned int offset, int value)
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{
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ingenic_gpio_set(gc, offset, value);
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return pinctrl_gpio_direction_output(gc->base + offset);
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}
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static inline void ingenic_config_pin(struct ingenic_pinctrl *jzpc,
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unsigned int pin, u8 reg, bool set)
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{
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@ -479,7 +718,7 @@ static int ingenic_pinmux_set_pin_fn(struct ingenic_pinctrl *jzpc,
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if (jzpc->version >= ID_JZ4770) {
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ingenic_config_pin(jzpc, pin, JZ4770_GPIO_INT, false);
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ingenic_config_pin(jzpc, pin, JZ4770_GPIO_MSK, false);
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ingenic_config_pin(jzpc, pin, GPIO_MSK, false);
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ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, func & 0x2);
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ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT0, func & 0x1);
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} else {
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@ -532,7 +771,7 @@ static int ingenic_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
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if (jzpc->version >= ID_JZ4770) {
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ingenic_config_pin(jzpc, pin, JZ4770_GPIO_INT, false);
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ingenic_config_pin(jzpc, pin, JZ4770_GPIO_MSK, true);
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ingenic_config_pin(jzpc, pin, GPIO_MSK, true);
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ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, input);
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} else {
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ingenic_config_pin(jzpc, pin, JZ4740_GPIO_SELECT, false);
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@ -717,6 +956,87 @@ static const struct of_device_id ingenic_pinctrl_of_match[] = {
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{},
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};
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static const struct of_device_id ingenic_gpio_of_match[] __initconst = {
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{ .compatible = "ingenic,jz4740-gpio", },
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{ .compatible = "ingenic,jz4770-gpio", },
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{ .compatible = "ingenic,jz4780-gpio", },
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{},
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};
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static int __init ingenic_gpio_probe(struct ingenic_pinctrl *jzpc,
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struct device_node *node)
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{
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struct ingenic_gpio_chip *jzgc;
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struct device *dev = jzpc->dev;
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unsigned int bank;
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int err;
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err = of_property_read_u32(node, "reg", &bank);
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if (err) {
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dev_err(dev, "Cannot read \"reg\" property: %i\n", err);
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return err;
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}
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jzgc = devm_kzalloc(dev, sizeof(*jzgc), GFP_KERNEL);
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if (!jzgc)
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return -ENOMEM;
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jzgc->jzpc = jzpc;
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jzgc->reg_base = bank * 0x100;
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jzgc->gc.label = devm_kasprintf(dev, GFP_KERNEL, "GPIO%c", 'A' + bank);
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if (!jzgc->gc.label)
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return -ENOMEM;
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/* DO NOT EXPAND THIS: FOR BACKWARD GPIO NUMBERSPACE COMPATIBIBILITY
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* ONLY: WORK TO TRANSITION CONSUMERS TO USE THE GPIO DESCRIPTOR API IN
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* <linux/gpio/consumer.h> INSTEAD.
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*/
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jzgc->gc.base = bank * 32;
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jzgc->gc.ngpio = 32;
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jzgc->gc.parent = dev;
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jzgc->gc.of_node = node;
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jzgc->gc.owner = THIS_MODULE;
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jzgc->gc.set = ingenic_gpio_set;
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jzgc->gc.get = ingenic_gpio_get;
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jzgc->gc.direction_input = ingenic_gpio_direction_input;
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jzgc->gc.direction_output = ingenic_gpio_direction_output;
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if (of_property_read_bool(node, "gpio-ranges")) {
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jzgc->gc.request = gpiochip_generic_request;
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jzgc->gc.free = gpiochip_generic_free;
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}
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err = devm_gpiochip_add_data(dev, &jzgc->gc, jzgc);
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if (err)
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return err;
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jzgc->irq = irq_of_parse_and_map(node, 0);
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if (!jzgc->irq)
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return -EINVAL;
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jzgc->irq_chip.name = jzgc->gc.label;
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jzgc->irq_chip.irq_enable = ingenic_gpio_irq_enable;
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jzgc->irq_chip.irq_disable = ingenic_gpio_irq_disable;
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jzgc->irq_chip.irq_unmask = ingenic_gpio_irq_unmask;
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jzgc->irq_chip.irq_mask = ingenic_gpio_irq_mask;
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jzgc->irq_chip.irq_ack = ingenic_gpio_irq_ack;
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jzgc->irq_chip.irq_set_type = ingenic_gpio_irq_set_type;
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jzgc->irq_chip.irq_set_wake = ingenic_gpio_irq_set_wake;
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jzgc->irq_chip.flags = IRQCHIP_MASK_ON_SUSPEND;
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err = gpiochip_irqchip_add(&jzgc->gc, &jzgc->irq_chip, 0,
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handle_level_irq, IRQ_TYPE_NONE);
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if (err)
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return err;
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gpiochip_set_chained_irqchip(&jzgc->gc, &jzgc->irq_chip,
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jzgc->irq, ingenic_gpio_irq_handler);
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return 0;
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}
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static int __init ingenic_pinctrl_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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@ -727,6 +1047,7 @@ static int __init ingenic_pinctrl_probe(struct platform_device *pdev)
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const struct of_device_id *of_id = of_match_device(
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ingenic_pinctrl_of_match, dev);
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const struct ingenic_chip_info *chip_info;
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struct device_node *node;
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unsigned int i;
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int err;
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@ -815,11 +1136,11 @@ static int __init ingenic_pinctrl_probe(struct platform_device *pdev)
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dev_set_drvdata(dev, jzpc->map);
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if (dev->of_node) {
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err = of_platform_populate(dev->of_node, NULL, NULL, dev);
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if (err) {
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dev_err(dev, "Failed to probe GPIO devices\n");
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return err;
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for_each_child_of_node(dev->of_node, node) {
|
||||
if (of_match_node(ingenic_gpio_of_match, node)) {
|
||||
err = ingenic_gpio_probe(jzpc, node);
|
||||
if (err)
|
||||
return err;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue