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MIPS: Allow emulation for unaligned [LS]DXC1 instructions 

If an address error exception occurs for a LDXC1 or SDXC1 instruction,
within the cop1x opcode space, allow it to be passed through to the FPU
emulator rather than resulting in a SIGILL. This causes LDXC1 & SDXC1 to
be handled in a manner consistent with the more common LDC1 & SDC1
instructions.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Tested-by: Aurelien Jarno <aurelien@aurel32.net>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/13143/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Paul Burton 2016-04-21 12:25:38 +01:00 committed by Ralf Baechle
parent abf378be49
commit e70ac023f9
1 changed files with 1 additions and 0 deletions
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arch/mips/kernel/unaligned.c
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@ -1191,6 +1191,7 @@ static void emulate_load_store_insn(struct pt_regs *regs,
case ldc1_op: case ldc1_op:
case swc1_op: case swc1_op:
case sdc1_op: case sdc1_op:
case cop1x_op:
die_if_kernel("Unaligned FP access in kernel code", regs); die_if_kernel("Unaligned FP access in kernel code", regs);
BUG_ON(!used_math()); BUG_ON(!used_math());